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Robertson Multiplier Map

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Feb 18th, 2017
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  1. Release 14.5 Map P.58f (nt64)
  2. Xilinx Mapping Report File for Design 'robertson'
  3.  
  4. Design Information
  5. ------------------
  6. Command Line : map -intstyle ise -p xc3s250e-tq144-4 -cm area -ir off -pr off
  7. -c 100 -o robertson_map.ncd robertson.ngd robertson.pcf
  8. Target Device : xc3s250e
  9. Target Package : tq144
  10. Target Speed : -4
  11. Mapper Version : spartan3e -- $Revision: 1.55 $
  12. Mapped Date : Fri Feb 10 12:58:01 2017
  13.  
  14. Design Summary
  15. --------------
  16. Number of errors: 0
  17. Number of warnings: 0
  18. Logic Utilization:
  19. Number of Slice Flip Flops: 35 out of 4,896 1%
  20. Number of 4 input LUTs: 73 out of 4,896 1%
  21. Logic Distribution:
  22. Number of occupied Slices: 46 out of 2,448 1%
  23. Number of Slices containing only related logic: 46 out of 46 100%
  24. Number of Slices containing unrelated logic: 0 out of 46 0%
  25. *See NOTES below for an explanation of the effects of unrelated logic.
  26. Total Number of 4 input LUTs: 73 out of 4,896 1%
  27. Number of bonded IOBs: 37 out of 108 34%
  28. Number of BUFGMUXs: 1 out of 24 4%
  29.  
  30. Average Fanout of Non-Clock Nets: 3.65
  31.  
  32. Peak Memory Usage: 246 MB
  33. Total REAL time to MAP completion: 2 secs
  34. Total CPU time to MAP completion: 1 secs
  35.  
  36. NOTES:
  37.  
  38. Related logic is defined as being logic that shares connectivity - e.g. two
  39. LUTs are "related" if they share common inputs. When assembling slices,
  40. Map gives priority to combine logic that is related. Doing so results in
  41. the best timing performance.
  42.  
  43. Unrelated logic shares no connectivity. Map will only begin packing
  44. unrelated logic into a slice once 99% of the slices are occupied through
  45. related logic packing.
  46.  
  47. Note that once logic distribution reaches the 99% level through related
  48. logic packing, this does not mean the device is completely utilized.
  49. Unrelated logic packing will then begin, continuing until all usable LUTs
  50. and FFs are occupied. Depending on your timing budget, increased levels of
  51. unrelated logic packing may adversely affect the overall timing performance
  52. of your design.
  53.  
  54. Table of Contents
  55. -----------------
  56. Section 1 - Errors
  57. Section 2 - Warnings
  58. Section 3 - Informational
  59. Section 4 - Removed Logic Summary
  60. Section 5 - Removed Logic
  61. Section 6 - IOB Properties
  62. Section 7 - RPMs
  63. Section 8 - Guide Report
  64. Section 9 - Area Group and Partition Summary
  65. Section 10 - Timing Report
  66. Section 11 - Configuration String Information
  67. Section 12 - Control Set Information
  68. Section 13 - Utilization by Hierarchy
  69.  
  70. Section 1 - Errors
  71. ------------------
  72.  
  73. Section 2 - Warnings
  74. --------------------
  75.  
  76. Section 3 - Informational
  77. -------------------------
  78. INFO:MapLib:562 - No environment variables are currently set.
  79. INFO:LIT:244 - All of the single ended outputs in this design are using slew
  80. rate limited output drivers. The delay on speed critical single ended outputs
  81. can be dramatically reduced by designating them as fast outputs.
  82.  
  83. Section 4 - Removed Logic Summary
  84. ---------------------------------
  85. 1 block(s) optimized away
  86. 1 signal(s) removed
  87.  
  88. Section 5 - Removed Logic
  89. -------------------------
  90.  
  91. The trimmed logic reported below is either:
  92. 1. part of a cycle
  93. 2. part of disabled logic
  94. 3. a side-effect of other trimmed logic
  95.  
  96. The signal "N1" is unused and has been removed.
  97.  
  98. Optimized Block(s):
  99. TYPE BLOCK
  100. VCC XST_VCC
  101.  
  102. To enable printing of redundant blocks removed and signals merged, set the
  103. detailed map report option and rerun map.
  104.  
  105. Section 6 - IOB Properties
  106. --------------------------
  107.  
  108. +---------------------------------------------------------------------------------------------------------------------------------------------------------+
  109. | IOB Name | Type | Direction | IO Standard | Diff | Drive | Slew | Reg (s) | Resistor | IOB |
  110. | | | | | Term | Strength | Rate | | | Delay |
  111. +---------------------------------------------------------------------------------------------------------------------------------------------------------+
  112. | X<0> | IBUF | INPUT | LVCMOS25 | | | | | | 0 / 0 |
  113. | X<1> | IBUF | INPUT | LVCMOS25 | | | | | | 0 / 0 |
  114. | X<2> | IBUF | INPUT | LVCMOS25 | | | | | | 0 / 0 |
  115. | X<3> | IBUF | INPUT | LVCMOS25 | | | | | | 0 / 0 |
  116. | X<4> | IBUF | INPUT | LVCMOS25 | | | | | | 0 / 0 |
  117. | X<5> | IBUF | INPUT | LVCMOS25 | | | | | | 0 / 0 |
  118. | X<6> | IBUF | INPUT | LVCMOS25 | | | | | | 0 / 0 |
  119. | X<7> | IBUF | INPUT | LVCMOS25 | | | | | | 0 / 0 |
  120. | Y<0> | IBUF | INPUT | LVCMOS25 | | | | | | 0 / 0 |
  121. | Y<1> | IBUF | INPUT | LVCMOS25 | | | | | | 0 / 0 |
  122. | Y<2> | IBUF | INPUT | LVCMOS25 | | | | | | 0 / 0 |
  123. | Y<3> | IBUF | INPUT | LVCMOS25 | | | | | | 0 / 0 |
  124. | Y<4> | IBUF | INPUT | LVCMOS25 | | | | | | 0 / 0 |
  125. | Y<5> | IBUF | INPUT | LVCMOS25 | | | | | | 0 / 0 |
  126. | Y<6> | IBUF | INPUT | LVCMOS25 | | | | | | 0 / 0 |
  127. | Y<7> | IBUF | INPUT | LVCMOS25 | | | | | | 0 / 0 |
  128. | clock | IBUF | INPUT | LVCMOS25 | | | | | | 0 / 0 |
  129. | error | IOB | OUTPUT | LVCMOS25 | | 12 | SLOW | | | 0 / 0 |
  130. | reset_n | IBUF | INPUT | LVCMOS25 | | | | | | 0 / 0 |
  131. | result<0> | IOB | OUTPUT | LVCMOS25 | | 12 | SLOW | | | 0 / 0 |
  132. | result<1> | IOB | OUTPUT | LVCMOS25 | | 12 | SLOW | | | 0 / 0 |
  133. | result<2> | IOB | OUTPUT | LVCMOS25 | | 12 | SLOW | | | 0 / 0 |
  134. | result<3> | IOB | OUTPUT | LVCMOS25 | | 12 | SLOW | | | 0 / 0 |
  135. | result<4> | IOB | OUTPUT | LVCMOS25 | | 12 | SLOW | | | 0 / 0 |
  136. | result<5> | IOB | OUTPUT | LVCMOS25 | | 12 | SLOW | | | 0 / 0 |
  137. | result<6> | IOB | OUTPUT | LVCMOS25 | | 12 | SLOW | | | 0 / 0 |
  138. | result<7> | IOB | OUTPUT | LVCMOS25 | | 12 | SLOW | | | 0 / 0 |
  139. | result<8> | IOB | OUTPUT | LVCMOS25 | | 12 | SLOW | | | 0 / 0 |
  140. | result<9> | IOB | OUTPUT | LVCMOS25 | | 12 | SLOW | | | 0 / 0 |
  141. | result<10> | IOB | OUTPUT | LVCMOS25 | | 12 | SLOW | | | 0 / 0 |
  142. | result<11> | IOB | OUTPUT | LVCMOS25 | | 12 | SLOW | | | 0 / 0 |
  143. | result<12> | IOB | OUTPUT | LVCMOS25 | | 12 | SLOW | | | 0 / 0 |
  144. | result<13> | IOB | OUTPUT | LVCMOS25 | | 12 | SLOW | | | 0 / 0 |
  145. | result<14> | IOB | OUTPUT | LVCMOS25 | | 12 | SLOW | | | 0 / 0 |
  146. | result<15> | IOB | OUTPUT | LVCMOS25 | | 12 | SLOW | | | 0 / 0 |
  147. | start | IBUF | INPUT | LVCMOS25 | | | | | | 0 / 0 |
  148. | stop | IOB | OUTPUT | LVCMOS25 | | 12 | SLOW | | | 0 / 0 |
  149. +---------------------------------------------------------------------------------------------------------------------------------------------------------+
  150.  
  151. Section 7 - RPMs
  152. ----------------
  153.  
  154. Section 8 - Guide Report
  155. ------------------------
  156. Guide not run on this design.
  157.  
  158. Section 9 - Area Group and Partition Summary
  159. --------------------------------------------
  160.  
  161. Partition Implementation Status
  162. -------------------------------
  163.  
  164. No Partitions were found in this design.
  165.  
  166. -------------------------------
  167.  
  168. Area Group Information
  169. ----------------------
  170.  
  171. No area groups were found in this design.
  172.  
  173. ----------------------
  174.  
  175. Section 10 - Timing Report
  176. --------------------------
  177. This design was not run using timing mode.
  178.  
  179. Section 11 - Configuration String Details
  180. -----------------------------------------
  181. Use the "-detail" map option to print out Configuration Strings
  182.  
  183. Section 12 - Control Set Information
  184. ------------------------------------
  185. No control set information for this architecture.
  186.  
  187. Section 13 - Utilization by Hierarchy
  188. -------------------------------------
  189. Use the "-detail" map option to print out the Utilization by Hierarchy section.
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