gd control 16-7-12 OzOnE

module control (
    SYSCLK, SDRAM_CLK_100M, RST_n,
    gd_sector_type, gd_start_sector, gd_sector_count, trig_block_read, block_dma_done,
    sector_data,
    cont_dma_rq, gd_dma_ack_n, gd_rd_n,

    SRAM_ADDR,
    SRAM_OE_n,
    SRAM_WE_n,
    SRAM_DATA,

    SDRAM_CLK,//connected to the clk port of SDRAM
    SDRAM_CKE,//connected to the cke port of SDRAM
    SDRAM_CS_n,//connected to the CS_n port of SDRAM
    SDRAM_RAS_n,//connected to the RAS_n port of SDRAM
    SDRAM_CAS_n,//connected to the CAS_n port of SDRAM
    SDRAM_WE_n,//connected to the WE_n port of SDRAM
    SDRAM_DQM,//connected to the LDQM port of SDRAM
    SDRAM_BA,//connected to the BA port of SDRAM
    SDRAM_ADDR,//connected to the ADDR port of SDRAM
    SDRAM_DQ,//connected to the DQ port of SDRAM
    SD_CS_n, SD_CLK, SD_DATA_IN, SD_DATA_OUT,
    AUD_BCLK,AUD_DACLRC,AUD_DACDAT,
    SEG_S, SEG,
    USB_TXE_n, USB_RXF_n, USB_RD_n, USB_WR, USB_DATA,
    error);

    input SYSCLK;
    input SDRAM_CLK_100M;

    input RST_n;

    output wire [18:0] SRAM_ADDR = (cont_dma_rq) ? DMA_ADDR : SRAM_ADDR_REG;
    output reg SRAM_WE_n;
    inout wire [15:0] SRAM_DATA = (!SRAM_WE_n) ? SRAM_DATA_WRITE : 19'hzzzzz;

    reg [18:0] DMA_ADDR;
    reg [18:0] SRAM_ADDR_REG;
    reg [15:0] SRAM_DATA_WRITE;


//  output wire SRAM_OE_n = (SRAM_WE_n) ? 1'b0 : 1'b1;      // Assert SRAM OE if SRAM_WE_n is NOT asserted!
    output reg SRAM_OE_n;

    input wire AUD_BCLK;
    input wire AUD_DACLRC;
    output wire AUD_DACDAT;

    input USB_TXE_n;
    input USB_RXF_n;
    output reg USB_RD_n;
    output reg USB_WR;
    inout [7:0] USB_DATA;

    output [3:0] SEG_S;
    output [7:0] SEG;

    output reg error;

// SDRAM pins and stuff...
    output SDRAM_CLK = SDRAM_CLK_100M;
    output SDRAM_CKE;
    output SDRAM_CS_n;
    output SDRAM_RAS_n;
    output SDRAM_CAS_n;
    output SDRAM_WE_n;
    output [1: 0] SDRAM_DQM;
    output [1 :0] SDRAM_BA;
    output [12:0] SDRAM_ADDR;
    inout  [15:0] SDRAM_DQ;

//  wire [1:0] Host_DQM = 2'b00;
//  wire [8:0] Host_Burst_Length = 2'b00;

    reg [23:0] Host_ADDR;           // SDRAM Address.

    reg Host_RD0_WR1;               // SDRAM Read / Write mode.
    reg SDRAM_trig_Host_command;

    reg SDRAM_Tx_fifo_clear;
    reg SDRAM_Tx_fifo_wrreq;
    reg [15:0] SDRAM_Tx_fifo_data;

    input wire [11:0] gd_sector_type;
    input wire [31:0] gd_start_sector;
    input wire [31:0] gd_sector_count;

    reg [31:0] gd_bytecount;        // Storage for bytecount, for current block of sector(s).

    reg [31:0] sd_bytecount/* synthesis noprune */;
    reg [31:0] dc_bytecount/* synthesis noprune */;

    input trig_block_read;
    output reg block_dma_done;

//  output reg [15:0] sector_data;

    output wire [15:0] sector_data = SRAM_DATA;

    output reg cont_dma_rq;     // When we're ready with the sector data, we assert "cont_dma_rq" (active high)...

    input gd_dma_ack_n;         // The Dreamcast will setup the IDE bus for DMA transfer, then assert "gd_dma_ack_n" (active low) when
                                // it's ready to receive the sector data.

    input gd_rd_n;              // We need this signal for counting the word transfers during DMA.

// SD interface pins and regs...
    output SD_CS_n;
    output SD_CLK;
    input  SD_DATA_IN;
    output SD_DATA_OUT;

    reg sd_rst_n;

    reg [2:0] Host_Command_Type;
    reg [31:0] Host_Command_Arg;
    reg trig_Host_Command;

    reg stop_mbr;       // My new signal for manually stopping the SD card Multiple Block Read.

    reg Rx_fifo_sclr;
    reg Rx_fifo_rdrq;
    reg Tx_fifo_wrrq;

    reg [9:0] state/* synthesis noprune */;

  parameter [2:0]//the definition of CMD Type
    CMD_Single_Block_Read     = 3'b000,
    CMD_Single_Block_Write    = 3'b001,
    CMD_Multiple_Block_Read   = 3'b010,
    CMD_Multiple_Block_Write  = 3'b011,
    CMD_Erase                 = 3'b100,
    CMD_Pre_Erase             = 3'b101,
    CMD_Read_CSD_CID_Rigister = 3'b110;

// GD Interface pins and regs...
//  reg gd_wr_n_1, gd_wr_n_2;   // Flip-flops for detecting async edges.
    reg gd_rd_n_1, gd_rd_n_2;

//  wire gd_wr_rising = gd_wr_n_1 & ~gd_wr_n_2;
    wire gd_rd_rising = gd_rd_n_1 & ~gd_rd_n_2;

    reg cont_dma_rq_1, cont_dma_rq_2;
    wire cont_dma_rq_rising = cont_dma_rq_1 & ~cont_dma_rq_2;

    reg gd_dma_ack_n_1, gd_dma_ack_n_2;
    wire gd_dma_ack_n_rising = gd_dma_ack_n_1 & ~gd_dma_ack_n_2;

//  wire gd_wr_falling = ~gd_wr_n_1 & gd_wr_n_2;
    wire gd_rd_falling = ~gd_rd_n_1 & gd_rd_n_2;

initial begin
    gd_bytecount <= 32'd0;  // Storage for requested bytecount, for current block of sector(s).

    sd_bytecount <= 32'd0;  // BYTE count from SD Card to SRAM.
    dc_bytecount <= 32'd0;  // BYTE count from SRAM to DC.

    stop_mbr <= 1'b0;

    az_rd_n_reg <= 1'b1;        // De-assert SDRAM block Read at power up! (active low)
    az_wr_n_reg <= 1'b1;        // De-assert SDRAM block WRite at power up! (active low)

    SDRAM_Rx_fifo_rdreq <= 1'b0;
    SDRAM_Rx_fifo_wrreq <= 1'b0;
    SDRAM_Rx_fifo_sclr <= 1'b0;

    cont_dma_rq <= 1'b0;
    block_dma_done <= 1'b0;

    trig_Host_Command <= 1'b0;

    sd_rst_n <= 1'b0;       // Reset the SD Card driver.

    Rx_fifo_sclr <= 1'b0;
    Rx_fifo_rdrq <= 1'b0;
    Tx_fifo_wrrq <= 1'b0;

    USB_RD_n <= 1'b1;
    USB_WR <= 1'b0;

    SRAM_ADDR_REG <= 19'b0;
    SRAM_OE_n <= 1'b1;          // De-assert SRAM Output Enable!
    SRAM_WE_n <= 1'b1;          // De-assert SRAM Write Enable!

    error <= 1'b0;
end

/*
always @(posedge cont_dma_rq_rising or posedge gd_rd_falling)
begin
    if (cont_dma_rq_rising) begin
//      DMA_ADDR <= 19'b1111111111111111111;    // Intentional wrap-around, so DMA_ADDR starts at zero on first falling edge of "gd_rd_n".
        dc_bytecount <= 32'hFFFFFFFE;           // Intentional wrap-around, so "dc_bytecount" starts at zero on first falling edge of "gd_rd_n".
    end
    else if (gd_rd_falling)
    begin
//      DMA_ADDR <= DMA_ADDR + 1;               // negedge of "gd_rd_n".
        dc_bytecount <= dc_bytecount + 2;   // Remember, a WORD is transferred from SRAM !!!
    end
end

assign DMA_ADDR = dc_bytecount[31:1];
*/

always @(posedge SYSCLK or negedge RST_n)
    if (!RST_n) begin
        state <= 10'd0;

        sd_bytecount <= 32'd0;  // BYTE count from SD Card to SRAM.
        dc_bytecount <= 32'd0;  // BYTE count from SRAM to DC.

        gd_bytecount <= 32'd0;  // Storage for requested bytecount, for current block of sector(s).

        stop_mbr <= 1'b0;

        az_rd_n_reg <= 1'b1;        // De-assert SDRAM block Read! (active low)
        az_wr_n_reg <= 1'b1;        // De-assert SDRAM block WRite! (active low)

        SDRAM_Rx_fifo_rdreq <= 1'b0;
        SDRAM_Rx_fifo_wrreq <= 1'b0;
        SDRAM_Rx_fifo_sclr <= 1'b0;

        cont_dma_rq <= 1'b0;
        block_dma_done <= 1'b0;

        trig_Host_Command <= 1'b0;

        sd_rst_n <= 1'b0;       // Reset the SD Card driver.

        Rx_fifo_sclr <= 1'b0;
        Rx_fifo_rdrq <= 1'b0;
        Tx_fifo_wrrq <= 1'b0;

        USB_RD_n <= 1'b1;
        USB_WR <= 1'b0;

        SRAM_ADDR_REG <= 19'b0;
        SRAM_OE_n <= 1'b1;          // De-assert SRAM Output Enable!
        SRAM_WE_n <= 1'b1;          // De-assert SRAM Write Enable!

        error <= 1'b0;
    end
    else begin

    gd_rd_n_1 <= gd_rd_n;       // Update edge regs on every clock.
    gd_rd_n_2 <= gd_rd_n_1;

    cont_dma_rq_1 <= cont_dma_rq;
    cont_dma_rq_2 <= cont_dma_rq_1;

    gd_dma_ack_n_1 <= gd_dma_ack_n;
    gd_dma_ack_n_2 <= gd_dma_ack_n_1;

    case (state)
            0: begin
                if (Error_Occur) error <= 1'b1;

                block_dma_done <= 1'b0;
                cont_dma_rq <= 1'b0;

                stop_mbr <= 1'b0;

                sd_rst_n <= 1'b1;       // Bring the SD Card driver out of reset!
                Rx_fifo_sclr <= 1'b1;   // Clear the SD Card receive FIFO.

                if (!trig_block_read) state <= 10'd1;   // Make sure "trig_block_read" is low before starting!
//              state <= 10'd1;             // TESTING audio streaming !!
            end

            1: begin
                Rx_fifo_sclr <= 1'b0;
                Rx_fifo_rdrq <= 1'b0;       // Sanity check.

                if (trig_block_read) state <= 10'd2;

//              Host_Command_Arg <= 32'd0;  // TESTING audio streaming !!
//              state <= 10'd2;             // TESTING audio streaming !!
            end

            2: if (!SD_driver_busy) begin
                gd_bytecount <= gd_sector_count * 2048; // 2048 Bytes per GD sector.

//              gd_bytecount <= 7056000;                // TESTING audio streaming !! (20 seconds worth at 44100Hz).

                sd_bytecount <= 32'd0;
                dc_bytecount <= 32'd0;

//              Host_ADDR <= 24'h000000;        // Set SDRAM start Address.

                SRAM_ADDR_REG <= 19'h000000;        // Set SRAM start Address.

            if (CCS)    // This should be HIGH if SD Card is SDHC.
                Host_Command_Arg <= (gd_start_sector - 45150) * 4;  // SDHC cards use 512-byte SECTOR addressing - Need to multiply the GD sector offset by 4.
            else
                Host_Command_Arg <= (gd_start_sector - 45150) * 2048;   // Low-density SD Cards use BYTE addressing - Need to multiply the GD sector offset by 2048.

                Host_Command_Type <= CMD_Multiple_Block_Read;
                trig_Host_Command <= 1'b1;

                state <= 10'd3;
            end

            3: begin
                trig_Host_Command <= 1'b0;      // Remember to only strobe "trig_Host_command" for ONE clock!!
                state <= 10'd4;
            end

            4: if (Rx_fifo_almost_full) begin       // Wait until SD Card Rx FIFO is almost full before starting DMA.

                Rx_fifo_rdrq <= 1'b1;               // SKIP first byte from SD Card! ???
                state <= 10'd5;
            end

            5: begin
                Rx_fifo_rdrq <= 1'b0;

                state <= 10'd6;
//              state <= 10'd12;                // TESTING audio streaming !!
            end

            6: if (!Rx_fifo_empty) begin
                    Rx_fifo_rdrq <= 1'b1;
                    state <= 10'd7;
                end

// Grab the MSB Byte from SD Card...
            7: begin                                        // SD Card Rx FIFO should contain some bytes at this point!
                SRAM_DATA_WRITE[15:8] <= Rx_fifo_q;         // Read MSB byte from SD Card into SRAM data reg. (don't write yet!)
                sd_bytecount <= sd_bytecount + 1'b1;        // Increment SD Card byte count.

                Rx_fifo_rdrq <= 1'b0;                       // De-assert SD Card FIFO Read ReQuest.
                state <= 10'd8;
            end

            8: if (!Rx_fifo_empty) begin
                    Rx_fifo_rdrq <= 1'b1;
                    state <= 10'd9;
                end

// Grab the LSB Byte from SD Card...
            9: begin
                SRAM_DATA_WRITE[7:0] <= Rx_fifo_q;          // Read LSB byte from SD Card into SRAM data reg...
                sd_bytecount <= sd_bytecount + 1'b1;        // Increment byte count.

                SRAM_WE_n <= 1'b0;                          // Write the WORD to SRAM...

                Rx_fifo_rdrq <= 1'b0;                       // De-assert SD Card FIFO Read ReQuest.
                state <= 10'd10;
            end

            10: begin
                SRAM_WE_n <= 1'b1;                          // De-assert SRAM Write Enable (Data is latched on RISING edge).

                if (sd_bytecount == gd_bytecount) begin     // Check if all bytes / words transferred from SD Card to SRAM...
                    DMA_ADDR <= 19'h00000;                  // Let DC start reading from start of SRAM.
                    SRAM_OE_n <= 1'b0;                      // Assert SRAM Output Enable!
                    state <= 10'd11;
                end
                else begin                                  // Else, keep reading in bytes from SD.
                    SRAM_ADDR_REG <= SRAM_ADDR_REG + 1'b1;
                    state <= 10'd6;
                end
            end

            11: begin
                cont_dma_rq <= 1'b1;            // Start the DMA transfer.

                if (gd_rd_falling) begin    // Skip first falling edge! (so SRAM / DMA addr starts at zero!)
                    dc_bytecount <= dc_bytecount + 2'd2;    // Inc "dc_bytecount" anyway (so it's not zero-based)
                    state <= 10'd12;
                end
            end

            12: begin
                if (gd_rd_falling) begin    // If "gd_rd_n" is asserted...
                    DMA_ADDR <= DMA_ADDR + 1'b1;
                    dc_bytecount <= dc_bytecount + 2'd2;    // Remember, a WORD is transferred from SRAM !!!
                end

                // NOTE: Byte / Word counting definitely does NOT work reliably when running at 100MHz SYSCLK! 50MHz seems better. OzOnE.
                if (gd_dma_ack_n_rising && !(dc_bytecount[4:0] == 5'b00000) ) begin // "dc_bytecount" should be multiple of 32 when "gd_dma_ack_n" goes high!
                    error <= 1'b1;
                    sd_bytecount <= dc_bytecount;   // DEBUG - Use "sd_bytecount" to store the position (ie. the chunk of 16 Words) where the error occured.
                end

                if (dc_bytecount == gd_bytecount) begin     // Have all Words / Sectors been transferred?...
                    state <= 10'd13;
                end
            end

// Finish the DMA transfer...
            13: if (gd_dma_ack_n) begin     // Wait for DC to de-assert "gd_dma_ack_n" (HIGH).
                cont_dma_rq <= 1'b0;        // Finish DMA transfer!
                block_dma_done <= 1'b1;     // Tell the GD_EMU block that we're finished.

                SRAM_OE_n <= 1'b1;          // De-assert SRAM Output Enable.

                stop_mbr <= 1'b1;
                sd_rst_n <= 1'b0;           // Reset the SD Card driver.
                Rx_fifo_rdrq <= 1'b0;       // Sanity check.

                state <= 10'd0;             // All Words transferred! - back to idle.
            end


    default: state <= 10'd1;
    endcase
end     // End for main loop!


wire Tx_fifo_sclr;
wire [7:0] Tx_fifo_data;
wire Tx_fifo_empty;
wire Tx_fifo_full;
wire [7:0] Rx_fifo_q;
wire Rx_fifo_almost_empty;
wire Rx_fifo_empty;
wire Rx_fifo_almost_full;
wire Rx_fifo_full;
wire [8:0] Rx_fifo_usedw;
wire CCS;
wire SD_driver_busy;
wire Error_Occur;

  SD_Card_driver U_SD_Card_driver(
    .CLK50M(SYSCLK),//Main clock
    .RST_n(sd_rst_n),//reset signal

    .trig_Host_Command(trig_Host_Command),//Used for the host to trig a command,synchronous to "SYSCLK"
    .Host_Command_Type(Host_Command_Type),//Express the command type,synchronous to "SYSCLK"
    .Host_Command_Arg(Host_Command_Arg),//The argument of a certain command(if needed),synchronous to "SYSCLK"
    .Tx_fifo_sclr(Tx_fifo_sclr),//the Host's synchronous clear to the Tx_fifo,synchronous to "SYSCLK"
    .Tx_fifo_wrrq(Tx_fifo_wrrq),//the Host's write require to the Tx_fifo,synchronous to "SYSCLK"
    .Tx_fifo_data(Tx_fifo_data),//the Host's write data to the Tx_fifo,synchronous to "SYSCLK"
    .Tx_fifo_empty(Tx_fifo_empty),//output signal to tell the Host that the Tx_fifo is empty,synchronous to "SYSCLK"
    .Tx_fifo_full(Tx_fifo_full),//output signal to tell the Host that the Tx_fifo is full,synchronous to "SYSCLK"
    .Rx_fifo_sclr(Rx_fifo_sclr),//the Host's synchronous clear to the Rx_fifo,synchronous to "SYSCLK"
    .Rx_fifo_rdrq(Rx_fifo_rdrq),//the Host's read require to the Rx_fifo,synchronous to "SYSCLK"
    .Rx_fifo_q(Rx_fifo_q),//the Rx_fifo output data to the Host,synchronous to "SYSCLK"
    .Rx_fifo_almost_empty(Rx_fifo_almost_empty),
    .Rx_fifo_empty(Rx_fifo_empty),//output signal to tell the Host that the Rx_fifo is empty,synchronous to "SYSCLK"
    .Rx_fifo_almost_full(Rx_fifo_almost_full),
    .Rx_fifo_full(Rx_fifo_full),//output signal to tell the Host that the Rx_fifo is full,synchronous to "SYSCLK"
    .Rx_fifo_usedw(Rx_fifo_usedw),

    .stop_mbr(stop_mbr),

    .SD_CS_n(SD_CS_n),//
    .SD_CLK(SD_CLK),//
    .SD_DATA_IN(SD_DATA_IN),//
    .SD_DATA_OUT(SD_DATA_OUT),//

    .CCS(CCS),
    .SD_driver_busy(SD_driver_busy),
    .Error_Occur(Error_Occur)
  );



wire SDRAM_BUSY;
wire SDRAM_data_valid;
wire [15:0] SDRAM_RD_data;

reg [15:0] az_data;
reg az_rd_n_reg;
reg az_wr_n_reg;
wire [12:0] SDRAM_ADDR;

  sdram sdram_inst
(                                       // ** Control inputs to SDRAM block. **
    .az_addr(Host_ADDR) ,               // input [23:0] az_addr
    .az_be_n(2'b00) ,                   // input [1:0] az_be_n
    .az_cs(1'b1) ,                      // input  az_cs
    .az_data(az_data) ,                 // input [15:0] az_data FROM SD Card.
    .az_rd_n(az_rd_n_reg) ,             // input  az_rd_n
    .az_wr_n(az_wr_n_reg) ,             // input  az_wr_n

                                        // ** Clock and reset for SDRAM (controller!) **
    .clk(SYSCLK) ,                      // input  clk
    .reset_n(RST_n) ,                   // input  reset_n

                                        // ** Control outputs from SDRAM block. **
    .za_data(SDRAM_RD_data) ,           // output [15:0] za_data TO Rx FIFO.
    .za_valid(SDRAM_data_valid) ,       // output  za_valid
    .za_waitrequest(SDRAM_BUSY) ,       // output  za_waitrequest

                                        // ** Connections to SDRAM itself. **
    .zs_addr(SDRAM_ADDR) ,                  // output [12:0] zs_addr
    .zs_ba(SDRAM_BA) ,                      // output [1:0] zs_ba
    .zs_cas_n(SDRAM_CAS_n) ,                // output  zs_cas_n
    .zs_cke(SDRAM_CKE) ,                    // output  zs_cke
    .zs_cs_n(SDRAM_CS_n) ,                  // output  zs_cs_n
    .zs_dq(SDRAM_DQ) ,                      // inout [15:0] zs_dq
    .zs_dqm(SDRAM_DQM) ,                    // output [1:0] zs_dqm
    .zs_ras_n(SDRAM_RAS_n) ,                // output  zs_ras_n
    .zs_we_n(SDRAM_WE_n)                    // output  zs_we_n
);


reg SDRAM_Rx_fifo_rdreq;
reg SDRAM_Rx_fifo_sclr;
reg SDRAM_Rx_fifo_wrreq;
wire SDRAM_Rx_fifo_empty;
wire SDRAM_Rx_fifo_full;
wire [15:0] SDRAM_Rx_data;
wire [8:0] SDRAM_Rx_used;
SDRAM_Rx_fifo sdram_rx_fifo_inst
(
    .clock(SYSCLK),
    .data(SDRAM_RD_data),           // Input data FROM SDRAM.
    .rdreq(SDRAM_Rx_fifo_rdreq),
    .sclr(SDRAM_Rx_fifo_sclr),
    .wrreq(SDRAM_Rx_fifo_wrreq),
    .empty(SDRAM_Rx_fifo_empty),
    .full(SDRAM_Rx_fifo_full),
    .q(SDRAM_Rx_data),              // Output data TO DC.
    .usedw(SDRAM_Rx_used)
);


reg [15:0] DAC_Left_channel_data;
reg [15:0] DAC_Right_channel_data;
wire [31:0] DAC_fifo_data = {DAC_Left_channel_data ,DAC_Right_channel_data};

reg DAC_fifo_wrreq;
wire DAC_fifo_empty;
wire DAC_fifo_full;
Audio_DAC_DSP_Control Audio_DAC_DSP_Control_inst (
   .CLK50M(SYSCLK),
   .RST_n(RST_n),

   .BCLK(AUD_BCLK),
   .DACLRC(AUD_DACLRC),
   .DACDAT(AUD_DACDAT),

   .DAC_fifo_wrreq(DAC_fifo_wrreq),
   .DAC_fifo_data(DAC_fifo_data),
   .DAC_fifo_empty(DAC_fifo_empty),
   .DAC_fifo_full(DAC_fifo_full)
);

//wire [15:0] seg_data = dc_bytecount[15:0];    // Note, can only see 16-bits on 7-SEG display!
wire [15:0] seg_data = {Rx_fifo_usedw[8:0], state[6:0]};    // Note, can only see 16-bits on 7-SEG display!
wire [3:0] dp = 4'b0;
  DYN_SEG U_DYN_SEG(
    .clk(SYSCLK),
    .data(seg_data),
    .dp(dp),
    .SEG_S(SEG_S),
    .SEG(SEG)
  );

endmodule