module wb_ram
  #(//Wishbone parameters
    parameter dw    = 32,

    //Memory parameters
    parameter depth = 256,
    parameter aw    = $clog2(depth))
   (input           wb_clk_i,
    input           wb_rst_i,

    input  [aw-1:0] wb_adr_i,
    input  [dw-1:0] wb_dat_i,
    input     [3:0] wb_sel_i,
    input           wb_we_i,
    input     [1:0] wb_bte_i,
    input     [2:0] wb_cti_i,
    input           wb_cyc_i,
    input           wb_stb_i,

    output reg      wb_ack_o,
    output          wb_err_o,
    output [dw-1:0] wb_dat_o);

reg  [aw-1:0] adr_r;
wire [aw-1:0] next_adr;

wire valid = wb_cyc_i & wb_stb_i;

reg valid_r;

wire new_cycle = valid  & !valid_r;

wb_next_adr #(.aw(aw)) wb_next_adr0(adr_r, wb_cti_i, wb_bte_i, next_adr);

wire [aw-1:0] adr = new_cycle ? wb_adr_i : next_adr;


always@(posedge wb_clk_i) begin
  adr_r <= adr;
  valid_r <= valid;

  //Ack generation
  wb_ack_o <= valid & (!((wb_cti_i == 3'b000) | (wb_cti_i == 3'b111)) | !wb_ack_o);
end

wire ram_we = wb_we_i & valid & wb_ack_o;

//TODO: Check for burst address errors
assign wb_err_o =  1'b0;

wb_ram_generic
  #(.aw (aw),
     .depth(depth))
ram0
  (.clk (wb_clk_i),
   .we  ({4{ram_we}} & wb_sel_i),
   .din (wb_dat_i),
    //.addr(new_cycle ? wb_adr_i : ram_we ? adr : next_adr),
    .addr(ram_we ? adr_r : adr),
   .dout (wb_dat_o));

endmodule