library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;

library work;
use work.all;

entity chooser is
    port(
        clk, rst : in std_logic;
        DATA : in std_logic_vector(4 downto 0);
        A : out std_logic_vector(4 downto 0);
        Src : in std_logic_vector(1 downto 0);
        SOp : in std_logic_vector(1 downto 0);
        debug : out std_logic_vector(4 downto 0)
    );
end entity;

architecture structural of chooser is
-- here
begin

end architecture;

library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;

entity MUX3x5 is
    port(
        IN0 : in std_logic_vector(4 downto 0);
        IN1 : in std_logic_vector(4 downto 0);
        IN2 : in std_logic_vector(4 downto 0);
        SEL : in std_logic_vector(1 downto 0);
        O : out std_logic_vector(4 downto 0)
    );
end entity;

architecture behaviour of MUX3x5 is

begin

    with SEl select O <=
        IN0 when "00",
        IN1 when "01",
        IN2 when others;

end architecture;

architecture structural of chooser is

signal -- signals here


-- copy of the inputs/outputs in the entity declaration in the file above
component MUX3x5 is
    port(
        IN0 : in std_logic_vector(4 downto 0);
        IN1 : in std_logic_vector(4 downto 0);
        IN2 : in std_logic_vector(4 downto 0);
        SEL : in std_logic_vector(1 downto 0);
        O   : out std_logic_vector(4 downto 0)
    );
end component;


component registry is
    port(
         -- some signals here
         TS : out TS std_logic_vector(4 downto 0)
    );

begin

-- port map here
    port map(
            TS => IN1;
            -- other maps
);