library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;

use work.core_pack.all;
use work.op_pack.all;

entity fwd is
	port (
		clk : in std_logic;
		reset : in std_logic;
		stall : in std_logic;
		exec_op_de : in exec_op_type; --output of decode, contains rs and rt
		rd_em : in std_logic_vector(REG_BITS-1 downto 0); --output of execute
		wb_op_em : in wb_op_type; --contains regwrite
		rd_mw : in std_logic_vector(REG_BITS-1 downto 0); --output of execute
		wb_op_mw : in wb_op_type; --contains regwrite
		mem_aluresult_in : in std_logic_vector(DATA_WIDTH-1 downto 0);
		wb_result_in : in std_logic_vector(DATA_WIDTH-1 downto 0);
		mem_aluresult_out : out std_logic_vector(DATA_WIDTH-1 downto 0);
		wb_result_out : out std_logic_vector(DATA_WIDTH-1 downto 0);
		forwardA : out fwd_type;
		forwardB : out fwd_type
);

end fwd;

architecture rtl of fwd is



begin  -- rtl

	process(mem_aluresult_in, wb_result_in, wb_op_em, wb_op_mw, rd_em, rd_mw, exec_op_de, reset, stall)
	begin
		if reset = '0' then
			forwardA <= FWD_NONE;
			forwardB <= FWD_NONE;
			mem_aluresult_out <= (others => '0');
			wb_result_out <= (others => '0');
		else
			if stall = '0' then
				forwardA <= FWD_NONE;
				forwardB <= FWD_NONE;
				mem_aluresult_out <= mem_aluresult_in;
				wb_result_out <= wb_result_in;

				----------- EX Harzard -------------
				if (wb_op_em.regwrite = '1') and (rd_em /= (REG_BITS-1 downto 0 => '0')) and (rd_em = exec_op_de.rs) then
						forwardA <= FWD_ALU;
				end if;
				if (wb_op_em.regwrite = '1') and (rd_em /= (REG_BITS-1 downto 0 => '0')) and (rd_em = exec_op_de.rt) then
					forwardB <= FWD_ALU;
				end if;
				----------- END EX Harzard -------------
				----------- MEM Harzard -------------
				if (wb_op_mw.regwrite = '1') and (rd_mw /= (REG_BITS-1 downto 0 => '0')) and not((wb_op_em.regwrite = '1') and (rd_em /= (REG_BITS-1 downto 0 => '0')) and (rd_em = exec_op_de.rs)) and (rd_mw = exec_op_de.rs) then
					forwardA <= FWD_WB;
				end if;
				if (wb_op_mw.regwrite = '1') and (rd_mw /= (REG_BITS-1 downto 0 => '0')) and not((wb_op_em.regwrite = '1') and (rd_em /= (REG_BITS-1 downto 0 => '0')) and (rd_em = exec_op_de.rt)) and (rd_mw = exec_op_de.rt) then
					forwardB <= FWD_WB;
				end if;
				----------- END MEM Harzard -------------

			end if;
		end if;
	end process;

end rtl;