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ivosexa

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Oct 23rd, 2014
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  1. #include <avr/io.h>
  2. #include <avr/interrupt.h>
  3.  
  4.  
  5. volatile data;
  6.  
  7. int main (void)
  8. {
  9. DDRD |= (1<<PD0);
  10. PORTD |= 0x00;
  11.  
  12. DDRB &= ~((1<<2)|(1<<3)|(1<<5)); // SCK, MOSI and SS as inputs
  13. DDRB |= (1<<4); // MISO as output
  14.  
  15. SPCR &= ~(1<<MSTR); // Set as slave
  16. SPCR |= (1<<SPR0)|(1<<SPR1); // divide clock by 128
  17. SPCR |= (1<<SPIE); // Enable SPI Interrupt
  18. SPCR |= (1<<SPE); // Enable SPI
  19.  
  20. sei();
  21.  
  22. while(1)
  23. {
  24.  
  25. }
  26. }
  27.  
  28. ISR (SPI_STC_vect)
  29. {
  30. data = SPDR;
  31. PORTD ^= (1<<PD0);
  32.  
  33. }
  34.  
  35.  
  36.  
  37.  
  38. #include <avr/io.h>
  39. #include <avr/interrupt.h>
  40.  
  41. volatile data;
  42.  
  43. int main (void)
  44. {
  45. char blah;
  46.  
  47. DDRB |= (1<<2)|(1<<3)|(1<<5); // SCK, MOSI and SS as outputs
  48. DDRB &= ~(1<<4); // MISO as input
  49.  
  50. SPCR |= (1<<MSTR); // Set as Master
  51. SPCR |= (1<<SPR0)|(1<<SPR1); // divided clock by 128
  52. SPCR |= (1<<SPIE); // Enable SPI Interrupt
  53. SPCR |= (1<<SPE); // Enable SPI
  54.  
  55.  
  56. sei();
  57.  
  58. while(1)
  59. {
  60. if ((SPSR & (1<<SPIF)) > 0) // checks to see if the SPI bit is clear
  61. data=blah; // send the data
  62.  
  63.  
  64. }
  65. }
  66.  
  67.  
  68. ISR (SPI_STC_vect)
  69. {
  70. SPDR = data;
  71. }
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