lab3_3

`timescale 1ns / 1ps

module Lab4_3(
	input  wire clk,
	input  wire rst,
	input  wire mosi,
	output wire miso,
	output wire [7:0] ld

    );
localparam INIT = 2'd0;
localparam ON   = 2'd1;
localparam OFF  = 2'd2;

reg [1:0] state;
wire		 blink= mosi;

always @ ( posedge clk)
begin
	if(rst)
		state <= INIT;
	else
		case ( state)
				INIT :  if (blink)
				state <= ON;
				else state <= INIT ;
				ON   :  state <= OFF;
				OFF  : if (blink)
				state <= ON;
				else state <= INIT ;

				default: state <= INIT;
		endcase
end

// kimenetek meghajtása
assign miso = (state == ON);
assign ld   = {8{(state == ON)}};

endmodule