/*
All required functionality for Lab 1 except some of the oscilloscope (in main file)

*/


//Frequency dividor
module Generate_Custom_Clock (clk, divid, out_clk);

input clk;
input [31:0] divid;
output reg out_clk;
reg [49:0] counter; //to make sure there is enough space for any clock division, 50 may be an overkill lel

always_ff @(posedge clk) begin

	if(counter >= divid) begin //if we just have == condition then if divid switches from higher value to low, we get stuck
		out_clk <= ~out_clk;
		counter <= 1;
		end
	else begin
		counter <= counter + 1;
		end
end
endmodule





//LED cycling
//We toggle LED cycling mode when we SW4 is hot and SW3,2,1 are off
//To reset we press and release KEY3
module LED_cycle(clk, switches, LED, rst);
input clk;
input [3:0] switches;
input rst;
output reg [7:0] LED = 8'b000_000_01;

always_ff @(posedge clk) begin

if (switches == 4'b1000) begin
	LED = LED *2; end
else if (switches == 4'b1000 && LED == 8'b100_000_00) begin
		LED = LED / 2;
	end
	//if (LED == 8'b000_000_00) begin //when we reach the end of the line, we overflow LED vector and it turns to 0
	//then we get stuck because 0*2 = 0, so we need to change 0 to 1
		//LED = 8'b000_000_01;
		//end

if (!rst) begin
	LED = 8'b000_000_01;
	end
end

endmodule



//Toggle audio ON/OFF with switch 0
module audio_output (switch, audio_data, data);
input switch;
input data;
output reg [7:0] audio_data;

always_comb
	case(switch)
	1'b0: audio_data = 0;
	default: audio_data = {(~data),{7{data}}};
	endcase
endmodule


//Logic for dividing clock to produce specified notes based on switch positions

module organ(switches, divid);
input [3:0] switches;
output reg [31:0] divid;
always_comb
	case(switches)
	4'b0000: divid = `Do;
	4'b0001: divid = `Re;
	4'b0010: divid = `Mi;
	4'b0011: divid = `Fa;
	4'b0100: divid = `So;
	4'b0101: divid = `La;
	4'b0110: divid = `Si;
	4'b0111: divid = `Do2;
	4'b1000: divid = `OneHz;
	default: divid = `OnekHZ;
	endcase
endmodule