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sun6i-a31.dtsi

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  1. /*
  2. * Copyright 2013 Maxime Ripard
  3. *
  4. * Maxime Ripard <maxime.ripard@free-electrons.com>
  5. *
  6. * This file is dual-licensed: you can use it either under the terms
  7. * of the GPL or the X11 license, at your option. Note that this dual
  8. * licensing only applies to this file, and not this project as a
  9. * whole.
  10. *
  11. * a) This file is free software; you can redistribute it and/or
  12. * modify it under the terms of the GNU General Public License as
  13. * published by the Free Software Foundation; either version 2 of the
  14. * License, or (at your option) any later version.
  15. *
  16. * This file is distributed in the hope that it will be useful,
  17. * but WITHOUT ANY WARRANTY; without even the implied warranty of
  18. * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
  19. * GNU General Public License for more details.
  20. *
  21. * Or, alternatively,
  22. *
  23. * b) Permission is hereby granted, free of charge, to any person
  24. * obtaining a copy of this software and associated documentation
  25. * files (the "Software"), to deal in the Software without
  26. * restriction, including without limitation the rights to use,
  27. * copy, modify, merge, publish, distribute, sublicense, and/or
  28. * sell copies of the Software, and to permit persons to whom the
  29. * Software is furnished to do so, subject to the following
  30. * conditions:
  31. *
  32. * The above copyright notice and this permission notice shall be
  33. * included in all copies or substantial portions of the Software.
  34. *
  35. * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
  36. * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
  37. * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
  38. * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT
  39. * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
  40. * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
  41. * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
  42. * OTHER DEALINGS IN THE SOFTWARE.
  43. */
  44.  
  45. #include "skeleton.dtsi"
  46.  
  47. #include <dt-bindings/clock/sun4i-a10-pll2.h>
  48. #include <dt-bindings/interrupt-controller/arm-gic.h>
  49. #include <dt-bindings/thermal/thermal.h>
  50.  
  51. #include <dt-bindings/pinctrl/sun4i-a10.h>
  52.  
  53. / {
  54. interrupt-parent = <&gic>;
  55.  
  56. aliases {
  57. ethernet0 = &gmac;
  58. };
  59.  
  60. chosen {
  61. #address-cells = <1>;
  62. #size-cells = <1>;
  63. ranges;
  64.  
  65. simplefb_hdmi: framebuffer@0 {
  66. compatible = "allwinner,simple-framebuffer",
  67. "simple-framebuffer";
  68. allwinner,pipeline = "de_be0-lcd0-hdmi";
  69. clocks = <&pll6 0>;
  70. status = "disabled";
  71. };
  72.  
  73. simplefb_lcd: framebuffer@1 {
  74. compatible = "allwinner,simple-framebuffer",
  75. "simple-framebuffer";
  76. allwinner,pipeline = "de_be0-lcd0";
  77. clocks = <&pll6 0>;
  78. status = "disabled";
  79. };
  80. };
  81.  
  82. timer {
  83. compatible = "arm,armv7-timer";
  84. interrupts = <GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>,
  85. <GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>,
  86. <GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>,
  87. <GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>;
  88. clock-frequency = <24000000>;
  89. arm,cpu-registers-not-fw-configured;
  90. };
  91.  
  92. cpus {
  93. enable-method = "allwinner,sun6i-a31";
  94. #address-cells = <1>;
  95. #size-cells = <0>;
  96.  
  97. cpu0: cpu@0 {
  98. compatible = "arm,cortex-a7";
  99. device_type = "cpu";
  100. reg = <0>;
  101. clocks = <&cpu>;
  102. clock-latency = <244144>; /* 8 32k periods */
  103. operating-points = <
  104. /* kHz uV */
  105. 1008000 1200000
  106. 864000 1200000
  107. 720000 1100000
  108. 480000 1000000
  109. >;
  110. #cooling-cells = <2>;
  111. cooling-min-level = <0>;
  112. cooling-max-level = <3>;
  113. };
  114.  
  115. cpu@1 {
  116. compatible = "arm,cortex-a7";
  117. device_type = "cpu";
  118. reg = <1>;
  119. };
  120.  
  121. cpu@2 {
  122. compatible = "arm,cortex-a7";
  123. device_type = "cpu";
  124. reg = <2>;
  125. };
  126.  
  127. cpu@3 {
  128. compatible = "arm,cortex-a7";
  129. device_type = "cpu";
  130. reg = <3>;
  131. };
  132. };
  133.  
  134. thermal-zones {
  135. cpu_thermal {
  136. /* milliseconds */
  137. polling-delay-passive = <250>;
  138. polling-delay = <1000>;
  139. thermal-sensors = <&rtp>;
  140.  
  141. cooling-maps {
  142. map0 {
  143. trip = <&cpu_alert0>;
  144. cooling-device = <&cpu0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
  145. };
  146. };
  147.  
  148. trips {
  149. cpu_alert0: cpu_alert0 {
  150. /* milliCelsius */
  151. temperature = <70000>;
  152. hysteresis = <2000>;
  153. type = "passive";
  154. };
  155.  
  156. cpu_crit: cpu_crit {
  157. /* milliCelsius */
  158. temperature = <100000>;
  159. hysteresis = <2000>;
  160. type = "critical";
  161. };
  162. };
  163. };
  164. };
  165.  
  166. memory {
  167. reg = <0x40000000 0x80000000>;
  168. };
  169.  
  170. pmu {
  171. compatible = "arm,cortex-a7-pmu", "arm,cortex-a15-pmu";
  172. interrupts = <GIC_SPI 120 IRQ_TYPE_LEVEL_HIGH>,
  173. <GIC_SPI 121 IRQ_TYPE_LEVEL_HIGH>,
  174. <GIC_SPI 122 IRQ_TYPE_LEVEL_HIGH>,
  175. <GIC_SPI 123 IRQ_TYPE_LEVEL_HIGH>;
  176. };
  177.  
  178. clocks {
  179. #address-cells = <1>;
  180. #size-cells = <1>;
  181. ranges;
  182.  
  183. osc24M: osc24M {
  184. #clock-cells = <0>;
  185. compatible = "fixed-clock";
  186. clock-frequency = <24000000>;
  187. };
  188.  
  189. osc32k: clk@0 {
  190. #clock-cells = <0>;
  191. compatible = "fixed-clock";
  192. clock-frequency = <32768>;
  193. clock-output-names = "osc32k";
  194. };
  195.  
  196. pll1: clk@01c20000 {
  197. #clock-cells = <0>;
  198. compatible = "allwinner,sun6i-a31-pll1-clk";
  199. reg = <0x01c20000 0x4>;
  200. clocks = <&osc24M>;
  201. clock-output-names = "pll1";
  202. };
  203.  
  204. pll2: clk@01c20008 {
  205. #clock-cells = <1>;
  206. compatible = "allwinner,sun6i-a31-pll2-clk";
  207. reg = <0x01c20008 0x8>;
  208. clocks = <&osc24M>;
  209. clock-output-names = "pll2-1x", "pll2-2x",
  210. "pll2-4x", "pll2-8x";
  211. };
  212.  
  213. pll6: clk@01c20028 {
  214. #clock-cells = <1>;
  215. compatible = "allwinner,sun6i-a31-pll6-clk";
  216. reg = <0x01c20028 0x4>;
  217. clocks = <&osc24M>;
  218. clock-output-names = "pll6", "pll6x2";
  219. };
  220.  
  221. cpu: cpu@01c20050 {
  222. #clock-cells = <0>;
  223. compatible = "allwinner,sun4i-a10-cpu-clk";
  224. reg = <0x01c20050 0x4>;
  225.  
  226. /*
  227. * PLL1 is listed twice here.
  228. * While it looks suspicious, it's actually documented
  229. * that way both in the datasheet and in the code from
  230. * Allwinner.
  231. */
  232. clocks = <&osc32k>, <&osc24M>, <&pll1>, <&pll1>;
  233. clock-output-names = "cpu";
  234. };
  235.  
  236. axi: axi@01c20050 {
  237. #clock-cells = <0>;
  238. compatible = "allwinner,sun4i-a10-axi-clk";
  239. reg = <0x01c20050 0x4>;
  240. clocks = <&cpu>;
  241. clock-output-names = "axi";
  242. };
  243.  
  244. ahb1: ahb1@01c20054 {
  245. #clock-cells = <0>;
  246. compatible = "allwinner,sun6i-a31-ahb1-clk";
  247. reg = <0x01c20054 0x4>;
  248. clocks = <&osc32k>, <&osc24M>, <&axi>, <&pll6 0>;
  249. clock-output-names = "ahb1";
  250.  
  251. /*
  252. * Clock AHB1 from PLL6, instead of CPU/AXI which
  253. * has rate changes due to cpufreq. Also the DMA
  254. * controller requires AHB1 clocked from PLL6.
  255. */
  256. assigned-clocks = <&ahb1>;
  257. assigned-clock-parents = <&pll6 0>;
  258. };
  259.  
  260. ahb1_gates: clk@01c20060 {
  261. #clock-cells = <1>;
  262. compatible = "allwinner,sun6i-a31-ahb1-gates-clk";
  263. reg = <0x01c20060 0x8>;
  264. clocks = <&ahb1>;
  265. clock-indices = <1>, <5>,
  266. <6>, <8>, <9>,
  267. <10>, <11>, <12>,
  268. <13>, <14>,
  269. <17>, <18>, <19>,
  270. <20>, <21>, <22>,
  271. <23>, <24>, <26>,
  272. <27>, <29>,
  273. <30>, <31>, <32>,
  274. <36>, <37>, <40>,
  275. <43>, <44>, <45>,
  276. <46>, <47>, <50>,
  277. <52>, <55>, <56>,
  278. <57>, <58>;
  279. clock-output-names = "ahb1_mipidsi", "ahb1_ss",
  280. "ahb1_dma", "ahb1_mmc0", "ahb1_mmc1",
  281. "ahb1_mmc2", "ahb1_mmc3", "ahb1_nand1",
  282. "ahb1_nand0", "ahb1_sdram",
  283. "ahb1_gmac", "ahb1_ts", "ahb1_hstimer",
  284. "ahb1_spi0", "ahb1_spi1", "ahb1_spi2",
  285. "ahb1_spi3", "ahb1_otg", "ahb1_ehci0",
  286. "ahb1_ehci1", "ahb1_ohci0",
  287. "ahb1_ohci1", "ahb1_ohci2", "ahb1_ve",
  288. "ahb1_lcd0", "ahb1_lcd1", "ahb1_csi",
  289. "ahb1_hdmi", "ahb1_de0", "ahb1_de1",
  290. "ahb1_fe0", "ahb1_fe1", "ahb1_mp",
  291. "ahb1_gpu", "ahb1_deu0", "ahb1_deu1",
  292. "ahb1_drc0", "ahb1_drc1";
  293. };
  294.  
  295. apb1: apb1@01c20054 {
  296. #clock-cells = <0>;
  297. compatible = "allwinner,sun4i-a10-apb0-clk";
  298. reg = <0x01c20054 0x4>;
  299. clocks = <&ahb1>;
  300. clock-output-names = "apb1";
  301. };
  302.  
  303. apb1_gates: clk@01c20068 {
  304. #clock-cells = <1>;
  305. compatible = "allwinner,sun6i-a31-apb1-gates-clk";
  306. reg = <0x01c20068 0x4>;
  307. clocks = <&apb1>;
  308. clock-indices = <0>, <1>,
  309. <4>, <5>,
  310. <12>, <13>;
  311. clock-output-names = "apb1_codec", "apb1_spdif",
  312. "apb1_digital_mic", "apb1_pio",
  313. "apb1_daudio0", "apb1_daudio1";
  314. };
  315.  
  316. apb2: clk@01c20058 {
  317. #clock-cells = <0>;
  318. compatible = "allwinner,sun4i-a10-apb1-clk";
  319. reg = <0x01c20058 0x4>;
  320. clocks = <&osc32k>, <&osc24M>, <&pll6 0>, <&pll6 0>;
  321. clock-output-names = "apb2";
  322. };
  323.  
  324. apb2_gates: clk@01c2006c {
  325. #clock-cells = <1>;
  326. compatible = "allwinner,sun6i-a31-apb2-gates-clk";
  327. reg = <0x01c2006c 0x4>;
  328. clocks = <&apb2>;
  329. clock-indices = <0>, <1>,
  330. <2>, <3>, <16>,
  331. <17>, <18>, <19>,
  332. <20>, <21>;
  333. clock-output-names = "apb2_i2c0", "apb2_i2c1",
  334. "apb2_i2c2", "apb2_i2c3",
  335. "apb2_uart0", "apb2_uart1",
  336. "apb2_uart2", "apb2_uart3",
  337. "apb2_uart4", "apb2_uart5";
  338. };
  339.  
  340. mmc0_clk: clk@01c20088 {
  341. #clock-cells = <1>;
  342. compatible = "allwinner,sun4i-a10-mmc-clk";
  343. reg = <0x01c20088 0x4>;
  344. clocks = <&osc24M>, <&pll6 0>;
  345. clock-output-names = "mmc0",
  346. "mmc0_output",
  347. "mmc0_sample";
  348. };
  349.  
  350. mmc1_clk: clk@01c2008c {
  351. #clock-cells = <1>;
  352. compatible = "allwinner,sun4i-a10-mmc-clk";
  353. reg = <0x01c2008c 0x4>;
  354. clocks = <&osc24M>, <&pll6 0>;
  355. clock-output-names = "mmc1",
  356. "mmc1_output",
  357. "mmc1_sample";
  358. };
  359.  
  360. mmc2_clk: clk@01c20090 {
  361. #clock-cells = <1>;
  362. compatible = "allwinner,sun4i-a10-mmc-clk";
  363. reg = <0x01c20090 0x4>;
  364. clocks = <&osc24M>, <&pll6 0>;
  365. clock-output-names = "mmc2",
  366. "mmc2_output",
  367. "mmc2_sample";
  368. };
  369.  
  370. mmc3_clk: clk@01c20094 {
  371. #clock-cells = <1>;
  372. compatible = "allwinner,sun4i-a10-mmc-clk";
  373. reg = <0x01c20094 0x4>;
  374. clocks = <&osc24M>, <&pll6 0>;
  375. clock-output-names = "mmc3",
  376. "mmc3_output",
  377. "mmc3_sample";
  378. };
  379.  
  380. ss_clk: clk@01c2009c {
  381. #clock-cells = <0>;
  382. compatible = "allwinner,sun4i-a10-mod0-clk";
  383. reg = <0x01c2009c 0x4>;
  384. clocks = <&osc24M>, <&pll6 0>;
  385. clock-output-names = "ss";
  386. };
  387.  
  388. spi0_clk: clk@01c200a0 {
  389. #clock-cells = <0>;
  390. compatible = "allwinner,sun4i-a10-mod0-clk";
  391. reg = <0x01c200a0 0x4>;
  392. clocks = <&osc24M>, <&pll6 0>;
  393. clock-output-names = "spi0";
  394. };
  395.  
  396. spi1_clk: clk@01c200a4 {
  397. #clock-cells = <0>;
  398. compatible = "allwinner,sun4i-a10-mod0-clk";
  399. reg = <0x01c200a4 0x4>;
  400. clocks = <&osc24M>, <&pll6 0>;
  401. clock-output-names = "spi1";
  402. };
  403.  
  404. spi2_clk: clk@01c200a8 {
  405. #clock-cells = <0>;
  406. compatible = "allwinner,sun4i-a10-mod0-clk";
  407. reg = <0x01c200a8 0x4>;
  408. clocks = <&osc24M>, <&pll6 0>;
  409. clock-output-names = "spi2";
  410. };
  411.  
  412. spi3_clk: clk@01c200ac {
  413. #clock-cells = <0>;
  414. compatible = "allwinner,sun4i-a10-mod0-clk";
  415. reg = <0x01c200ac 0x4>;
  416. clocks = <&osc24M>, <&pll6 0>;
  417. clock-output-names = "spi3";
  418. };
  419.  
  420. i2s0_clk: clk@01c200b0 {
  421. #clock-cells = <0>;
  422. compatible = "allwinner,sun6i-a31-mod1-clk";
  423. reg = <0x01c200b0 0x4>;
  424. clocks = <&pll2 SUN4I_A10_PLL2_8X>,
  425. <&pll2 SUN4I_A10_PLL2_4X>,
  426. <&pll2 SUN4I_A10_PLL2_2X>,
  427. <&pll2 SUN4I_A10_PLL2_1X>;
  428. clock-output-names = "i2s0";
  429. };
  430.  
  431. i2s1_clk: clk@01c200b4 {
  432. #clock-cells = <0>;
  433. compatible = "allwinner,sun6i-a31-mod1-clk";
  434. reg = <0x01c200b4 0x4>;
  435. clocks = <&pll2 SUN4I_A10_PLL2_8X>,
  436. <&pll2 SUN4I_A10_PLL2_4X>,
  437. <&pll2 SUN4I_A10_PLL2_2X>,
  438. <&pll2 SUN4I_A10_PLL2_1X>;
  439. clock-output-names = "i2s1";
  440. };
  441.  
  442. usb_clk: clk@01c200cc {
  443. #clock-cells = <1>;
  444. #reset-cells = <1>;
  445. compatible = "allwinner,sun6i-a31-usb-clk";
  446. reg = <0x01c200cc 0x4>;
  447. clocks = <&osc24M>;
  448. clock-indices = <8>, <9>, <10>,
  449. <16>, <17>,
  450. <18>;
  451. clock-output-names = "usb_phy0", "usb_phy1", "usb_phy2",
  452. "usb_ohci0", "usb_ohci1",
  453. "usb_ohci2";
  454. };
  455.  
  456. /*
  457. * The following two are dummy clocks, placeholders
  458. * used in the gmac_tx clock. The gmac driver will
  459. * choose one parent depending on the PHY interface
  460. * mode, using clk_set_rate auto-reparenting.
  461. *
  462. * The actual TX clock rate is not controlled by the
  463. * gmac_tx clock.
  464. */
  465. mii_phy_tx_clk: clk@1 {
  466. #clock-cells = <0>;
  467. compatible = "fixed-clock";
  468. clock-frequency = <25000000>;
  469. clock-output-names = "mii_phy_tx";
  470. };
  471.  
  472. gmac_int_tx_clk: clk@2 {
  473. #clock-cells = <0>;
  474. compatible = "fixed-clock";
  475. clock-frequency = <125000000>;
  476. clock-output-names = "gmac_int_tx";
  477. };
  478.  
  479. spdif_clk: clk@01c200c0 {
  480. #clock-cells = <0>;
  481. compatible = "allwinner,sun4i-a10-mod1-clk";
  482. reg = <0x01c200c0 0x4>;
  483. clocks = <&pll2 SUN4I_A10_PLL2_8X>,
  484. <&pll2 SUN4I_A10_PLL2_4X>,
  485. <&pll2 SUN4I_A10_PLL2_2X>,
  486. <&pll2 SUN4I_A10_PLL2_1X>;
  487. clock-output-names = "spdif";
  488. };
  489.  
  490. gmac_tx_clk: clk@01c200d0 {
  491. #clock-cells = <0>;
  492. compatible = "allwinner,sun7i-a20-gmac-clk";
  493. reg = <0x01c200d0 0x4>;
  494. clocks = <&mii_phy_tx_clk>, <&gmac_int_tx_clk>;
  495. clock-output-names = "gmac_tx";
  496. };
  497.  
  498. audio_codec_clk: clk@01c20140 {
  499. #clock-cells = <0>;
  500. compatible = "allwinner,sun4i-a10-codec-clk";
  501. reg = <0x01c20140 0x4>;
  502. clocks = <&pll2 SUN4I_A10_PLL2_1X>;
  503. clock-output-names = "codec";
  504. };
  505. };
  506.  
  507. soc@01c00000 {
  508. compatible = "simple-bus";
  509. #address-cells = <1>;
  510. #size-cells = <1>;
  511. ranges;
  512.  
  513. dma: dma-controller@01c02000 {
  514. compatible = "allwinner,sun6i-a31-dma";
  515. reg = <0x01c02000 0x1000>;
  516. interrupts = <GIC_SPI 50 IRQ_TYPE_LEVEL_HIGH>;
  517. clocks = <&ahb1_gates 6>;
  518. resets = <&ahb1_rst 6>;
  519. #dma-cells = <1>;
  520. };
  521.  
  522. mmc0: mmc@01c0f000 {
  523. compatible = "allwinner,sun5i-a13-mmc";
  524. reg = <0x01c0f000 0x1000>;
  525. clocks = <&ahb1_gates 8>,
  526. <&mmc0_clk 0>,
  527. <&mmc0_clk 1>,
  528. <&mmc0_clk 2>;
  529. clock-names = "ahb",
  530. "mmc",
  531. "output",
  532. "sample";
  533. resets = <&ahb1_rst 8>;
  534. reset-names = "ahb";
  535. interrupts = <GIC_SPI 60 IRQ_TYPE_LEVEL_HIGH>;
  536. status = "disabled";
  537. #address-cells = <1>;
  538. #size-cells = <0>;
  539. };
  540.  
  541. mmc1: mmc@01c10000 {
  542. compatible = "allwinner,sun5i-a13-mmc";
  543. reg = <0x01c10000 0x1000>;
  544. clocks = <&ahb1_gates 9>,
  545. <&mmc1_clk 0>,
  546. <&mmc1_clk 1>,
  547. <&mmc1_clk 2>;
  548. clock-names = "ahb",
  549. "mmc",
  550. "output",
  551. "sample";
  552. resets = <&ahb1_rst 9>;
  553. reset-names = "ahb";
  554. interrupts = <GIC_SPI 61 IRQ_TYPE_LEVEL_HIGH>;
  555. status = "disabled";
  556. #address-cells = <1>;
  557. #size-cells = <0>;
  558. };
  559.  
  560. mmc2: mmc@01c11000 {
  561. compatible = "allwinner,sun5i-a13-mmc";
  562. reg = <0x01c11000 0x1000>;
  563. clocks = <&ahb1_gates 10>,
  564. <&mmc2_clk 0>,
  565. <&mmc2_clk 1>,
  566. <&mmc2_clk 2>;
  567. clock-names = "ahb",
  568. "mmc",
  569. "output",
  570. "sample";
  571. resets = <&ahb1_rst 10>;
  572. reset-names = "ahb";
  573. interrupts = <GIC_SPI 62 IRQ_TYPE_LEVEL_HIGH>;
  574. status = "disabled";
  575. #address-cells = <1>;
  576. #size-cells = <0>;
  577. };
  578.  
  579. mmc3: mmc@01c12000 {
  580. compatible = "allwinner,sun5i-a13-mmc";
  581. reg = <0x01c12000 0x1000>;
  582. clocks = <&ahb1_gates 11>,
  583. <&mmc3_clk 0>,
  584. <&mmc3_clk 1>,
  585. <&mmc3_clk 2>;
  586. clock-names = "ahb",
  587. "mmc",
  588. "output",
  589. "sample";
  590. resets = <&ahb1_rst 11>;
  591. reset-names = "ahb";
  592. interrupts = <GIC_SPI 63 IRQ_TYPE_LEVEL_HIGH>;
  593. status = "disabled";
  594. #address-cells = <1>;
  595. #size-cells = <0>;
  596. };
  597.  
  598. usb_otg: usb@01c19000 {
  599. compatible = "allwinner,sun6i-a31-musb";
  600. reg = <0x01c19000 0x0400>;
  601. clocks = <&ahb1_gates 24>;
  602. resets = <&ahb1_rst 24>;
  603. interrupts = <GIC_SPI 71 IRQ_TYPE_LEVEL_HIGH>;
  604. interrupt-names = "mc";
  605. phys = <&usbphy 0>;
  606. phy-names = "usb";
  607. extcon = <&usbphy 0>;
  608. status = "disabled";
  609. };
  610.  
  611. usbphy: phy@01c19400 {
  612. compatible = "allwinner,sun6i-a31-usb-phy";
  613. reg = <0x01c19400 0x10>,
  614. <0x01c1a800 0x4>,
  615. <0x01c1b800 0x4>;
  616. reg-names = "phy_ctrl",
  617. "pmu1",
  618. "pmu2";
  619. clocks = <&usb_clk 8>,
  620. <&usb_clk 9>,
  621. <&usb_clk 10>;
  622. clock-names = "usb0_phy",
  623. "usb1_phy",
  624. "usb2_phy";
  625. resets = <&usb_clk 0>,
  626. <&usb_clk 1>,
  627. <&usb_clk 2>;
  628. reset-names = "usb0_reset",
  629. "usb1_reset",
  630. "usb2_reset";
  631. status = "disabled";
  632. #phy-cells = <1>;
  633. };
  634.  
  635. ehci0: usb@01c1a000 {
  636. compatible = "allwinner,sun6i-a31-ehci", "generic-ehci";
  637. reg = <0x01c1a000 0x100>;
  638. interrupts = <GIC_SPI 72 IRQ_TYPE_LEVEL_HIGH>;
  639. clocks = <&ahb1_gates 26>;
  640. resets = <&ahb1_rst 26>;
  641. phys = <&usbphy 1>;
  642. phy-names = "usb";
  643. status = "disabled";
  644. };
  645.  
  646. ohci0: usb@01c1a400 {
  647. compatible = "allwinner,sun6i-a31-ohci", "generic-ohci";
  648. reg = <0x01c1a400 0x100>;
  649. interrupts = <GIC_SPI 73 IRQ_TYPE_LEVEL_HIGH>;
  650. clocks = <&ahb1_gates 29>, <&usb_clk 16>;
  651. resets = <&ahb1_rst 29>;
  652. phys = <&usbphy 1>;
  653. phy-names = "usb";
  654. status = "disabled";
  655. };
  656.  
  657. ehci1: usb@01c1b000 {
  658. compatible = "allwinner,sun6i-a31-ehci", "generic-ehci";
  659. reg = <0x01c1b000 0x100>;
  660. interrupts = <GIC_SPI 74 IRQ_TYPE_LEVEL_HIGH>;
  661. clocks = <&ahb1_gates 27>;
  662. resets = <&ahb1_rst 27>;
  663. phys = <&usbphy 2>;
  664. phy-names = "usb";
  665. status = "disabled";
  666. };
  667.  
  668. ohci1: usb@01c1b400 {
  669. compatible = "allwinner,sun6i-a31-ohci", "generic-ohci";
  670. reg = <0x01c1b400 0x100>;
  671. interrupts = <GIC_SPI 75 IRQ_TYPE_LEVEL_HIGH>;
  672. clocks = <&ahb1_gates 30>, <&usb_clk 17>;
  673. resets = <&ahb1_rst 30>;
  674. phys = <&usbphy 2>;
  675. phy-names = "usb";
  676. status = "disabled";
  677. };
  678.  
  679. ohci2: usb@01c1c400 {
  680. compatible = "allwinner,sun6i-a31-ohci", "generic-ohci";
  681. reg = <0x01c1c400 0x100>;
  682. interrupts = <GIC_SPI 77 IRQ_TYPE_LEVEL_HIGH>;
  683. clocks = <&ahb1_gates 31>, <&usb_clk 18>;
  684. resets = <&ahb1_rst 31>;
  685. status = "disabled";
  686. };
  687.  
  688. pio: pinctrl@01c20800 {
  689. compatible = "allwinner,sun6i-a31-pinctrl";
  690. reg = <0x01c20800 0x400>;
  691. interrupts = <GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH>,
  692. <GIC_SPI 15 IRQ_TYPE_LEVEL_HIGH>,
  693. <GIC_SPI 16 IRQ_TYPE_LEVEL_HIGH>,
  694. <GIC_SPI 17 IRQ_TYPE_LEVEL_HIGH>;
  695. clocks = <&apb1_gates 5>;
  696. gpio-controller;
  697. interrupt-controller;
  698. #interrupt-cells = <3>;
  699. #gpio-cells = <3>;
  700.  
  701. uart0_pins_a: uart0@0 {
  702. allwinner,pins = "PH20", "PH21";
  703. allwinner,function = "uart0";
  704. allwinner,drive = <SUN4I_PINCTRL_10_MA>;
  705. allwinner,pull = <SUN4I_PINCTRL_NO_PULL>;
  706. };
  707.  
  708. i2c0_pins_a: i2c0@0 {
  709. allwinner,pins = "PH14", "PH15";
  710. allwinner,function = "i2c0";
  711. allwinner,drive = <SUN4I_PINCTRL_10_MA>;
  712. allwinner,pull = <SUN4I_PINCTRL_NO_PULL>;
  713. };
  714.  
  715. i2c1_pins_a: i2c1@0 {
  716. allwinner,pins = "PH16", "PH17";
  717. allwinner,function = "i2c1";
  718. allwinner,drive = <SUN4I_PINCTRL_10_MA>;
  719. allwinner,pull = <SUN4I_PINCTRL_NO_PULL>;
  720. };
  721.  
  722. i2c2_pins_a: i2c2@0 {
  723. allwinner,pins = "PH18", "PH19";
  724. allwinner,function = "i2c2";
  725. allwinner,drive = <SUN4I_PINCTRL_10_MA>;
  726. allwinner,pull = <SUN4I_PINCTRL_NO_PULL>;
  727. };
  728.  
  729. mmc0_pins_a: mmc0@0 {
  730. allwinner,pins = "PF0", "PF1", "PF2",
  731. "PF3", "PF4", "PF5";
  732. allwinner,function = "mmc0";
  733. allwinner,drive = <SUN4I_PINCTRL_30_MA>;
  734. allwinner,pull = <SUN4I_PINCTRL_NO_PULL>;
  735. };
  736.  
  737. mmc1_pins_a: mmc1@0 {
  738. allwinner,pins = "PG0", "PG1", "PG2", "PG3",
  739. "PG4", "PG5";
  740. allwinner,function = "mmc1";
  741. allwinner,drive = <SUN4I_PINCTRL_30_MA>;
  742. allwinner,pull = <SUN4I_PINCTRL_NO_PULL>;
  743. };
  744.  
  745. mmc2_pins_a: mmc2@0 {
  746. allwinner,pins = "PC6", "PC7", "PC8", "PC9",
  747. "PC10", "PC11";
  748. allwinner,function = "mmc2";
  749. allwinner,drive = <SUN4I_PINCTRL_30_MA>;
  750. allwinner,pull = <SUN4I_PINCTRL_PULL_UP>;
  751. };
  752.  
  753. mmc2_8bit_emmc_pins: mmc2@1 {
  754. allwinner,pins = "PC6", "PC7", "PC8", "PC9",
  755. "PC10", "PC11", "PC12",
  756. "PC13", "PC14", "PC15",
  757. "PC24";
  758. allwinner,function = "mmc2";
  759. allwinner,drive = <SUN4I_PINCTRL_30_MA>;
  760. allwinner,pull = <SUN4I_PINCTRL_NO_PULL>;
  761. };
  762.  
  763. mmc3_8bit_emmc_pins: mmc3@1 {
  764. allwinner,pins = "PC6", "PC7", "PC8", "PC9",
  765. "PC10", "PC11", "PC12",
  766. "PC13", "PC14", "PC15",
  767. "PC24";
  768. allwinner,function = "mmc3";
  769. allwinner,drive = <SUN4I_PINCTRL_40_MA>;
  770. allwinner,pull = <SUN4I_PINCTRL_NO_PULL>;
  771. };
  772.  
  773. gmac_pins_mii_a: gmac_mii@0 {
  774. allwinner,pins = "PA0", "PA1", "PA2", "PA3",
  775. "PA8", "PA9", "PA11",
  776. "PA12", "PA13", "PA14", "PA19",
  777. "PA20", "PA21", "PA22", "PA23",
  778. "PA24", "PA26", "PA27";
  779. allwinner,function = "gmac";
  780. allwinner,drive = <SUN4I_PINCTRL_10_MA>;
  781. allwinner,pull = <SUN4I_PINCTRL_NO_PULL>;
  782. };
  783.  
  784. gmac_pins_gmii_a: gmac_gmii@0 {
  785. allwinner,pins = "PA0", "PA1", "PA2", "PA3",
  786. "PA4", "PA5", "PA6", "PA7",
  787. "PA8", "PA9", "PA10", "PA11",
  788. "PA12", "PA13", "PA14", "PA15",
  789. "PA16", "PA17", "PA18", "PA19",
  790. "PA20", "PA21", "PA22", "PA23",
  791. "PA24", "PA25", "PA26", "PA27";
  792. allwinner,function = "gmac";
  793. /*
  794. * data lines in GMII mode run at 125MHz and
  795. * might need a higher signal drive strength
  796. */
  797. allwinner,drive = <SUN4I_PINCTRL_30_MA>;
  798. allwinner,pull = <SUN4I_PINCTRL_NO_PULL>;
  799. };
  800.  
  801. gmac_pins_rgmii_a: gmac_rgmii@0 {
  802. allwinner,pins = "PA0", "PA1", "PA2", "PA3",
  803. "PA9", "PA10", "PA11",
  804. "PA12", "PA13", "PA14", "PA19",
  805. "PA20", "PA25", "PA26", "PA27";
  806. allwinner,function = "gmac";
  807. /*
  808. * data lines in RGMII mode use DDR mode
  809. * and need a higher signal drive strength
  810. */
  811. allwinner,drive = <SUN4I_PINCTRL_40_MA>;
  812. allwinner,pull = <SUN4I_PINCTRL_NO_PULL>;
  813. };
  814.  
  815. spdif_pins_a: spdif@0 {
  816. allwinner,pins = "PH28";
  817. allwinner,function = "spdif";
  818. allwinner,drive = <SUN4I_PINCTRL_10_MA>;
  819. allwinner,pull = <SUN4I_PINCTRL_PULL_UP>;
  820. };
  821. };
  822.  
  823. ahb1_rst: reset@01c202c0 {
  824. #reset-cells = <1>;
  825. compatible = "allwinner,sun6i-a31-ahb1-reset";
  826. reg = <0x01c202c0 0xc>;
  827. };
  828.  
  829. apb1_rst: reset@01c202d0 {
  830. #reset-cells = <1>;
  831. compatible = "allwinner,sun6i-a31-clock-reset";
  832. reg = <0x01c202d0 0x4>;
  833. };
  834.  
  835. apb2_rst: reset@01c202d8 {
  836. #reset-cells = <1>;
  837. compatible = "allwinner,sun6i-a31-clock-reset";
  838. reg = <0x01c202d8 0x4>;
  839. };
  840.  
  841. timer@01c20c00 {
  842. compatible = "allwinner,sun4i-a10-timer";
  843. reg = <0x01c20c00 0xa0>;
  844. interrupts = <GIC_SPI 18 IRQ_TYPE_LEVEL_HIGH>,
  845. <GIC_SPI 19 IRQ_TYPE_LEVEL_HIGH>,
  846. <GIC_SPI 20 IRQ_TYPE_LEVEL_HIGH>,
  847. <GIC_SPI 21 IRQ_TYPE_LEVEL_HIGH>,
  848. <GIC_SPI 22 IRQ_TYPE_LEVEL_HIGH>;
  849. clocks = <&osc24M>;
  850. };
  851.  
  852. wdt1: watchdog@01c20ca0 {
  853. compatible = "allwinner,sun6i-a31-wdt";
  854. reg = <0x01c20ca0 0x20>;
  855. };
  856.  
  857. spdif: spdif@01c21000 {
  858. #sound-dai-cells = <0>;
  859. compatible = "allwinner,sun6i-a31-spdif";
  860. reg = <0x01c21000 0x400>;
  861. interrupts = <GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH>;
  862. clocks = <&apb1_gates 1>, <&spdif_clk>;
  863. clock-names = "apb", "spdif";
  864. dmas = <&dma 2>, <&dma 2>;
  865. dma-names = "rx", "tx";
  866. resets = <&apb1_rst 1>;
  867. spdif-out = "disabled";
  868. status = "disabled";
  869. };
  870.  
  871. lradc: lradc@01c22800 {
  872. compatible = "allwinner,sun4i-a10-lradc-keys";
  873. reg = <0x01c22800 0x100>;
  874. interrupts = <GIC_SPI 30 IRQ_TYPE_LEVEL_HIGH>;
  875. status = "disabled";
  876. };
  877.  
  878. codec: codec@01c22c00 {
  879. #address-cells = <1>;
  880. #size-cells = <1>;
  881. compatible = "allwinner,sun6i-a31-codec";
  882. interrupts = <GIC_SPI 29 IRQ_TYPE_LEVEL_HIGH>;
  883. reg = <0x01c22c00 0x400>;
  884. resets = <&apb1_rst 0>;
  885. clocks = <&apb1_gates 0>, <&audio_codec_clk>;
  886. clock-names = "apb", "codec";
  887. dmas = <&dma 15>,
  888. <&dma 15>;
  889. dma-names = "rx", "tx";
  890. status = "disabled";
  891. };
  892.  
  893. rtp: rtp@01c25000 {
  894. compatible = "allwinner,sun6i-a31-ts";
  895. reg = <0x01c25000 0x100>;
  896. interrupts = <GIC_SPI 28 IRQ_TYPE_LEVEL_HIGH>;
  897. #thermal-sensor-cells = <0>;
  898. };
  899.  
  900. uart0: serial@01c28000 {
  901. compatible = "snps,dw-apb-uart";
  902. reg = <0x01c28000 0x400>;
  903. interrupts = <GIC_SPI 0 IRQ_TYPE_LEVEL_HIGH>;
  904. reg-shift = <2>;
  905. reg-io-width = <4>;
  906. clocks = <&apb2_gates 16>;
  907. resets = <&apb2_rst 16>;
  908. dmas = <&dma 6>, <&dma 6>;
  909. dma-names = "rx", "tx";
  910. status = "disabled";
  911. };
  912.  
  913. uart1: serial@01c28400 {
  914. compatible = "snps,dw-apb-uart";
  915. reg = <0x01c28400 0x400>;
  916. interrupts = <GIC_SPI 1 IRQ_TYPE_LEVEL_HIGH>;
  917. reg-shift = <2>;
  918. reg-io-width = <4>;
  919. clocks = <&apb2_gates 17>;
  920. resets = <&apb2_rst 17>;
  921. dmas = <&dma 7>, <&dma 7>;
  922. dma-names = "rx", "tx";
  923. status = "disabled";
  924. };
  925.  
  926. uart2: serial@01c28800 {
  927. compatible = "snps,dw-apb-uart";
  928. reg = <0x01c28800 0x400>;
  929. interrupts = <GIC_SPI 2 IRQ_TYPE_LEVEL_HIGH>;
  930. reg-shift = <2>;
  931. reg-io-width = <4>;
  932. clocks = <&apb2_gates 18>;
  933. resets = <&apb2_rst 18>;
  934. dmas = <&dma 8>, <&dma 8>;
  935. dma-names = "rx", "tx";
  936. status = "disabled";
  937. };
  938.  
  939. uart3: serial@01c28c00 {
  940. compatible = "snps,dw-apb-uart";
  941. reg = <0x01c28c00 0x400>;
  942. interrupts = <GIC_SPI 3 IRQ_TYPE_LEVEL_HIGH>;
  943. reg-shift = <2>;
  944. reg-io-width = <4>;
  945. clocks = <&apb2_gates 19>;
  946. resets = <&apb2_rst 19>;
  947. dmas = <&dma 9>, <&dma 9>;
  948. dma-names = "rx", "tx";
  949. status = "disabled";
  950. };
  951.  
  952. uart4: serial@01c29000 {
  953. compatible = "snps,dw-apb-uart";
  954. reg = <0x01c29000 0x400>;
  955. interrupts = <GIC_SPI 4 IRQ_TYPE_LEVEL_HIGH>;
  956. reg-shift = <2>;
  957. reg-io-width = <4>;
  958. clocks = <&apb2_gates 20>;
  959. resets = <&apb2_rst 20>;
  960. dmas = <&dma 10>, <&dma 10>;
  961. dma-names = "rx", "tx";
  962. status = "disabled";
  963. };
  964.  
  965. uart5: serial@01c29400 {
  966. compatible = "snps,dw-apb-uart";
  967. reg = <0x01c29400 0x400>;
  968. interrupts = <GIC_SPI 5 IRQ_TYPE_LEVEL_HIGH>;
  969. reg-shift = <2>;
  970. reg-io-width = <4>;
  971. clocks = <&apb2_gates 21>;
  972. resets = <&apb2_rst 21>;
  973. dmas = <&dma 22>, <&dma 22>;
  974. dma-names = "rx", "tx";
  975. status = "disabled";
  976. };
  977.  
  978. i2c0: i2c@01c2ac00 {
  979. compatible = "allwinner,sun6i-a31-i2c";
  980. reg = <0x01c2ac00 0x400>;
  981. interrupts = <GIC_SPI 6 IRQ_TYPE_LEVEL_HIGH>;
  982. clocks = <&apb2_gates 0>;
  983. resets = <&apb2_rst 0>;
  984. status = "disabled";
  985. #address-cells = <1>;
  986. #size-cells = <0>;
  987. };
  988.  
  989. i2c1: i2c@01c2b000 {
  990. compatible = "allwinner,sun6i-a31-i2c";
  991. reg = <0x01c2b000 0x400>;
  992. interrupts = <GIC_SPI 7 IRQ_TYPE_LEVEL_HIGH>;
  993. clocks = <&apb2_gates 1>;
  994. resets = <&apb2_rst 1>;
  995. status = "disabled";
  996. #address-cells = <1>;
  997. #size-cells = <0>;
  998. };
  999.  
  1000. i2c2: i2c@01c2b400 {
  1001. compatible = "allwinner,sun6i-a31-i2c";
  1002. reg = <0x01c2b400 0x400>;
  1003. interrupts = <GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>;
  1004. clocks = <&apb2_gates 2>;
  1005. resets = <&apb2_rst 2>;
  1006. status = "disabled";
  1007. #address-cells = <1>;
  1008. #size-cells = <0>;
  1009. };
  1010.  
  1011. i2c3: i2c@01c2b800 {
  1012. compatible = "allwinner,sun6i-a31-i2c";
  1013. reg = <0x01c2b800 0x400>;
  1014. interrupts = <GIC_SPI 9 IRQ_TYPE_LEVEL_HIGH>;
  1015. clocks = <&apb2_gates 3>;
  1016. resets = <&apb2_rst 3>;
  1017. status = "disabled";
  1018. #address-cells = <1>;
  1019. #size-cells = <0>;
  1020. };
  1021.  
  1022. gmac: ethernet@01c30000 {
  1023. compatible = "allwinner,sun7i-a20-gmac";
  1024. reg = <0x01c30000 0x1054>;
  1025. interrupts = <GIC_SPI 82 IRQ_TYPE_LEVEL_HIGH>;
  1026. interrupt-names = "macirq";
  1027. clocks = <&ahb1_gates 17>, <&gmac_tx_clk>;
  1028. clock-names = "stmmaceth", "allwinner_gmac_tx";
  1029. resets = <&ahb1_rst 17>;
  1030. reset-names = "stmmaceth";
  1031. snps,pbl = <2>;
  1032. snps,fixed-burst;
  1033. snps,force_sf_dma_mode;
  1034. status = "disabled";
  1035. #address-cells = <1>;
  1036. #size-cells = <0>;
  1037. };
  1038.  
  1039. crypto: crypto-engine@01c15000 {
  1040. compatible = "allwinner,sun4i-a10-crypto";
  1041. reg = <0x01c15000 0x1000>;
  1042. interrupts = <GIC_SPI 80 IRQ_TYPE_LEVEL_HIGH>;
  1043. clocks = <&ahb1_gates 5>, <&ss_clk>;
  1044. clock-names = "ahb", "mod";
  1045. resets = <&ahb1_rst 5>;
  1046. reset-names = "ahb";
  1047. };
  1048.  
  1049. timer@01c60000 {
  1050. compatible = "allwinner,sun6i-a31-hstimer",
  1051. "allwinner,sun7i-a20-hstimer";
  1052. reg = <0x01c60000 0x1000>;
  1053. interrupts = <GIC_SPI 51 IRQ_TYPE_LEVEL_HIGH>,
  1054. <GIC_SPI 52 IRQ_TYPE_LEVEL_HIGH>,
  1055. <GIC_SPI 53 IRQ_TYPE_LEVEL_HIGH>,
  1056. <GIC_SPI 54 IRQ_TYPE_LEVEL_HIGH>;
  1057. clocks = <&ahb1_gates 19>;
  1058. resets = <&ahb1_rst 19>;
  1059. };
  1060.  
  1061. spi0: spi@01c68000 {
  1062. compatible = "allwinner,sun6i-a31-spi";
  1063. reg = <0x01c68000 0x1000>;
  1064. interrupts = <GIC_SPI 65 IRQ_TYPE_LEVEL_HIGH>;
  1065. clocks = <&ahb1_gates 20>, <&spi0_clk>;
  1066. clock-names = "ahb", "mod";
  1067. dmas = <&dma 23>, <&dma 23>;
  1068. dma-names = "rx", "tx";
  1069. resets = <&ahb1_rst 20>;
  1070. status = "disabled";
  1071. };
  1072.  
  1073. spi1: spi@01c69000 {
  1074. compatible = "allwinner,sun6i-a31-spi";
  1075. reg = <0x01c69000 0x1000>;
  1076. interrupts = <GIC_SPI 66 IRQ_TYPE_LEVEL_HIGH>;
  1077. clocks = <&ahb1_gates 21>, <&spi1_clk>;
  1078. clock-names = "ahb", "mod";
  1079. dmas = <&dma 24>, <&dma 24>;
  1080. dma-names = "rx", "tx";
  1081. resets = <&ahb1_rst 21>;
  1082. status = "disabled";
  1083. };
  1084.  
  1085. spi2: spi@01c6a000 {
  1086. compatible = "allwinner,sun6i-a31-spi";
  1087. reg = <0x01c6a000 0x1000>;
  1088. interrupts = <GIC_SPI 67 IRQ_TYPE_LEVEL_HIGH>;
  1089. clocks = <&ahb1_gates 22>, <&spi2_clk>;
  1090. clock-names = "ahb", "mod";
  1091. dmas = <&dma 25>, <&dma 25>;
  1092. dma-names = "rx", "tx";
  1093. resets = <&ahb1_rst 22>;
  1094. status = "disabled";
  1095. };
  1096.  
  1097. spi3: spi@01c6b000 {
  1098. compatible = "allwinner,sun6i-a31-spi";
  1099. reg = <0x01c6b000 0x1000>;
  1100. interrupts = <GIC_SPI 68 IRQ_TYPE_LEVEL_HIGH>;
  1101. clocks = <&ahb1_gates 23>, <&spi3_clk>;
  1102. clock-names = "ahb", "mod";
  1103. dmas = <&dma 26>, <&dma 26>;
  1104. dma-names = "rx", "tx";
  1105. resets = <&ahb1_rst 23>;
  1106. status = "disabled";
  1107. };
  1108.  
  1109. gic: interrupt-controller@01c81000 {
  1110. compatible = "arm,cortex-a7-gic", "arm,cortex-a15-gic";
  1111. reg = <0x01c81000 0x1000>,
  1112. <0x01c82000 0x1000>,
  1113. <0x01c84000 0x2000>,
  1114. <0x01c86000 0x2000>;
  1115. interrupt-controller;
  1116. #interrupt-cells = <3>;
  1117. interrupts = <GIC_PPI 9 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>;
  1118. };
  1119.  
  1120. rtc: rtc@01f00000 {
  1121. compatible = "allwinner,sun6i-a31-rtc";
  1122. reg = <0x01f00000 0x54>;
  1123. interrupts = <GIC_SPI 40 IRQ_TYPE_LEVEL_HIGH>,
  1124. <GIC_SPI 41 IRQ_TYPE_LEVEL_HIGH>;
  1125. };
  1126.  
  1127. nmi_intc: interrupt-controller@01f00c0c {
  1128. compatible = "allwinner,sun6i-a31-sc-nmi";
  1129. interrupt-controller;
  1130. #interrupt-cells = <2>;
  1131. reg = <0x01f00c0c 0x38>;
  1132. interrupts = <GIC_SPI 32 IRQ_TYPE_LEVEL_HIGH>;
  1133. };
  1134.  
  1135. prcm@01f01400 {
  1136. compatible = "allwinner,sun6i-a31-prcm";
  1137. reg = <0x01f01400 0x200>;
  1138.  
  1139. ar100: ar100_clk {
  1140. compatible = "allwinner,sun6i-a31-ar100-clk";
  1141. #clock-cells = <0>;
  1142. clocks = <&osc32k>, <&osc24M>, <&pll6 0>,
  1143. <&pll6 0>;
  1144. clock-output-names = "ar100";
  1145. };
  1146.  
  1147. ahb0: ahb0_clk {
  1148. compatible = "fixed-factor-clock";
  1149. #clock-cells = <0>;
  1150. clock-div = <1>;
  1151. clock-mult = <1>;
  1152. clocks = <&ar100>;
  1153. clock-output-names = "ahb0";
  1154. };
  1155.  
  1156. apb0: apb0_clk {
  1157. compatible = "allwinner,sun6i-a31-apb0-clk";
  1158. #clock-cells = <0>;
  1159. clocks = <&ahb0>;
  1160. clock-output-names = "apb0";
  1161. };
  1162.  
  1163. apb0_gates: apb0_gates_clk {
  1164. compatible = "allwinner,sun6i-a31-apb0-gates-clk";
  1165. #clock-cells = <1>;
  1166. clocks = <&apb0>;
  1167. clock-output-names = "apb0_pio", "apb0_ir",
  1168. "apb0_timer", "apb0_p2wi",
  1169. "apb0_uart", "apb0_1wire",
  1170. "apb0_i2c";
  1171. };
  1172.  
  1173. ir_clk: ir_clk {
  1174. #clock-cells = <0>;
  1175. compatible = "allwinner,sun4i-a10-mod0-clk";
  1176. clocks = <&osc32k>, <&osc24M>;
  1177. clock-output-names = "ir";
  1178. };
  1179.  
  1180. apb0_rst: apb0_rst {
  1181. compatible = "allwinner,sun6i-a31-clock-reset";
  1182. #reset-cells = <1>;
  1183. };
  1184. };
  1185.  
  1186. cpucfg@01f01c00 {
  1187. compatible = "allwinner,sun6i-a31-cpuconfig";
  1188. reg = <0x01f01c00 0x300>;
  1189. };
  1190.  
  1191. ir: ir@01f02000 {
  1192. compatible = "allwinner,sun5i-a13-ir";
  1193. clocks = <&apb0_gates 1>, <&ir_clk>;
  1194. clock-names = "apb", "ir";
  1195. resets = <&apb0_rst 1>;
  1196. interrupts = <GIC_SPI 37 IRQ_TYPE_LEVEL_HIGH>;
  1197. reg = <0x01f02000 0x40>;
  1198. status = "disabled";
  1199. };
  1200.  
  1201. r_pio: pinctrl@01f02c00 {
  1202. compatible = "allwinner,sun6i-a31-r-pinctrl";
  1203. reg = <0x01f02c00 0x400>;
  1204. interrupts = <GIC_SPI 45 IRQ_TYPE_LEVEL_HIGH>,
  1205. <GIC_SPI 46 IRQ_TYPE_LEVEL_HIGH>;
  1206. clocks = <&apb0_gates 0>;
  1207. resets = <&apb0_rst 0>;
  1208. gpio-controller;
  1209. interrupt-controller;
  1210. #interrupt-cells = <3>;
  1211. #size-cells = <0>;
  1212. #gpio-cells = <3>;
  1213.  
  1214. ir_pins_a: ir@0 {
  1215. allwinner,pins = "PL4";
  1216. allwinner,function = "s_ir";
  1217. allwinner,drive = <SUN4I_PINCTRL_10_MA>;
  1218. allwinner,pull = <SUN4I_PINCTRL_NO_PULL>;
  1219. };
  1220.  
  1221. p2wi_pins: p2wi {
  1222. allwinner,pins = "PL0", "PL1";
  1223. allwinner,function = "s_p2wi";
  1224. allwinner,drive = <SUN4I_PINCTRL_10_MA>;
  1225. allwinner,pull = <SUN4I_PINCTRL_NO_PULL>;
  1226. };
  1227. };
  1228.  
  1229. p2wi: i2c@01f03400 {
  1230. compatible = "allwinner,sun6i-a31-p2wi";
  1231. reg = <0x01f03400 0x400>;
  1232. interrupts = <GIC_SPI 39 IRQ_TYPE_LEVEL_HIGH>;
  1233. clocks = <&apb0_gates 3>;
  1234. clock-frequency = <100000>;
  1235. resets = <&apb0_rst 3>;
  1236. pinctrl-names = "default";
  1237. pinctrl-0 = <&p2wi_pins>;
  1238. status = "disabled";
  1239. #address-cells = <1>;
  1240. #size-cells = <0>;
  1241. };
  1242. };
  1243. };
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