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- Release 14.7 par P.20131013 (lin64)
- Copyright (c) 1995-2013 Xilinx, Inc. All rights reserved.
- w530:: Mon Jun 22 18:40:48 2015
- par -ol high -w nandreader-nandreadersoc-pipistrello_map.ncd
- nandreader-nandreadersoc-pipistrello.ncd
- nandreader-nandreadersoc-pipistrello.pcf
- Constraints file: nandreader-nandreadersoc-pipistrello.pcf.
- Loading device for application Rf_Device from file '6slx45.nph' in environment /mnt/lu/opt/Xilinx/14.7/ISE_DS/ISE/.
- "top" is an NCD, version 3.2, device xc6slx45, package csg324, speed -3
- Initializing temperature to 85.000 Celsius. (default - Range: 0.000 to 85.000 Celsius)
- Initializing voltage to 1.140 Volts. (default - Range: 1.140 to 1.260 Volts)
- Device speed data version: "PRODUCTION 1.23 2013-10-13".
- Device Utilization Summary:
- Slice Logic Utilization:
- Number of Slice Registers: 2,401 out of 54,576 4%
- Number used as Flip Flops: 2,396
- Number used as Latches: 0
- Number used as Latch-thrus: 0
- Number used as AND/OR logics: 5
- Number of Slice LUTs: 3,098 out of 27,288 11%
- Number used as logic: 2,873 out of 27,288 10%
- Number using O6 output only: 2,157
- Number using O5 output only: 62
- Number using O5 and O6: 654
- Number used as ROM: 0
- Number used as Memory: 199 out of 6,408 3%
- Number used as Dual Port RAM: 192
- Number using O6 output only: 0
- Number using O5 output only: 16
- Number using O5 and O6: 176
- Number used as Single Port RAM: 0
- Number used as Shift Register: 7
- Number using O6 output only: 6
- Number using O5 output only: 0
- Number using O5 and O6: 1
- Number used exclusively as route-thrus: 26
- Number with same-slice register load: 24
- Number with same-slice carry load: 2
- Number with other load: 0
- Slice Logic Distribution:
- Number of occupied Slices: 1,175 out of 6,822 17%
- Number of MUXCYs used: 468 out of 13,644 3%
- Number of LUT Flip Flop pairs used: 3,629
- Number with an unused Flip Flop: 1,538 out of 3,629 42%
- Number with an unused LUT: 531 out of 3,629 14%
- Number of fully used LUT-FF pairs: 1,560 out of 3,629 42%
- Number of slice register sites lost
- to control set restrictions: 0 out of 54,576 0%
- A LUT Flip Flop pair for this architecture represents one LUT paired with
- one Flip Flop within a slice. A control set is a unique combination of
- clock, reset, set, and enable signals for a registered element.
- The Slice Logic Distribution report is not meaningful if the design is
- over-mapped for a non-slice resource or if Placement fails.
- IO Utilization:
- Number of bonded IOBs: 77 out of 218 35%
- Number of LOCed IOBs: 77 out of 77 100%
- IOB Flip Flops: 6
- Specific Feature Utilization:
- Number of RAMB16BWERs: 11 out of 116 9%
- Number of RAMB8BWERs: 3 out of 232 1%
- Number of BUFIO2/BUFIO2_2CLKs: 1 out of 32 3%
- Number used as BUFIO2s: 1
- Number used as BUFIO2_2CLKs: 0
- Number of BUFIO2FB/BUFIO2FB_2CLKs: 0 out of 32 0%
- Number of BUFG/BUFGMUXs: 3 out of 16 18%
- Number used as BUFGs: 3
- Number used as BUFGMUX: 0
- Number of DCM/DCM_CLKGENs: 0 out of 8 0%
- Number of ILOGIC2/ISERDES2s: 16 out of 376 4%
- Number used as ILOGIC2s: 0
- Number used as ISERDES2s: 16
- Number of IODELAY2/IODRP2/IODRP2_MCBs: 0 out of 376 0%
- Number of OLOGIC2/OSERDES2s: 22 out of 376 5%
- Number used as OLOGIC2s: 4
- Number used as OSERDES2s: 18
- Number of BSCANs: 0 out of 4 0%
- Number of BUFHs: 0 out of 256 0%
- Number of BUFPLLs: 1 out of 8 12%
- Number of BUFPLL_MCBs: 0 out of 4 0%
- Number of DSP48A1s: 3 out of 58 5%
- Number of ICAPs: 0 out of 1 0%
- Number of MCBs: 0 out of 2 0%
- Number of PCILOGICSEs: 0 out of 2 0%
- Number of PLL_ADVs: 1 out of 4 25%
- Number of PMVs: 0 out of 1 0%
- Number of STARTUPs: 0 out of 1 0%
- Number of SUSPEND_SYNCs: 0 out of 1 0%
- Overall effort level (-ol): High
- Router effort level (-rl): High
- Starting initial Timing Analysis. REAL time: 8 secs
- Finished initial Timing Analysis. REAL time: 8 secs
- WARNING:Par:288 - The signal obj_ledio_led0_IBUF has no load. PAR will not attempt to route this signal.
- WARNING:Par:288 - The signal obj_ledio_led1_IBUF has no load. PAR will not attempt to route this signal.
- WARNING:Par:288 - The signal obj_ledio_led2_IBUF has no load. PAR will not attempt to route this signal.
- WARNING:Par:288 - The signal obj_ledio_led3_IBUF has no load. PAR will not attempt to route this signal.
- WARNING:Par:288 - The signal nandreadersoc_nandreadersoc_nandreadersoc_serial_cts_IBUF has no load. PAR will not attempt to route this
- signal.
- WARNING:Par:288 - The signal nandreadersoc_nandreadersoc_nandreadersoc_serial_rts_IBUF has no load. PAR will not attempt to route this
- signal.
- WARNING:Par:288 - The signal obj_second_serial_cts_IBUF has no load. PAR will not attempt to route this signal.
- WARNING:Par:288 - The signal obj_second_serial_rts_IBUF has no load. PAR will not attempt to route this signal.
- Starting Router
- Phase 1 : 20465 unrouted; REAL time: 9 secs
- Phase 2 : 17902 unrouted; REAL time: 11 secs
- Phase 3 : 7900 unrouted; REAL time: 20 secs
- Phase 4 : 7900 unrouted; (Setup:0, Hold:3807, Component Switching Limit:0) REAL time: 22 secs
- Updating file: nandreader-nandreadersoc-pipistrello.ncd with current fully routed design.
- Phase 5 : 0 unrouted; (Setup:0, Hold:3360, Component Switching Limit:0) REAL time: 35 secs
- Phase 6 : 0 unrouted; (Setup:0, Hold:3360, Component Switching Limit:0) REAL time: 35 secs
- Phase 7 : 0 unrouted; (Setup:0, Hold:3360, Component Switching Limit:0) REAL time: 35 secs
- Phase 8 : 0 unrouted; (Setup:0, Hold:3360, Component Switching Limit:0) REAL time: 35 secs
- Phase 9 : 0 unrouted; (Setup:0, Hold:0, Component Switching Limit:0) REAL time: 36 secs
- Phase 10 : 0 unrouted; (Setup:0, Hold:0, Component Switching Limit:0) REAL time: 39 secs
- Total REAL time to Router completion: 39 secs
- Total CPU time to Router completion: 41 secs
- Partition Implementation Status
- -------------------------------
- No Partitions were found in this design.
- -------------------------------
- Generating "PAR" statistics.
- **************************
- Generating Clock Report
- **************************
- +---------------------+--------------+------+------+------------+-------------+
- | Clock Net | Resource |Locked|Fanout|Net Skew(ns)|Max Delay(ns)|
- +---------------------+--------------+------+------+------------+-------------+
- | sys_clk | BUFGMUX_X2Y2| No | 812 | 0.168 | 1.381 |
- +---------------------+--------------+------+------+------------+-------------+
- | sdram_half_clk | BUFGMUX_X3Y13| No | 17 | 0.484 | 1.743 |
- +---------------------+--------------+------+------+------------+-------------+
- |nandreadersoc_crg_cl | | | | | |
- |k_sdram_half_shifted | | | | | |
- | | BUFGMUX_X2Y3| No | 4 | 0.000 | 1.774 |
- +---------------------+--------------+------+------+------------+-------------+
- | sdram_full_wr_clk | Local| | 34 | 0.028 | 1.533 |
- +---------------------+--------------+------+------+------------+-------------+
- * Net Skew is the difference between the minimum and maximum routing
- only delays for the net. Note this is different from Clock Skew which
- is reported in TRCE timing report. Clock Skew is the difference between
- the minimum and maximum path delays which includes logic delays.
- * The fanout is the number of component pins not the individual BEL loads,
- for example SLICE loads not FF loads.
- Timing Score: 0 (Setup: 0, Hold: 0, Component Switching Limit: 0)
- Number of Timing Constraints that were not applied: 4
- Asterisk (*) preceding a constraint indicates it was not met.
- This may be due to a setup or hold violation.
- ----------------------------------------------------------------------------------------------------------
- Constraint | Check | Worst Case | Best Case | Timing | Timing
- | | Slack | Achievable | Errors | Score
- ----------------------------------------------------------------------------------------------------------
- TS_nandreadersoc_crg_pll_2_ = PERIOD TIME | SETUP | 0.012ns| 6.650ns| 0| 0
- GRP "nandreadersoc_crg_pll_2_" TS | HOLD | 0.476ns| | 0| 0
- _nandreadersoc_crg_clk50b / 3 PHASE 5 ns | | | | |
- HIGH 50% | | | | |
- ----------------------------------------------------------------------------------------------------------
- TS_nandreadersoc_crg_pll_5_ = PERIOD TIME | SETUP | 0.226ns| 12.381ns| 0| 0
- GRP "nandreadersoc_crg_pll_5_" TS | HOLD | 0.043ns| | 0| 0
- _nandreadersoc_crg_clk50b / 1.5 HIGH 50% | | | | |
- ----------------------------------------------------------------------------------------------------------
- TS_nandreadersoc_crg_clk50b = PERIOD TIME | MINLOWPULSE | 15.000ns| 5.000ns| 0| 0
- GRP "nandreadersoc_crg_clk50b" TS | | | | |
- clk50 HIGH 50% | | | | |
- ----------------------------------------------------------------------------------------------------------
- TS_nandreadersoc_crg_pll_3_ = PERIOD TIME | MINPERIOD | 4.936ns| 1.730ns| 0| 0
- GRP "nandreadersoc_crg_pll_3_" TS | | | | |
- _nandreadersoc_crg_clk50b / 3 PHASE 4.629 | | | | |
- 62963 ns HIGH 50% | | | | |
- ----------------------------------------------------------------------------------------------------------
- TSclk50 = PERIOD TIMEGRP "GRPclk50" 20 ns | MINPERIOD | 19.075ns| 0.925ns| 0| 0
- HIGH 50% | | | | |
- ----------------------------------------------------------------------------------------------------------
- TS_nandreadersoc_crg_pll_0_ = PERIOD TIME | N/A | N/A| N/A| N/A| N/A
- GRP "nandreadersoc_crg_pll_0_" TS | | | | |
- _nandreadersoc_crg_clk50b / 6 HIGH 50% | | | | |
- ----------------------------------------------------------------------------------------------------------
- Derived Constraint Report
- Review Timing Report for more details on the following derived constraints.
- To create a Timing Report, run "trce -v 12 -fastpaths -o design_timing_report design.ncd design.pcf"
- or "Run Timing Analysis" from Timing Analyzer (timingan).
- Derived Constraints for TSclk50
- +-------------------------------+-------------+-------------+-------------+-------------+-------------+-------------+-------------+
- | | Period | Actual Period | Timing Errors | Paths Analyzed |
- | Constraint | Requirement |-------------+-------------|-------------+-------------|-------------+-------------|
- | | | Direct | Derivative | Direct | Derivative | Direct | Derivative |
- +-------------------------------+-------------+-------------+-------------+-------------+-------------+-------------+-------------+
- |TSclk50 | 20.000ns| 0.925ns| 19.950ns| 0| 0| 0| 367284|
- | TS_nandreadersoc_crg_clk50b | 20.000ns| 5.000ns| 19.950ns| 0| 0| 0| 367284|
- | TS_nandreadersoc_crg_pll_3_ | 6.667ns| 1.730ns| N/A| 0| 0| 0| 0|
- | TS_nandreadersoc_crg_pll_5_ | 13.333ns| 12.381ns| N/A| 0| 0| 367034| 0|
- | TS_nandreadersoc_crg_pll_0_ | 3.333ns| N/A| N/A| 0| 0| 0| 0|
- | TS_nandreadersoc_crg_pll_2_ | 6.667ns| 6.650ns| N/A| 0| 0| 250| 0|
- +-------------------------------+-------------+-------------+-------------+-------------+-------------+-------------+-------------+
- All constraints were met.
- INFO:Timing:2761 - N/A entries in the Constraints List may indicate that the
- constraint is not analyzed due to the following: No paths covered by this
- constraint; Other constraints intersect with this constraint; or This
- constraint was disabled by a Path Tracing Control. Please run the Timespec
- Interaction Report (TSI) via command line (trce tsi) or Timing Analyzer GUI.
- Generating Pad Report.
- All signals are completely routed.
- WARNING:Par:283 - There are 8 loadless signals in this design. This design will cause Bitgen to issue DRC warnings.
- Total REAL time to PAR completion: 41 secs
- Total CPU time to PAR completion: 43 secs
- Peak Memory Usage: 795 MB
- Placer: Placement generated during map.
- Routing: Completed - No errors found.
- Timing: Completed - No errors found.
- Number of error messages: 0
- Number of warning messages: 10
- Number of info messages: 0
- Writing design to file nandreader-nandreadersoc-pipistrello.ncd
- PAR done!
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