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- // zegar 40MHz
- // 1 cykl 25ns
- entity vga is
- port( CLK40 : in std_logic;
- RESET : in std_logic;
- posx : in std_logic_vector(10 downto 0);
- posy : in std_logic_vector(9 downto 0);
- KOLOR : out std_logic_vector(2 downto 0);
- SYN_POZ : out std_logic;
- SYN_PION : out std_logic
- );
- end vga;
- architecture arch_vga of vga is
- signal x : std_logic_vector(10 downto 0);
- signal y : std_logic_vector(9 downto 0);
- process (CLK40, RESET)
- begin
- if (RESET = '1') then
- obr <= "010 000 000 000 000 000 000 000 000 000 --rysunek 10x10
- 000 010 001 000 000 000 000 000 000 000
- 000 000 000 000 000 000 000 000 000 000
- 000 000 000 000 110 000 000 000 000 000
- 000 000 000 000 000 000 000 000 000 000
- 000 000 010 000 000 111 000 000 000 000
- 100 000 000 000 000 000 000 000 000 000
- 000 000 000 000 000 000 000 000 000 000
- 000 000 000 000 000 000 000 000 000 000
- 000 000 000 000 000 000 000 000 000 000";
- x <= (others => '0');
- y <= (others => '0');
- elsif (CLK40''event and CLK = '1') then
- if (x > 800 or y > 600) then
- KOLOR <= "000";
- elsif (x >= posx and x < posx + 10 and y > posy and y < posy + 10) then
- obr <= obr(296 downto 0) & obr(299 downto 297);
- KOLOR <= obr(299 downto 297);
- else
- KOLOR <= "111"; -- biale tlo
- x <= x + 1;
- if (x = 1055) then // koniec linii, jeden mniejsze
- x <= (others => '0');
- y <= y + 1;
- if (y = 627) // koniec klatki, jeden mniejsze
- y <= (other => '0');
- end if;
- end if;
- end if;
- end process;
- SYN_POZ <= '0' when x >= 840 and x <= 968 else '1';
- SYN_PION <= '0' when y >= 601 and y <= 605 else '1';
- end arch_vga;
- kolor <= "000" when x > 1259 or y >= 480 else
- "100" when x >= posx and x < posx + 10 and y >= posy and y < posy + 10 else
- "010";
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