tclConsole-xps Segfault

create_project pmod_test /home/stephen/Programming/Xilinx/MyProjects/pmod_test -part xc7z020clg484-1
set_property board zedBoard [current_project]
set_property target_language VHDL [current_project]
set_property ng.output_hdl_format VHDL [get_filesets sim_1]
create_xps pmod_sub_des
INFO: [Edk 24-176] Creating XPS sub-design source for 'pmod_sub_des'...

Xilinx Platform Studio
Xilinx EDK 14.4 Build EDK_P.49d
Copyright (c) 1995-2012 Xilinx, Inc.  All rights reserved.

XPS% Evaluating file
/home/stephen/Programming/Xilinx/MyProjects/pmod_test/pmod_test.srcs/sources_1/e
dk/pmod_sub_des/__xps/pa/_pmod_sub_des_create.tcl
Created pcores directory
Copied
/home/stephen/Programming/Xilinx/Xilinx_14.4_install/14.4/ISE_DS/EDK/data/xflow/
bitgen_zynq.ut to etc directory
Copied file
/home/stephen/Programming/Xilinx/Xilinx_14.4_install/14.4/ISE_DS/EDK/data/xflow/
fast_runtime_zynq.opt to etc directory

Overriding IP level properties ...

Computing clock values...

Performing IP level DRCs on properties...

Running DRC Tcl procedures for OPTION IPLEVEL_DRC_PROC...

Checking platform address map ...
Created backup of etc/bitgen.ut to etc/bitgen.ut.virtex5
Copied
/home/stephen/Programming/Xilinx/Xilinx_14.4_install/14.4/ISE_DS/EDK/data/xflow/
bitgen_zynq.ut to etc directory
Created backup of etc/fast_runtime.opt to etc/fast_runtime.opt.virtex5
Copied file
/home/stephen/Programming/Xilinx/Xilinx_14.4_install/14.4/ISE_DS/EDK/data/xflow/
fast_runtime_zynq.opt to etc directory
No changes to be saved in MHS file
Saved project XMP file
Saved Make file
INFO: [Edk 24-189] XPS sub-design source created

INFO: [Edk 24-185] Launching XPS GUI for configuring XPS sub-design source 'pmod_sub_des'. The GUI will be up in a moment...
INFO: [Edk 24-173]  After configuring the source design, please select 'File->Exit' from the XPS GUI to exit from XPS. The source will be added to the current project automatically.

Xilinx Platform Studio
Xilinx EDK 14.4 Build EDK_P.49d
Copyright (c) 1995-2012 Xilinx, Inc.  All rights reserved.

Launching XPS GUI...
INFO:EDK - Simulation, Implementation and Device configuration flows are
   disabled in XPS when launched from PlanAhead. All these features are
   available in PlanAhead.
MainWindow
INTERNAL_ERROR:PersonalityModule:baspmspec.c:1751:1.79 - Could not load
   definition file <qvirtex6.acd>


INFO: [Edk 24-127] XPS completed
create_xps: Time (s): cpu = 00:00:20 ; elapsed = 00:00:21 . Memory (MB): peak = 1045.520 ; gain = 0.000
set_property top pmod [current_fileset]
add_files -norecurse -scan_for_includes
set_property top pmod_sub_des [current_fileset]
export_hardware [get_files /home/stephen/Programming/Xilinx/MyProjects/pmod_test/pmod_test.srcs/sources_1/edk/pmod_sub_des/pmod_sub_des.xmp]
INFO: [Edk 24-140] Exporting hardware platform for 'pmod_sub_des'...