Advertisement
Not a member of Pastebin yet?
Sign Up,
it unlocks many cool features!
- 00000001 R0=00000000 R1=00000000 R2=00000000 R3=00000000 R4=00000000 R5=00000000 R6=00000000 R7=00000000 R8=00000000 R9=00000000 R10=00000000 R11=00000000 R12=00000000 SP=00000000 LR=00000000 PSR=400001D3 F0=FFFFFFFFFFFFFFFF F1=FFFFFFFFFFFFFFFF F2=FFFFFFFFFFFFFFFF F3=FFFFFFFFFFFFFFFF F4=FFFFFFFFFFFFFFFF F5=FFFFFFFFFFFFFFFF F6=FFFFFFFFFFFFFFFF F7=FFFFFFFFFFFFFFFF FPS=FFFFFFFF
- 00000001 ROM_EXP:rom_exception B rom_start ; Branch
- 00000001 ROM_EXP:rom_exception B rom_start ; Branch
- 00000001 ROM:rom_start LDR R0, =OMAP3430_reg_CONTROL_STATUS ; Control Module Status register: latches system information at reset time R0=480022F0
- 00000001 ROM:rom_start+4 LDR R0, [R0] ; Control Module Status register: latches system information at reset time R0=0000030F
- 00000001 ROM:rom_start+8 MOV R0, R0,LSR#8 ; R0 = R0 * 256; R0=00000003
- 00000001 ROM:rom_start+C AND R0, R0, #0b111 ; Rd = Op1 & Op2
- 00000001 ROM:rom_start+10 CMP R0, #0b11 ; Set cond. codes on Op1 - Op2 C=1
- 00000001 ROM:rom_start+14 BNE boot_normal ; go if R0 is not equal [xxxxx011]
- 00000001 ROM:rom_start:boot_fast LDR R0, =OMAP3430_reg_CONTROL_STATUS ; Control Module Status register: latches system information at reset time R0=480022F0
- 00000001 ROM:rom_start+1C LDR R0, [R0] ; Control Module Status register: latches system information at reset time R0=0000030F
- 00000001 ROM:rom_start+20 MOV R6, R0 ; Rd = Op2 R6=0000030F
- 00000001 ROM:rom_start+24 AND R0, R0, #0b11111 ; Rd = Op1 & Op2 R0=0000000F
- 00000001 ROM:rom_start+28 CMP R0, #0b11111 ; if CONTROL STATUS register is [xxx11111] bits C=0 Z=0 N=1
- 00000001 ROM:rom_start+2C BLEQ boot_fast_XIP ; Branch with Link
- 00000001 ROM:rom_start:boot_normal MSR CPSR_c, #0b11010011 ; Transfer Register to PSR
- 00000001 ROM:rom_start+34 LDR SP, =unk_4020FCAC ; Load from Memory SP=4020FCAC
- 00000001 ROM:rom_start+38 LDR R4, =0x14000 ; Set Nonsecure Vector Base R4=00014000
- 00000001 ROM:rom_start+3C MCR p15, 0, R4,c12,c0, 0 ; Write Secure or Nonsecure Vector Base Address Register
- 00000001 ROM:rom_start+40 BL prepare_tracing_data ; Branch with Link LR=40014904
- 00000001 ROM:prepare_tracing_data LDR R0, =OMAP3430_reg_PRM_RSTST ; This register logs the global reset sources. Each bit is set upon release of the domain reset signal. Must be cleared by software R0=48307258
- 00000001 ROM:prepare_tracing_data+4 LDR R0, [R0] ; Load from Memory R0=00000001
- 00000001 ROM:prepare_tracing_data+8 AND R0, R0, #1 ; Rd = Op1 & Op2
- 00000001 ROM:prepare_tracing_data+C CMP R0, #1 ; Set cond. codes on Op1 - Op2 C=1 Z=1 N=0
- 00000001 ROM:prepare_tracing_data+10 BNE loc_40014858 ; Branch
- 00000001 ROM:prepare_tracing_data+14 LDR R0, =unk_4020FFBC ; Load from Memory R0=4020FFBC
- 00000001 ROM:prepare_tracing_data+18 MOV R1, #0 ; Rd = Op2
- 00000001 ROM:prepare_tracing_data+1C STR R1, [R0] ; Store to Memory
- 00000001 ROM:prepare_tracing_data+20 STR R1, [R0,#(unk_4020FFC0 - 0x4020FFBC)] ; Store to Memory
- 00000001 ROM:prepare_tracing_data+24 B loc_4001487C ; Branch
- 00000001 ROM:prepare_tracing_data:loc_4001487C LDR R0, =memory_buffer ; Load from Memory R0=4020FFB0
- 00000001 ROM:prepare_tracing_data+50 MOV R1, #0 ; Rd = Op2
- 00000001 ROM:prepare_tracing_data+54 STR R1, [R0] ; Store to Memory
- 00000001 ROM:prepare_tracing_data+58 STR R1, [R0,#(unk_4020FFB4 - 0x4020FFB0)] ; Store to Memory
- 00000001 ROM:prepare_tracing_data+5C LDR R0, =OMAP3430_reg_PRM_RSTST ; This register logs the global reset sources. Each bit is set upon release of the domain reset signal. Must be cleared by software R0=48307258
- 00000001 ROM:prepare_tracing_data+60 LDR R1, [R0] ; Load from Memory R1=00000001
- 00000001 ROM:prepare_tracing_data+64 LDR R0, =unk_4020FFB8 ; Load from Memory R0=4020FFB8
- 00000001 ROM:prepare_tracing_data+68 STR R1, [R0] ; Store to Memory
- 00000001 ROM:prepare_tracing_data+6C BX LR ; Branch to/from Thumb mode
- 00000001 ROM:rom_start+44 LDR R0, =memory_buffer ; Load from Memory R0=4020FFB0
- 00000001 ROM:rom_start+48 LDR R1, [R0] ; Load from Memory R1=00000000
- 00000001 ROM:rom_start+4C MOV R0, #tracing_Reset ; Rd = Op2 R0=00000001
- 00000001 ROM:rom_start+50 ORR R1, R1, R0 ; Public ROM code C main R1=00000001
- 00000001 ROM:rom_start+54 LDR R0, =memory_buffer ; Load from Memory R0=4020FFB0
- 00000001 ROM:rom_start+58 STR R1, [R0] ; Store to Memory
- 00000001 ROM:rom_start+5C MRC p15, 0, R0,c1,c0, 0 ; Read Control Register R0=00C50078
- 00000001 ROM:rom_start+60 ORR R0, R0, #0b1100000000000 ; [13] - High exception vectors selected, address range = 0xFFFF0000-0xFFFF001C. R0=00C51878
- 00000001 ROM:rom_start+64 MCR p15, 0, R0,c1,c0, 0 ; Write Control Register
- 00000001 ROM:rom_start+68 B memory_init ; Branch
- 00000001 ROM:rom_start:memory_init B memory_init ; Branch
- 00000001 ROM:memory_init B loc_40014710 ; Branch
- 00000001 ROM:memory_init:loc_40014710 ADR R0, dword_40014740 ; Load address R0=40014740
- 00000001 ROM:memory_init+C LDMIA R0, {R10,R11} ; Load Block from Memory R10=000070F0 R11=00007120
- 00000001 ROM:memory_init+10 ADD R10, R10, R0 ; Rd = Op1 + Op2 R10=4001B830
- 00000001 ROM:memory_init+14 ADD R11, R11, R0 ; Rd = Op1 + Op2 R11=4001B860
- 00000001 ROM:memory_init+18 SUB R7, R10, #1 ; Rd = Op1 - Op2 R7=4001B82F
- 00000001 ROM:memory_init:loc_40014724 CMP R10, R11 ; Set cond. codes on Op1 - Op2 C=0 Z=0 N=1
- 00000001 ROM:memory_init+20 BEQ pre_main ; Branch
- 00000001 ROM:memory_init:loc_4001472C LDMIA R10!, {R0-R3} ; Load Block from Memory R0=0001B860 R1=4020FCB0 R2=0000002C R3=00014748 R10=4001B840
- 00000001 ROM:memory_init+28 ADR LR, loc_40014724 ; Load address LR=40014724
- 00000001 ROM:memory_init+2C TST R3, #1 ; Set cond. codes on Op1 & Op2 Z=1 N=0
- 00000001 ROM:memory_init+30 SUBNE PC, R7, R3 ; Rd = Op1 - Op2
- 00000001 ROM:memory_init+34 BX R3 ; Branch to/from Thumb mode
Advertisement
Add Comment
Please, Sign In to add comment
Advertisement