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  1. /* arch/arm/mach-msm/include/mach/msm_iomap.h
  2.  *
  3.  * Copyright (C) 2007 Google, Inc.
  4.  * Author: Brian Swetland <swetland@google.com>
  5.  *
  6.  * This software is licensed under the terms of the GNU General Public
  7.  * License version 2, as published by the Free Software Foundation, and
  8.  * may be copied, distributed, and modified under those terms.
  9.  *
  10.  * This program is distributed in the hope that it will be useful,
  11.  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  12.  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  13.  * GNU General Public License for more details.
  14.  *
  15.  *
  16.  * The MSM peripherals are spread all over across 768MB of physical
  17.  * space, which makes just having a simple IO_ADDRESS macro to slide
  18.  * them into the right virtual location rough.  Instead, we will
  19.  * provide a master phys->virt mapping for peripherals here.
  20.  *
  21.  */
  22.  
  23. #ifndef __ASM_ARCH_MSM_IOMAP_H
  24. #define __ASM_ARCH_MSM_IOMAP_H
  25.  
  26. #include <asm/sizes.h>
  27.  
  28. /* Physical base address and size of peripherals.
  29.  * Ordered by the virtual base addresses they will be mapped at.
  30.  *
  31.  * MSM_VIC_BASE must be an value that can be loaded via a "mov"
  32.  * instruction, otherwise entry-macro.S will not compile.
  33.  *
  34.  * If you add or remove entries here, you'll want to edit the
  35.  * msm_io_desc array in arch/arm/mach-msm/io.c to reflect your
  36.  * changes.
  37.  *
  38.  */
  39.  
  40. #ifdef __ASSEMBLY__
  41. #define IOMEM(x)    x
  42. #else
  43. #define IOMEM(x)    ((void __force __iomem *)(x))
  44. #endif
  45.  
  46. #if defined(CONFIG_ARCH_MSM_ARM11)
  47. #define _PHYS(a11,scorp) (a11)
  48. #endif
  49. #if defined(CONFIG_ARCH_MSM_SCORPION)
  50. #define _PHYS(a11,scorp) (scorp)
  51. #endif
  52.  
  53. #define MSM_VIC_BASE          IOMEM(0xF8000000)
  54. #define MSM_VIC_PHYS          _PHYS(0xC0000000,0xAC000000)
  55. #define MSM_VIC_SIZE          SZ_4K
  56.  
  57. #define MSM_CSR_BASE          IOMEM(0xF8001000)
  58. #define MSM_CSR_PHYS          _PHYS(0xC0100000,0xAC100000)
  59. #define MSM_CSR_SIZE          SZ_4K
  60.  
  61. #define MSM_GPT_PHYS          MSM_CSR_PHYS
  62. #define MSM_GPT_BASE          MSM_CSR_BASE
  63. #define MSM_GPT_SIZE          SZ_4K
  64.  
  65. #define MSM_DMOV_BASE         IOMEM(0xF8002000)
  66. #define MSM_DMOV_PHYS         0xA9700000
  67. #define MSM_DMOV_SIZE         SZ_4K
  68.  
  69. #define MSM_GPIO1_BASE        IOMEM(0xF8003000)
  70. #define MSM_GPIO1_PHYS        _PHYS(0xA9200000,0xA9000000)
  71. #define MSM_GPIO1_SIZE        SZ_4K
  72.  
  73. #define MSM_GPIO2_BASE        IOMEM(0xF8004000)
  74. #define MSM_GPIO2_PHYS        _PHYS(0xA9300000,0xA9100000)
  75. #define MSM_GPIO2_SIZE        SZ_4K
  76.  
  77. #define MSM_CLK_CTL_BASE      IOMEM(0xF8005000)
  78. #define MSM_CLK_CTL_PHYS      0xA8600000
  79. #define MSM_CLK_CTL_SIZE      SZ_4K
  80.  
  81. #if defined(CONFIG_ARCH_MSM_SCORPION)
  82. #define MSM_SIRC_BASE         IOMEM(0xF8006000)
  83. #define MSM_SIRC_PHYS         0xAC200000
  84. #define MSM_SIRC_SIZE         SZ_4K
  85.  
  86. #define MSM_SCPLL_BASE        IOMEM(0xF8007000)
  87. #define MSM_SCPLL_PHYS        0xA8800000
  88. #define MSM_SCPLL_SIZE        SZ_4K
  89.  
  90. #define MSM_TCSR_BASE         IOMEM(0xF8008000)
  91. #define MSM_TCSR_PHYS         0xA8700000
  92. #define MSM_TCSR_SIZE         SZ_4K
  93. #endif
  94.  
  95. #define MSM_MDP_BASE          IOMEM(0xF8010000)
  96. #define MSM_MDP_PHYS          0xAA200000
  97. #define MSM_MDP_SIZE          0x000F0000
  98.  
  99. #define MSM_SHARED_RAM_BASE   IOMEM(0xF8100000)
  100. #if defined(CONFIG_ARCH_QSD8X50)
  101. #define MSM_SHARED_RAM_PHYS   0x00100000
  102. #else
  103. #define MSM_SHARED_RAM_PHYS   0x01F00000
  104. #endif
  105. #define MSM_SHARED_RAM_SIZE   SZ_1M
  106.  
  107. #define MSM_MDC_BASE          IOMEM(0xF8200000)
  108. #define MSM_MDC_PHYS          0xAA500000
  109. #define MSM_MDC_SIZE          SZ_1M
  110.  
  111. #define MSM_AD5_BASE          IOMEM(0xF8300000)
  112. #define MSM_AD5_PHYS          0xAC000000
  113. #define MSM_AD5_SIZE          (SZ_1M*13)
  114.  
  115. #ifdef CONFIG_MSM_DEBUG_UART
  116. #define MSM_DEBUG_UART_BASE   0xF9000000
  117. #if CONFIG_MSM_DEBUG_UART == 1
  118. #define MSM_DEBUG_UART_PHYS   MSM_UART1_PHYS
  119. #elif CONFIG_MSM_DEBUG_UART == 2
  120. #define MSM_DEBUG_UART_PHYS   MSM_UART2_PHYS
  121. #elif CONFIG_MSM_DEBUG_UART == 3
  122. #define MSM_DEBUG_UART_PHYS   MSM_UART3_PHYS
  123. #endif
  124. #define MSM_DEBUG_UART_SIZE   SZ_4K
  125. #endif
  126.  
  127. #define MSM_GPIOCFG1_BASE     IOMEM(0xF9004000)
  128. #define MSM_GPIOCFG1_PHYS     _PHYS(0xA9000000,0xA8E00000)
  129. #define MSM_GPIOCFG1_SIZE     SZ_4K
  130.  
  131. #define MSM_GPIOCFG2_BASE     IOMEM(0xF9005000)
  132. #define MSM_GPIOCFG2_PHYS     _PHYS(0xA9100000,0xA8F00000)
  133. #define MSM_GPIOCFG2_SIZE     SZ_4K
  134.  
  135. #define MSM_TS_BASE           IOMEM(0xF9006000)
  136. #define MSM_TS_PHYS           0xAA300000
  137. #define MSM_TS_SIZE           SZ_4K
  138.  
  139. #define MSM_SSBI_BASE         IOMEM(0xF9008000)
  140. #define MSM_SSBI_PHYS         0xA8100000
  141. #define MSM_SSBI_SIZE         SZ_4K
  142.  
  143. #define MSM_TSSC_BASE         IOMEM(0xF9009000)
  144. #define MSM_TSSC_PHYS         0xAA300000
  145. #define MSM_TSSC_SIZE         SZ_4K
  146.  
  147. /* Have to be checked
  148. #define MSM_AXIGS_BASE        IOMEM(0xF900A000)
  149. #define MSM_AXIGS_PHYS        0xA8250000
  150. #define MSM_AXIGS_SIZE        SZ_4K
  151.  
  152. #define MSM_IMEM_BASE         IOMEM(0xF900B000)
  153. #define MSM_IMEM_PHYS         0xA8500000
  154. #define MSM_IMEM_SIZE         0x100
  155. */
  156.  
  157. #define MSM_UART1_PHYS        0xA9A00000
  158. #define MSM_UART1_SIZE        SZ_4K
  159.  
  160. #define MSM_UART2_PHYS        0xA9B00000
  161. #define MSM_UART2_SIZE        SZ_4K
  162.  
  163. #define MSM_UART3_PHYS        0xA9C00000
  164. #define MSM_UART3_SIZE        SZ_4K
  165.  
  166. #define MSM_SDC1_PHYS         _PHYS(0xA0400000,0xA0300000)
  167. #define MSM_SDC1_SIZE         SZ_4K
  168. #define MSM_SDC2_PHYS         _PHYS(0xA0500000,0xA0400000)
  169. #define MSM_SDC2_SIZE         SZ_4K
  170. #define MSM_SDC3_PHYS         _PHYS(0xA0600000,0xA0500000)
  171. #define MSM_SDC3_SIZE         SZ_4K
  172. #define MSM_SDC4_PHYS         _PHYS(0xA0700000,0xA0600000)
  173. #define MSM_SDC4_SIZE         SZ_4K
  174.  
  175. #define MSM_I2C_PHYS          0xA9900000
  176. #define MSM_I2C_SIZE          SZ_4K
  177.  
  178. #define MSM_HSUSB_PHYS        0xA0800000
  179. #define MSM_HSUSB_SIZE        SZ_4K
  180.  
  181. #define MSM_PMDH_PHYS         0xAA600000
  182. #define MSM_PMDH_SIZE         SZ_4K
  183.  
  184. #define MSM_EMDH_PHYS         0xAA700000
  185. #define MSM_EMDH_SIZE         SZ_4K
  186.  
  187. #define MSM_VFE_PHYS          0xA0F00000
  188. #define MSM_VFE_SIZE          SZ_1M
  189.  
  190. #define MSM_UART1DM_PHYS      0xA0200000
  191. #define MSM_UART2DM_PHYS      0xA0300000
  192.  
  193. #if defined(CONFIG_ARCH_QSD8X50)
  194. #define MSM_GPU_REG_PHYS      0xA0000000
  195. #define MSM_GPU_REG_SIZE      0x00020000
  196. #endif
  197.  
  198. #if defined(CONFIG_ARCH_QSD8X50)
  199. #define MSM_SPI_PHYS          0xA1200000
  200. #define MSM_SPI_SIZE          SZ_4K
  201. #endif
  202.  
  203. // Originally this does not need to be defined
  204. // but is required to make early_ramconsole work
  205. // These values must match the values used in
  206. // the defconfig.
  207. #define MSM_RAM_CONSOLE_BASE    IOMEM(0xF9100000)
  208. #define MSM_RAM_CONSOLE_PHYS    0x2FFC0000
  209. #define MSM_RAM_CONSOLE_SIZE    0x00040000
  210.  
  211. #endif
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