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  1. /*
  2.  * Copyright (C) 2005 Vivien Chappelier -- Inventel/Thomson
  3.  *
  4.  * This program is free software; you can redistribute it and/or
  5.  * modify it under the terms of the GNU General Public License
  6.  * as published by the Free Software Foundation; either version 2
  7.  * of the License, or (at your option) any later version.
  8.  *
  9.  * This program is distributed in the hope that it will be useful,
  10.  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  11.  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  12.  * GNU General Public License for more details.
  13.  *
  14.  * You should have received a copy of the GNU General Public License
  15.  * along with this program; if not, write to the Free Software
  16.  * Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA  02111-1307, USA.
  17.  */
  18.  
  19. #include <linux/init.h>
  20. #include <linux/delay.h>
  21. #include <linux/interrupt.h>
  22. #include <linux/smp.h>
  23. #include <linux/kernel_stat.h>
  24. #include <linux/spinlock.h>
  25.  
  26. #include <asm/mmu_context.h>
  27. #include <asm/io.h>
  28. #include <asm/bcm963xx/bcm_intr.h>
  29. #include <linux/module.h>
  30.  
  31. #define DEBUG
  32. #undef VDEBUG
  33.  
  34. #ifdef DEBUG
  35. #define dbg printk
  36. #else
  37. #define dbg(...) do { } while(0);
  38. #endif
  39.  
  40. #ifdef VDEBUG
  41. #define vdbg printk
  42. #else
  43. #define vdbg(...) do { } while(0);
  44. #endif
  45.  
  46. extern void show_registers(struct pt_regs *regs);
  47. extern void show_regs(struct pt_regs *regs);
  48.  
  49. #define TIMEOUT (HZ/4) /* time to wait for the other core to boot */
  50.  
  51. /* CMT bits */
  52. #define BRCM_CONFIG0_CMT  (1 << 18) /* concurrent multi-threading support */
  53. #define BRCM_CONFIG0_SIC  (1 << 12) /* split I-cache for each thread */
  54. #define CMT_INT_XIR_IP4   (1 << 31) /* external interrupt 4 routing */
  55. #define CMT_INT_XIR_IP3   (1 << 30) /* external interrupt 3 routing */
  56. #define CMT_INT_XIR_IP2   (1 << 29) /* external interrupt 2 routing */
  57. #define CMT_INT_XIR_IP1   (1 << 28) /* external interrupt 1 routing */
  58. #define CMT_INT_XIR_IP0   (1 << 27) /* external interrupt 0 routing */
  59. #define CMT_INT_SIR_IP1   (1 << 16) /* software interrupt 1 routing */
  60. #define CMT_INT_SIR_IP0   (1 << 15) /* software interrupt 0 routing */
  61. #define CMT_INT_NMI_MASK  3
  62. #define CMT_INT_NMI_T0    1         /* NMI interrupt routing to thread 0 */
  63. #define CMT_INT_NMI_T1    2         /* NMI interrupt routing to thread 1 */
  64.  
  65. #define CMT_PRIO_TP1      (1 <<  5) /* give exception priority to thread 1 */
  66. #define CMT_PRIO_TP0      (1 <<  4) /* give exception priority to thread 0 */
  67. #define CMT_RSTSE         (1 <<  0) /* thread 1 reset */
  68.  
  69. #define CMT_LOCAL_TID     (1 << 31) /* thread identifier */
  70.  
  71. /*
  72.  * Return the thread ID where this code is executed
  73.  */
  74. int brcm_cmt_id(void)
  75. {
  76.         unsigned int local;
  77.  
  78.         local = read_c0_brcm_cmt_local();
  79.  
  80.         return((local & CMT_LOCAL_TID) != 0);
  81. }
  82.  
  83. /*
  84.  * SMP init and finish on secondary CPUs
  85.  */
  86. void bcm6358_smp_info(void)
  87. {
  88.         unsigned int config;
  89.         unsigned int introuting;
  90.  
  91.         config = read_c0_brcm_config0();
  92.  
  93.         if(!(config & BRCM_CONFIG0_CMT)) {
  94.                 printk("SMP not supported on this processor\n");
  95.                 return;
  96.         }
  97.  
  98.         if(config & BRCM_CONFIG0_SIC)
  99.                 printk("Multicore CPU with split I-cache\n");
  100.         else
  101.                 printk("Multicore CPU with shared I-cache\n");
  102.  
  103.         introuting =  read_c0_brcm_cmt_int();
  104.         printk("Interrupt routing:\n");
  105.         if(introuting & CMT_INT_XIR_IP4)
  106.                 printk(" IP4: set A to T1, set B to T0\n");
  107.         else
  108.                 printk(" IP4: set A to T0, set B to T1\n");
  109.         if(introuting & CMT_INT_XIR_IP3)
  110.                 printk(" IP3: set A to T1, set B to T0\n");
  111.         else
  112.                 printk(" IP3: set A to T0, set B to T1\n");
  113.         if(introuting & CMT_INT_XIR_IP2)
  114.                 printk(" IP2: set A to T1, set B to T0\n");
  115.         else
  116.                 printk(" IP2: set A to T0, set B to T1\n");
  117.         if(introuting & CMT_INT_XIR_IP1)
  118.                 printk(" IP1: set A to T1, set B to T0\n");
  119.         else
  120.                 printk(" IP1: set A to T0, set B to T1\n");
  121.         if(introuting & CMT_INT_XIR_IP0)
  122.                 printk(" IP0: set A to T1, set B to T0\n");
  123.         else
  124.                 printk(" IP0: set A to T0, set B to T1\n");
  125.         if(introuting & CMT_INT_SIR_IP1)
  126.                 printk(" SOFT1: set A to T1, set B to T0\n");
  127.         else
  128.                 printk(" SOFT1: set A to T0, set B to T1\n");
  129.         if(introuting & CMT_INT_SIR_IP0)
  130.                 printk(" SOFT0: set A to T1, set B to T0\n");
  131.         else
  132.                 printk(" SOFT0: set A to T0, set B to T1\n");
  133.        
  134.         if((introuting & CMT_INT_NMI_MASK) == 1)
  135.                 printk(" NMI routed to thread 0\n");
  136.         else
  137.                 printk(" NMI routed to thread 1\n");
  138. }
  139.  
  140. /* This mailbox contains the ipi message. It is fast as the CPU cores
  141.    share the same data cache. */
  142. struct letter {
  143.         unsigned int action;
  144.         spinlock_t lock;
  145. };
  146.  
  147. static struct letter mailbox[NR_CPUS];
  148.  
  149. void core_send_ipi(int cpu, unsigned int action)
  150. {
  151.         unsigned int softint;
  152.         unsigned long flags;
  153.  
  154.         vdbg("core_send_ipi cpu=%d action=0x%08x\n", cpu, action);
  155.  
  156.         if (cpu)
  157.                 softint = CAUSEF_IP1;
  158.         else
  159.                 softint = CAUSEF_IP0;
  160.  
  161.         spin_lock_irqsave(&mailbox[cpu].lock, flags);
  162.         mailbox[cpu].action |= action;
  163.         set_c0_cause(softint);
  164.         spin_unlock_irqrestore(&mailbox[cpu].lock, flags);
  165. }
  166.  
  167. /* Schedule a tasklet on the other core */
  168. static DEFINE_SPINLOCK(smp_tasklet_lock);
  169. struct tasklet_struct *smp_tasklet;
  170.  
  171. void smp_tasklet_hi_schedule(int cpu, struct tasklet_struct *tasklet)
  172. {
  173.         spin_lock(&smp_tasklet_lock);
  174.         smp_tasklet = tasklet;
  175.         core_send_ipi(cpu, SMP_SCHEDULE_TASKLET);
  176.         while (spin_is_locked(&smp_tasklet_lock))
  177.                 core_send_ipi(cpu, 0);
  178. }
  179.  
  180. extern void local_timer_interrupt(int irq, void *dev_id, struct pt_regs *regs);
  181.  
  182. static irqreturn_t
  183. bcm6358_mailbox_interrupt(int irq, void *dev_id, struct pt_regs *regs)
  184. {
  185.         int cpu = smp_processor_id();
  186.         unsigned int action;
  187.         unsigned int softint;
  188.  
  189.         if (cpu)
  190.                 softint = CAUSEF_IP1;
  191.         else
  192.                 softint = CAUSEF_IP0;
  193.  
  194.         /* Open the mailbox and figure out what we're supposed to do */
  195.         spin_lock(&mailbox[cpu].lock);
  196.         action = mailbox[cpu].action;
  197.         mailbox[cpu].action = 0;
  198.         clear_c0_cause(softint);
  199.         spin_unlock(&mailbox[cpu].lock);
  200.  
  201.         vdbg("ipi on T%d, cpu %d, action = 0x%08x\n",
  202.             brcm_cmt_id(), cpu, action);
  203.  
  204.         /*
  205.          * Nothing to do for SMP_RESCHEDULE_YOURSELF;
  206.          * returning from the interrupt will do the reschedule for us
  207.          */
  208.         if (action & SMP_CALL_FUNCTION)
  209.                 smp_call_function_interrupt();
  210.  
  211.         /* The second timer interrupt is simulated using an ipi */
  212.         if (action & SMP_TIMER_INTERRUPT)
  213.                 local_timer_interrupt(irq, NULL, regs);
  214.  
  215.         /* Allows to schedule a tasklet on a different core */
  216.         if (action & SMP_SCHEDULE_TASKLET) {
  217.                 tasklet_hi_schedule(smp_tasklet);
  218.                 spin_unlock(&smp_tasklet_lock);
  219.         }
  220.  
  221. #ifdef DEBUG
  222.         /* Dump stack frame for debugging */
  223.         if (action & SMP_DUMP_STACK) {
  224.                 if(user_mode(regs))
  225.                         show_regs(regs);
  226.                 else
  227.                         show_registers(regs);
  228.         }
  229. #endif
  230.  
  231.         return(IRQ_HANDLED);
  232. }
  233.  
  234. /*
  235.  * Common setup before any secondaries are started
  236.  */
  237. void __init prom_prepare_cpus(unsigned int max_cpus)
  238. {
  239.         int cpu;
  240.         unsigned int config;
  241.  
  242.         /* set up the primary cpu info */
  243.         cpus_clear(phys_cpu_present_map);
  244.         cpu_set(0, phys_cpu_present_map);
  245.         cpu_set(0, cpu_online_map);
  246.         __cpu_number_map[0] = 0;
  247.         __cpu_logical_map[0] = 0;
  248.  
  249.         config = read_c0_brcm_config0();
  250.  
  251.         /* check for a secondary cpu */
  252.         if(config & BRCM_CONFIG0_CMT) {
  253.                 cpu_set(1, phys_cpu_present_map);
  254.                 __cpu_logical_map[1] = 0; /* same physical CPU */
  255.         } else
  256.                 return;
  257.  
  258.         /* initialize the mailboxes */
  259.         for(cpu = 0; cpu < NR_CPUS; cpu++) {
  260.                 spin_lock_init(&mailbox[cpu].lock);
  261.                 mailbox[cpu].action = 0;
  262.         }
  263.  
  264.         /* register ipi interrupt for current processor */
  265.         if(request_irq(INTERRUPT_ID_SOFTWARE_0, bcm6358_mailbox_interrupt,
  266.                        SA_INTERRUPT, "cpu0soft", 0)) {
  267.                 printk("Cannot register ipi interrupt\n");
  268.                 return;
  269.         }
  270.  
  271.         /* register ipi interrupt for second processor */
  272.         if(request_irq(INTERRUPT_ID_SOFTWARE_1, bcm6358_mailbox_interrupt,
  273.                        SA_SAMPLE_RANDOM | SA_INTERRUPT, "cpu1soft", 0)) {
  274.                 printk("Cannot register ipi interrupt\n");
  275.                 return;
  276.         }
  277. }
  278.  
  279. /*
  280.  * Setup the PC, SP, and GP of a secondary processor and start it running:
  281.  *
  282.  * The secondary core is reset and starts running at 0xbfc00000. The bootloader
  283.  * detects it is running on the secondary core and does the following instead
  284.  * of running the normal boot code:
  285.  *   - flush the I-cache
  286.  *   - enable software interrupt 1
  287.  *   - route software interrupt 0 and 1 across cores
  288.  *   - wait for interrupt
  289.  * In the meantime, the primary core polls the common interrupt routing
  290.  * register until the software interrupts are crossed, meaning the secondary
  291.  * core is ready to receive interrupts. It then stores the values of the
  292.  * desired PC, SP and GP in the cmt_bootstrap_* variables. There is no need to
  293.  * flush the D-cache here as it is shared between the cores. The interrupt
  294.  * vector is then changed to cmt_bootstrap_IRQ (which includes flushing the
  295.  * corresponding entry in the primary core I-cache) and an interrupt is sent
  296.  * to the secondary core. The secondary core takes the interrupt, jumping to
  297.  * cmt_bootstrap_IRQ, which loads SP and GP from the cmt_bootstrap_* variables
  298.  * and stores cmt_bootstrap_pc to the CP0 EPC register. It finally returns from
  299.  * interrupt to the desired PC.
  300.  */
  301. extern asmlinkage void cmt_bootstrap_IRQ(void);
  302. unsigned long cmt_bootstrap_sp;
  303. unsigned long cmt_bootstrap_gp;
  304. unsigned long cmt_bootstrap_pc;
  305. extern asmlinkage void invtlIRQ(void);
  306.  
  307. DEFINE_SPINLOCK(cmt_bootstrap_lock);
  308.  
  309. void prom_boot_secondary(int cpu, struct task_struct *idle)
  310. {
  311.         unsigned int ctrl;
  312.         unsigned int flags;
  313.         unsigned long timeout = TIMEOUT;
  314.  
  315.         dbg("booting secondary core\n");
  316.  
  317.         /* take thread 1 out of reset */
  318.         ctrl = read_c0_brcm_cmt_ctrl();
  319.         write_c0_brcm_cmt_ctrl(ctrl | CMT_RSTSE | CMT_PRIO_TP0);
  320.  
  321.         dbg("secondary core reset\n");
  322.  
  323.         /* wait for thread 1 to be ready to receive interrupts */
  324.         timeout += jiffies;
  325.         while (time_before(jiffies, timeout) &&
  326.               !(read_c0_brcm_cmt_int() & CMT_INT_SIR_IP1));
  327.         if (time_after_eq(jiffies, timeout)) {
  328.                 printk(KERN_ERR "secondary CPU did not respond!\n");
  329.                 return;
  330.         }
  331.  
  332.         dbg("secondary core ready\n");
  333.  
  334.         /* store the desired values for the secondary processor registers */
  335.         cmt_bootstrap_pc = (unsigned long)&smp_bootstrap;
  336.         cmt_bootstrap_sp = __KSTK_TOS(idle);
  337.         cmt_bootstrap_gp = (unsigned long)idle->thread_info;
  338.  
  339.         /* install the bootstrap interrupt handler */
  340.         local_irq_save(flags);
  341.         set_except_vector(0, cmt_bootstrap_IRQ);
  342.  
  343.         /* send an ipi to thread 1 */
  344.         spin_lock(&cmt_bootstrap_lock);
  345.         set_c0_cause(CAUSEF_IP1);
  346.  
  347.         /* wait until the interrupt is taken by thread 1 */
  348.         while(spin_is_locked(&cmt_bootstrap_lock))
  349.                 mb();
  350.  
  351.         /* restore the normal irq handler */
  352.         set_except_vector(0, invtlIRQ);
  353.         local_irq_restore(flags);
  354. }
  355.  
  356. /*
  357.  * Code to run on secondary just after probing the CPU
  358.  */
  359. extern void __init brcm_irq_setup(void);
  360.  
  361. void prom_init_secondary(void)
  362. {
  363.         spin_unlock(&cmt_bootstrap_lock);
  364.  
  365.         /* install the interrupt exception vector */
  366.         /* this is needed to ensure the bootstrap vector */
  367.         /* is not stalling in the I-cache of TP1 */
  368.         brcm_irq_setup();
  369. }
  370.  
  371. /*
  372.  * Do any tidying up before marking online and running the idle
  373.  * loop
  374.  */
  375.  
  376. void prom_smp_finish(void)
  377. {
  378.         local_irq_enable();
  379. }
  380.  
  381. /*
  382.  * Final cleanup after all secondaries booted
  383.  */
  384. void prom_cpus_done(void)
  385. {
  386.         bcm6358_smp_info();
  387. }
  388.  
  389. /*
  390.  * EBI access locking
  391.  *   When one thread accesses the EBI bus while the other is doing a memory
  392.  *   read, there is a hazard that the EBI access will be done twice. Therefore
  393.  *   we must lock the other core out of the way when doing EBI accesses that
  394.  *   are sensitive to multiple read/writes, such as flash accesses.
  395.  *   The other core is caught by an ipi and locked waiting for the EBI lock.
  396.  *   We use the NMI routing in the shared CMT interrupt routing register as the
  397.  *   lock to ensure no memory access is made on the other core while waiting
  398.  *   for the lock. Any other common CP0 R/W location would do the trick.
  399.  */
  400. DEFINE_SPINLOCK(bus_lock);
  401.  
  402. void ebi_lock_ipi(void *info)
  403. {
  404.         int introuting;
  405.  
  406.         introuting = read_c0_brcm_cmt_int();
  407.         introuting &= ~CMT_INT_NMI_MASK;
  408.         introuting |= CMT_INT_NMI_T1;
  409.         write_c0_brcm_cmt_int(introuting);
  410.         while ((read_c0_brcm_cmt_int() & 3) == 2);
  411. }
  412.  
  413. void ebi_lock(void)
  414. {
  415.         if (num_online_cpus() < 2)
  416.                 return;
  417.  
  418.         spin_lock(&bus_lock);
  419.         while((read_c0_brcm_cmt_int() & 3) == 2);
  420.         smp_call_function(ebi_lock_ipi, NULL, 0, 0);
  421.         while((read_c0_brcm_cmt_int() & 3) == 1);
  422. }
  423.  
  424. void ebi_unlock(void)
  425. {
  426.         int introuting;
  427.  
  428.         if (num_online_cpus() < 2)
  429.                 return;
  430.  
  431.         introuting = read_c0_brcm_cmt_int();
  432.         introuting &= ~CMT_INT_NMI_MASK;
  433.         introuting |= CMT_INT_NMI_T0;
  434.         write_c0_brcm_cmt_int(introuting);
  435.         spin_unlock(&bus_lock);
  436. }
  437.  
  438. EXPORT_SYMBOL(smp_tasklet_hi_schedule);
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