library  IEEE;
  use IEEE.STD_LOGIC_1164.ALL;
  use IEEE.STD_LOGIC_ARITH.ALL;
  use IEEE.STD_LOGIC_UNSIGNED.ALL;
  use IEEE.STD_LOGIC_TEXTIO.ALL;
  use STD.TEXTIO.ALL;

entity ram20d_tb is
	generic (
    fileIN                 : string := "ram_input.txt";
    fileOUT                : string := "ram_output.txt";
    fileCOMPARE            : string := "ram_compare.txt");
end ram20d_tb;

architecture ram20dTestbench of ram20d_tb is
file infile              : TEXT is in fileIN;
file outfile             : TEXT is out fileOUT;
file infileCompare             : TEXT is in fileIN;
file outfileCompare            : TEXT is in fileOUT;

file comparefile : TEXT is out fileCOMPARE;

component ram20d is
	port (
           clk           : in std_logic;
           we            : in std_logic;
           oe            : in std_logic;
           addr          : in std_logic_vector(5 downto 0);
           data          : inout std_logic_vector(15 downto 0));
end component;

-- ram
constant CLK_PERIOD      : time := 20 ns;
constant SIM_TIME        : time := 128 * CLK_PERIOD;
signal clk_i, we_i, oe_i : std_logic := '0';
signal addr_i            : std_logic_vector(5 downto 0) := "000000";
signal data_i            : std_logic_vector(15 downto 0) := "0000000000000000";

-- licznik
signal rst_i, ce_i       : std_logic := '0';
signal q_i               : std_logic_vector( 5 downto 0);

signal data_out          : std_logic_vector(15 downto 0) := "0000000000000000";
signal compare_e 		: std_logic := '0';

signal check_compare : std_logic := '1';

type compareFiles is (idle, compareAndSave, done);
signal compare_state : compareFiles;

begin

addrGen                  : entity work.licznik_u
generic map(N => 6, M => 64, T => 1 ns)
port map(q => q_i, rst => rst_i,  ce => ce_i, clk => clk_i);

UUT                      : ram20d
	PORT MAP(
		clk => clk_i,
		we => we_i,
		oe => oe_i,
		addr => addr_i,
		data => data_i);

clock                    : process (clk_i)
begin
	clk_i <= not clk_i after CLK_PERIOD/2;
end process;

select_address           : process(clk_i)
begin
	if(falling_edge(clk_i)) then
	if (we_i = '1' or oe_i = '1') then
		addr_i <= q_i;
		else
			addr_i <= (others => 'Z');
			end  if;
			end if;
end process;

write_data               : process(clk_i)

variable in_line         : line;
variable out_line        : line;
variable in_data        : integer := 0;

begin
		if (we_i = '1' and oe_i = '0') then
			if(falling_edge(clk_i)) then
				readline(infile, in_line);
				read(in_line, in_data);
				data_i <= conv_std_logic_vector(in_data, 16);
			end if;
		elsif (we_i = '0' and oe_i = '1') then
		if(rising_edge(clk_i)) then
			data_out <= data_i;
			write(out_line, conv_integer(data_i));
			write(out_line, HT);
			write(out_line, data_i);
			writeline(outfile, out_line);
			end if;
		else
			data_i <= (others => 'Z');
		end if;
end process;

compare : process(clk_i)
variable in_line         : line;
variable out_line        : line;
variable compare_line :line;
variable in_data        : integer := 0;
variable out_data        : integer := 0;
begin

	case compare_state is
		when idle =>
			if(compare_e = '1') then
				compare_state <= compareAndSave;
				file_close(infile);
				file_close(outfile);
				end if;
		when compareAndSave =>

			while not Endfile(infileCompare) loop

				readline(infileCompare,in_line);
				read(in_line, in_data);
				readline(outfileCompare,out_line);
				read(out_line, out_data);

				write(compare_line, in_data);
				write(compare_line, HT);
				write(compare_line, out_data);
				writeline(comparefile, compare_line);

				if(in_data /= out_data) then
					check_compare <= '0';
				end if;
			end loop;

				compare_state <= done;

		when done =>
		    assert check_compare = '1'
		      report "Comparision error: " & time'image(now)
		      severity Note ;
		    assert check_compare = '0'
		      report "Comparision OK: " & time'image(now)
		      severity Note ;
		    assert false
		      severity Failure;
	end case;

end process compare;

ce_i <= we_i or oe_i;
rst_i <= not we_i and not oe_i;
we_i <= '0', '1' after CLK_PERIOD, '0' after (64+1) * CLK_PERIOD;
oe_i <= '0', '1' after (64+1+1) * CLK_PERIOD, '0' after (128+1+1) * CLK_PERIOD;
compare_e <= '0', '1' after (128+1+1+1) * CLK_PERIOD;


end  ram20dTestbench;