tb

library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;

entity multiplier32FP_tb is
end multiplier32FP_tb;

architecture tb of multiplier32FP_tb is

    component multiplier32FP
        port(
        clk, rst_n          : in std_logic;
        start_i             : in std_logic;
        a_i, b_i            : in std_logic_vector(31 downto 0);

        product_o           : out std_logic_vector(31 downto 0);
        done_o              : out std_logic;
        nan_o, infinit_o    : out std_logic;
        overflow_o          : out std_logic;
        underflow_o         : out std_logic
        );
    end component;

    signal clk      : std_logic := '0';
    signal rst      : std_logic := '0';
    signal nan      : std_logic;
    signal infinite : std_logic;
    signal overflow : std_logic;
    signal underflow : std_logic;

    signal inputA   : std_logic_vector(31 downto 0);
    signal inputB   : std_logic_vector(31 downto 0);

    signal Start    : std_logic := '1';
    signal Done     : std_logic;
    signal output   : std_logic_vector(31 downto 0);

    type Mem is array (0 to 30) of std_logic_vector (31 downto 0);
    signal arrayA       : Mem := (x"FBAC0503",x"15049502", x"F91BA005", x"01E3714C", x"9F0CD1FF", x"01FCBEAA", x"758BAC56", x"03FBEAB4", x"938BDAC2", x"EBA10A09", x"9183FBC4", x"F17DFFB4", x"8172BAD3", x"AEB37143", x"15049502", x"15049502", x"EB3714CB", x"70C0D1F1", x"0C0D1FB6", x"C1FCBEA2", x"1F504502", x"C41FCBEA", x"FA10A094", x"DAEB3143", x"43AEB371", x"AEB37103", x"0EB3714C", x"0AEB3715", x"0AEB3711", x"F14D590F", x"FFFFFFFF");
    signal arrayB       : Mem := (x"01BA0051",x"011BA005", x"0514D590", x"1BA00501", x"A0050102", x"70C01F08", x"270C0D1F", x"77C1FCBE", x"B14D590B", x"0AEB3714", x"BEB37149", x"BEB714D5", x"3714D590", x"0E371491", x"2AEB3714", x"3F01BA00", x"A3011BA0", x"0011BA06", x"11A00501", x"BBC1FCBE", x"070C0DF8", x"B901BA00", x"01BA00D5", x"9C1FCBE0", x"01BE3714", x"EB371401", x"0114D590", x"01BA0055", x"0BEB3711", x"0B371412", x"FFFFFFFF");

    constant clk_period : time := 4.75 ns;

begin

    uut: multiplier32FP port map(
            clk         => clk,
            rst_n       => rst,
            a_i         => inputA,
            b_i         => inputB,
            product_o   => output,
            done_o      => Done,
            nan_o       => nan,
            infinit_o   => infinite,
            start_i     => Start,
        underflow_o => underflow,
        overflow_o  => overflow
        );

    clk <= not clk after clk_period/2;




    process
        variable i : integer := 0;
    begin
        inputA <= arrayA(i); --CONV_STD_LOGIC_VECTOR(6,WIDTH);
            inputB <= arrayB(i); --CONV_STD_LOGIC_VECTOR(4,WIDTH);
        wait until  clk = '1';
        rst <= '1';
        wait until  clk = '1';
        rst <= '0';
        wait until  clk = '1';

        wait until done ='1';   -- Suspend process
        i:=i+1;
    end process;

end tb;