Vybrid LPDDR2@200MHz CCM

static void clock_init(void)
{
    struct ccm_reg *ccm = (struct ccm_reg *)CCM_BASE_ADDR;
    struct anadig_reg *anadig = (struct anadig_reg *)ANADIG_BASE_ADDR;

    clrsetbits_le32(&ccm->ccgr0, CCM_REG_CTRL_MASK,
        CCM_CCGR0_DMA0_CTRL_MASK | CCM_CCGR0_DMA1_CTRL_MASK |
        CCM_CCGR0_UART0_CTRL_MASK | CCM_CCGR0_UART3_CTRL_MASK |
        CCM_CCGR0_DSPI0_CTRL_MASK);

    clrsetbits_le32(&ccm->ccgr1, CCM_REG_CTRL_MASK,
        CCM_CCGR1_PIT_CTRL_MASK | CCM_CCGR1_FTM0 |
        CCM_CCGR1_FTM1 | CCM_CCGR1_ADC0 |
        CCM_CCGR1_WDOGA5_CTRL_MASK);

    clrsetbits_le32(&ccm->ccgr2, CCM_REG_CTRL_MASK,
        CCM_CCGR2_IOMUXC_CTRL_MASK | CCM_CCGR2_PORTA_CTRL_MASK |
        CCM_CCGR2_PORTB_CTRL_MASK | CCM_CCGR2_PORTC_CTRL_MASK |
        CCM_CCGR2_PORTD_CTRL_MASK | CCM_CCGR2_PORTE_CTRL_MASK |
        CCM_CCGR2_QSPI0_CTRL_MASK);


    clrsetbits_le32(&ccm->ccgr3, CCM_REG_CTRL_MASK,
        CCM_CCGR3_ANADIG_CTRL_MASK | CCM_CCGR3_SCSC_CTRL_MASK);

    clrsetbits_le32(&ccm->ccgr4, CCM_REG_CTRL_MASK,
        CCM_CCGR4_EWM_CTRL_MASK | CCM_CCGR4_I2C0_CTRL_MASK |
        CCM_CCGR4_WKUP_CTRL_MASK |
        CCM_CCGR4_CCM_CTRL_MASK | CCM_CCGR4_GPC_CTRL_MASK);

    clrsetbits_le32(&ccm->ccgr6, CCM_REG_CTRL_MASK,
        CCM_CCGR6_DMA2_CTRL_MASK | CCM_CCGR6_DMA3_CTRL_MASK |
        CCM_CCGR6_DSPI3_CTRL_MASK |
        CCM_CCGR6_OCOTP_CTRL_MASK | CCM_CCGR6_DDRMC_CTRL_MASK);

    clrsetbits_le32(&ccm->ccgr7, CCM_REG_CTRL_MASK,
        CCM_CCGR7_ADC1_CTRL_MASK);

    clrsetbits_le32(&ccm->ccgr10, CCM_REG_CTRL_MASK,
        CCM_CCGR10_NFC_CTRL_MASK);

    clrsetbits_le32(&anadig->pll2_ctrl, ANADIG_PLL2_CTRL_POWERDOWN,
        ANADIG_PLL2_CTRL_ENABLE | ANADIG_PLL2_CTRL_DIV_SELECT);
    clrsetbits_le32(&anadig->pll1_ctrl, ANADIG_PLL1_CTRL_POWERDOWN,
        ANADIG_PLL1_CTRL_ENABLE | ANADIG_PLL1_CTRL_DIV_SELECT);

    clrsetbits_le32(&ccm->ccr, CCM_CCR_OSCNT_MASK,
        CCM_CCR_FIRC_EN | CCM_CCR_OSCNT(5));
    clrsetbits_le32(&ccm->ccsr, CCM_REG_CTRL_MASK,
        CCM_CCSR_PLL1_PFD_CLK_SEL(3) | CCM_CCSR_PLL2_PFD4_EN |
        CCM_CCSR_PLL2_PFD3_EN | CCM_CCSR_PLL2_PFD2_EN |
        CCM_CCSR_PLL2_PFD1_EN | CCM_CCSR_PLL1_PFD4_EN |
        CCM_CCSR_PLL1_PFD3_EN | CCM_CCSR_PLL1_PFD2_EN |
        CCM_CCSR_PLL1_PFD1_EN | CCM_CCSR_DDRC_CLK_SEL(1) |
        CCM_CCSR_FAST_CLK_SEL(1) | CCM_CCSR_SYS_CLK_SEL(4));
    clrsetbits_le32(&ccm->cacrr, CCM_REG_CTRL_MASK,
        CCM_CACRR_IPG_CLK_DIV(1) | CCM_CACRR_BUS_CLK_DIV(2) |

        CCM_CACRR_ARM_CLK_DIV(1));




    clrsetbits_le32(&ccm->cscmr1, CCM_REG_CTRL_MASK,
        CCM_CSCMR1_ESDHC1_CLK_SEL(3) | CCM_CSCMR1_QSPI0_CLK_SEL(3) |
        CCM_CSCMR1_NFC_CLK_SEL(0));
    clrsetbits_le32(&ccm->cscdr2, CCM_REG_CTRL_MASK,
        CCM_CSCDR2_ESDHC1_EN | CCM_CSCDR2_ESDHC1_CLK_DIV(0) |
        CCM_CSCDR2_NFC_EN);
    clrsetbits_le32(&ccm->cscdr3, CCM_REG_CTRL_MASK,
        CCM_CSCDR3_QSPI0_EN | CCM_CSCDR3_QSPI0_DIV(1) |
        CCM_CSCDR3_QSPI0_X2_DIV(1) | CCM_CSCDR3_QSPI0_X4_DIV(3) |
        CCM_CSCDR3_NFC_PRE_DIV(5));
}