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  1. /*
  2.  *
  3.  *  BlueZ - Bluetooth protocol stack for Linux
  4.  *
  5.  *  Copyright (C) 2010-2011  RDA Micro <anli@rdamicro.com>
  6.  *  This file belong to RDA micro
  7.  *
  8.  *  This program is free software; you can redistribute it and/or modify
  9.  *  it under the terms of the GNU General Public License as published by
  10.  *  the Free Software Foundation; either version 2 of the License, or
  11.  *  (at your option) any later version.
  12.  *
  13.  *  This program is distributed in the hope that it will be useful,
  14.  *  but WITHOUT ANY WARRANTY; without even the implied warranty of
  15.  *  MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  16.  *  GNU General Public License for more details.
  17.  *
  18.  *  You should have received a copy of the GNU General Public License
  19.  *  along with this program; if not, write to the Free Software
  20.  *  Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA  02110-1301  USA
  21.  *
  22.  */
  23.  
  24. #ifdef HAVE_CONFIG_H
  25. #include <config.h>
  26. #endif
  27.  
  28. #include <errno.h>
  29. #include <fcntl.h>
  30. #include <sys/ioctl.h>
  31. #include <sys/socket.h>
  32. #include <sys/types.h>
  33. #include <sys/stat.h>
  34.  
  35. #define TCC_BT_DEVICE_PATH          "/dev/tcc_bt_dev"
  36. #define BT_DEV_MAJOR_NUM            234
  37. #define IOCTL_BT_DEV_POWER      _IO(BT_DEV_MAJOR_NUM, 100)
  38. #define IOCTL_BT_DEV_CTRL   _IO(BT_DEV_MAJOR_NUM, 102)
  39.  
  40. //#define __RDA_CHIP_R10_5870E__   //ʹÓÃRDA5870E
  41. //#define __RDA_CHIP_R11_5875__      //ʹÓÃRDA5875
  42. #define __RDA_CHIP_R11_5876__    //ʹÓÃRDA5875Y,RDA5876
  43. #define EXTERNAL_32K               //ÈôÍⲿÊäÈë32KʱÖÓµ½PIN#10£¬¿ª´Ëºê.
  44.  
  45.  
  46. /*´Ëº¯ÊýʵÏÖÀ­¸ßLDO_DON,²¢ÑÓʱ50ms*/
  47. void RDA_pin_to_high(int fd)
  48. {
  49. #if 0
  50.    RDA_BT_POWER_ON;//open LDO_ON
  51.    usleep(5000);
  52.    GPIO_SetBtReset(SCI_TRUE);//open reset  
  53.    usleep(20000);
  54. #endif
  55.     int bt_on_off = 1;
  56.     ioctl(fd, IOCTL_BT_DEV_CTRL, &bt_on_off);      
  57. }
  58. /*´Ëº¯ÊýʵÏÖÀ­µÍLDO_DON,²¢ÑÓʱ50ms*/
  59. void RDA_pin_to_low(int fd)
  60. {
  61. #if 0
  62.    RDA_BT_POWER_OFF;//shut down LDO_ON
  63.    usleep(5000);
  64.    GPIO_SetBtReset(SCI_FALSE);//shut down reset  
  65.    usleep(20000);
  66. #endif
  67.     int bt_on_off = 0;
  68.     ioctl(fd, IOCTL_BT_DEV_CTRL, &bt_on_off);      
  69. }
  70.  
  71. void rdabt_write_memory(int fd,__u32 addr,__u32 *data,__u8 len,__u8 memory_type)
  72. {
  73.    __u16 num_to_send;  
  74.    __u16 i,j;
  75.    __u8 data_to_send[256]={0};
  76.    __u32 address_convert;
  77.    
  78.    data_to_send[0] = 0x01;
  79.    data_to_send[1] = 0x02;
  80.    data_to_send[2] = 0xfd;
  81.    data_to_send[3] = (__u8)(len*4+6);
  82.    data_to_send[4] = (memory_type/*+0x80*/);  // add the event display
  83.    data_to_send[5] = len;
  84.    if(memory_type == 0x01)
  85.    {
  86.       address_convert = addr*4+0x200;
  87.       data_to_send[6] = (__u8)address_convert;
  88.       data_to_send[7] = (__u8)(address_convert>>8);
  89.       data_to_send[8] = (__u8)(address_convert>>16);
  90.       data_to_send[9] = (__u8)(address_convert>>24);     
  91.    }
  92.    else
  93.    {
  94.       data_to_send[6] = (__u8)addr;
  95.       data_to_send[7] = (__u8)(addr>>8);
  96.       data_to_send[8] = (__u8)(addr>>16);
  97.       data_to_send[9] = (__u8)(addr>>24);
  98.    }
  99.    for(i=0;i<len;i++,data++)
  100.    {
  101.        j=10+i*4;
  102.        data_to_send[j] =  (__u8)(*data);
  103.        data_to_send[j+1] = (__u8)((*data)>>8);
  104.        data_to_send[j+2] = (__u8)((*data)>>16);
  105.        data_to_send[j+3] = (__u8)((*data)>>24);
  106.    }
  107.    num_to_send = 4+data_to_send[3];
  108.  
  109.    write(fd,&(data_to_send[0]),num_to_send);
  110.    
  111. }
  112.  
  113.  
  114.  
  115. void RDA_uart_write_simple(int fd,__u8* buf,__u16 len)
  116. {
  117.     __u16 num_send;
  118.     write(fd,buf,len);
  119.     usleep(10000);//10ms?
  120. }
  121.  
  122. void RDA_uart_write_array(int fd,__u32 buf[][2],__u16 len,__u8 type)
  123. {
  124.    __u32 i;
  125.    for(i=0;i<len;i++)
  126.    {
  127.       rdabt_write_memory(fd,buf[i][0],&buf[i][1],1,type);
  128.       usleep(12000);//12ms?
  129.    }   
  130. }
  131.  
  132. #ifdef __RDA_CHIP_R11_5876__
  133. __u32 rdabt_rf_init_12[][2] =
  134. {  
  135. {0x0000003f,0x00000000},//
  136. {0x00000001,0x00001FFF},//                                                              
  137. {0x00000006,0x000007F7},//padrv_set,increase the power.                                  
  138. {0x00000008,0x000001E7},//                                                              
  139. {0x00000009,0x00000520},//                                                              
  140. {0x0000000B,0x000003DF},//filter_cap_tuning<3:0>1101                                    
  141. {0x0000000C,0x000085E8},//                                                              
  142. {0x0000000F,0x00000DBC},// 0FH,16'h1D8C; 0FH,16'h1DBC;adc_clk_sel=1 20110314 ;adc_digi_pw
  143. {0x00000012,0x000007F7},//padrv_set,increase the power.                                  
  144. {0x00000013,0x00000327},//agpio down pullen .                                            
  145. {0x00000014,0x00000CCC},//h0CFE; bbdac_cm 00=vdd/2.                                      
  146. {0x00000015,0x00000526},//Pll_bypass_ontch:1,improve ACPR.                              
  147. {0x00000016,0x00008918},//add div24 20101126                                            
  148. {0x00000018,0x00008800},//add div24 20101231                                            
  149. {0x00000019,0x000010C8},//pll_adcclk_en=1 20101126                                      
  150. {0x0000001A,0x00009128},//Mdll_adcclk_out_en=0                                          
  151. {0x0000001B,0x000080C0},//1BH,16'h80C2                                                  
  152. {0x0000001C,0x00003613},//                                                              
  153. {0x0000001D,0x000013E3},//Pll_cp_bit_tx<3:0>1110;13D3                                    
  154. {0x0000001E,0x0000300C},//Pll_lpf_gain_tx<1:0> 00;304C                                  
  155. {0x00000023,0x00002222},//                                                              
  156. {0x00000024,0x0000359F},//                                                              
  157. {0x00000027,0x00000011},//                                                              
  158. {0x00000028,0x0000124F},//                                                              
  159. {0x00000039,0x0000A5FC},//      
  160. {0x0000003f,0x00000001},//                                                        
  161. {0x00000000,0x0000043F},//agc                                                            
  162. {0x00000001,0x0000467F},//agc                                                            
  163. {0x00000002,0x000028FF},//agc//2011032382H,16'h68FF;agc                                  
  164. {0x00000003,0x000067FF},//agc                                                            
  165. {0x00000004,0x000057FF},//agc                                                            
  166. {0x00000005,0x00007BFF},//agc                                                            
  167. {0x00000006,0x00003FFF},//agc                                                            
  168. {0x00000007,0x00007FFF},//agc                                                            
  169. {0x00000018,0x0000F3F5},//                                                              
  170. {0x00000019,0x0000F3F5},//                                                              
  171. {0x0000001A,0x0000E7F3},//                                                              
  172. {0x0000001B,0x0000F1FF},//                                                              
  173. {0x0000001C,0x0000FFFF},//                                                              
  174. {0x0000001D,0x0000FFFF},//                                                              
  175. {0x0000001E,0x0000FFFF},//                                                              
  176. {0x0000001F,0x0000FFFF},//padrv_gain;9FH,16'hFFEC;padrv_gain20101103;improve ACPR;      
  177. #ifdef EXTERNAL_32K
  178.         {0x00000023,0x00004224},//;ext32k
  179. #endif
  180. {0x00000025,0x000043E1},//ldo_vbit:110,1.96v                                            
  181. {0x00000026,0x00004BB5},//reg_ibit:101,reg_vbit:110,1.12v,reg_vbit_deepsleep:110,750mV  
  182. {0x00000032,0x00000079},//TM mod                                                        
  183. {0x0000003f,0x00000000},//
  184. };
  185.  
  186. __u32 RDA5876_ENABLE_SPI[][2] =
  187. {
  188.     {0x40240000,0x0004f39c},                              
  189. };
  190.  
  191. __u32 RDA5876_DISABLE_SPI[][2] =
  192. {
  193.     {0x40240000,0x0000f29c},
  194. };
  195.  
  196. __u32 RDA5876_PSKEY_RF[][2] =
  197. {
  198. {0x40240000,0x0004f39c},
  199. {0x800000C0,0x00000020},
  200. {0x800000C4,0x003F0000},
  201. {0x800000C8,0x00414003},
  202. {0x800000CC,0x004225BD},
  203. {0x800000D0,0x004908E4},
  204. {0x800000D4,0x0043B074},
  205. {0x800000D8,0x0044D01A},
  206. {0x800000DC,0x004A0800},
  207. {0x800000E0,0x0054A020},
  208. {0x800000E4,0x0055A020},
  209. {0x800000E8,0x0056A542},
  210. {0x800000EC,0x00574C18},
  211. {0x800000F0,0x003F0001},
  212. {0x800000F4,0x00410900},
  213. {0x800000F8,0x0046033F},
  214. {0x800000FC,0x004C0000},
  215. {0x80000100,0x004D0015},
  216. {0x80000104,0x004E002B},
  217. {0x80000108,0x004F0042},
  218. {0x8000010C,0x0050005A},
  219. {0x80000110,0x00510073},
  220. {0x80000114,0x0052008D},
  221. {0x80000118,0x005300A7},
  222. {0x8000011C,0x005400C4},
  223. {0x80000120,0x005500E3},
  224. {0x80000124,0x00560103},
  225. {0x80000128,0x00570127},
  226. {0x8000012C,0x0058014E},
  227. {0x80000130,0x00590178},
  228. {0x80000134,0x005A01A1},
  229. {0x80000138,0x005B01CE},
  230. {0x8000013C,0x005C01FF},
  231. {0x80000140,0x003F0000},
  232. {0x80000040,0x10000000},
  233. };
  234.  
  235. __u32 RDA5876_DCCAL[][2]=
  236. {
  237.     {0x0000003f,0x00000000},
  238. {0x00000030,0x00000129},
  239. {0x00000030,0x0000012B},
  240. };
  241.  
  242. __u32 RDA5876_PSKEY_MISC[][2] =
  243. {
  244.     {0x800004ec,0x788dffff}, ///disable edr
  245.     {0x800004f0,0x83713f98}, ///disable 3m esco ev4 ev5
  246.    
  247.   {0x80000070,0x00006058},  //6050
  248. #ifdef EXTERNAL_32K
  249.     {0x80000074,0xa5025010},
  250. #else
  251.     {0x80000074,0x05025010},//0x05025010 for no sleep ; 0xa5025010 for sleep
  252. #endif
  253. //  {0x80000084,0x9098C007},
  254.     {0x80000084,0xb4b8C007},
  255.     {0x800000a0,0x00000000},
  256. #ifdef EXTERNAL_32K
  257.     {0x800000a4,0x08a0280a},
  258. #else
  259.     {0x800000a4,0x00000000},
  260.  
  261. #endif
  262.     {0x800000a8,0x0bbfbf30},//min power level
  263.     {0x80000040,0x07023000},//PSKEY: modify flag
  264. };
  265.  
  266. __u32 RDA5876_TRAP[][2] =
  267. {
  268.   {0x40180100,0x000068b8},//inc power
  269.     {0x40180120,0x000069f4},
  270.    
  271.     {0x40180104,0x000066b8},//dec power
  272.     {0x40180124,0x000069f4},
  273.  
  274.    
  275.     {0x40180108,0x0001544c},//esco w
  276.     {0x40180128,0x0001568c},
  277.    
  278.     {0x80000100,0xe3a0704f}, ///2ev3 ev3 hv3
  279.     {0x4018010c,0x0000bae8},//esco packet
  280.     {0x4018012c,0x80000100},
  281.  
  282.  
  283.     {0x40180110,0x000247a0},//sleep patch
  284.     {0x40180130,0x0002475c},
  285.   {0x40180114,0x0000f8c4},///all rxon
  286.   {0x40180134,0x00026948},
  287.  
  288.   {0x40180118,0x000130b8},///qos PRH_CHN_QUALITY_MIN_NUM_PACKETS
  289.   {0x40180138,0x0001cbb4},
  290.  
  291.  
  292.   {0x4018011c,0x0000bac8},
  293.   {0x4018013c,0x0000bae4},
  294.  
  295.     {0x40180000,0x0000ff00},  
  296. };
  297.  
  298.  
  299. void RDA5876_RfInit(int fd)
  300. {
  301.     RDA_uart_write_array(fd,RDA5876_ENABLE_SPI,sizeof(RDA5876_ENABLE_SPI)/sizeof(RDA5876_ENABLE_SPI[0]),0);
  302.     RDA_uart_write_array(fd,rdabt_rf_init_12,sizeof(rdabt_rf_init_12)/sizeof(rdabt_rf_init_12[0]),1);
  303.     usleep(50000);//50ms?
  304. }
  305.  
  306. void RDA5876_Pskey_RfInit(int fd)
  307. {
  308.     RDA_uart_write_array(fd,RDA5876_PSKEY_RF,sizeof(RDA5876_PSKEY_RF)/sizeof(RDA5876_PSKEY_RF[0]),0);
  309. }
  310.  
  311. void RDA5876_Dccal(int fd)
  312. {
  313.     RDA_uart_write_array(fd,RDA5876_DCCAL,sizeof(RDA5876_DCCAL)/sizeof(RDA5876_DCCAL[0]),1);
  314.     RDA_uart_write_array(fd,RDA5876_DISABLE_SPI,sizeof(RDA5876_DISABLE_SPI)/sizeof(RDA5876_DISABLE_SPI[0]),0);
  315. }
  316.  
  317. void RDA5876_Pskey_Misc(int fd)
  318. {
  319.     RDA_uart_write_array(fd,RDA5876_PSKEY_MISC,sizeof(RDA5876_PSKEY_MISC)/sizeof(RDA5876_PSKEY_MISC[0]),0);
  320. }
  321.  
  322. void RDA5876_Trap(int fd)
  323. {
  324.     RDA_uart_write_array(fd,RDA5876_TRAP,sizeof(RDA5876_TRAP)/sizeof(RDA5876_TRAP[0]),0);
  325. }
  326.  
  327.  
  328. #if 0
  329. void RDA5876_DUT_Test(int fd)
  330. {
  331.     RDA_uart_write_array(fd,RDA5876_DUT,sizeof(RDA5876_DUT)/sizeof(RDA5876_DUT[0]),0);
  332. }
  333. #endif
  334.  
  335. #endif
  336.  
  337. #ifdef __RDA_CHIP_R11_5875__
  338.  
  339.  
  340. __u32 RDA5872P_5400_PSKEY[][2] =
  341. {  
  342.     {0x0000003f,0x00000000},
  343.     {0x00000001,0x00001FFF},//;
  344.     {0x00000006,0x000007F4},//;padrv_set,increase the power.
  345.     {0x00000008,0x000001E7},//;
  346.     {0x00000009,0x00000520},//;
  347.     {0x0000000B,0x000003DF},//;filter_cap_tuning<3:0>1101
  348.     {0x0000000C,0x000085e8},//;
  349.     {0x0000000F,0x00001dCC},//;
  350.     {0x00000012,0x000007F4},//;padrv_set,increase the power.
  351.     {0x00000013,0x00000327},//;padrv_set,increase the power.
  352.     {0x00000014,0x00000CFE},//;
  353.     {0x00000015,0x00000526},//;Pll_bypass_ontch:1,improve ACPR.
  354.     {0x00000016,0x00008918},//;Pll_bypass_ontch:1,improve ACPR.
  355.     {0x00000018,0x00008800},//;Pll_bypass_ontch:1,improve ACPR.
  356.     {0x00000019,0x000010c8},//;Pll_bypass_ontch:1,improve ACPR.
  357.     {0x0000001B,0x000080c2},//;
  358.     {0x0000001C,0x00003613},//;
  359.     {0x0000001D,0x000013E3},//;Pll_cp_bit_tx<3:0>1110;13D3
  360.     {0x0000001E,0x0000300C},//;Pll_lpf_gain_tx<1:0> 00;304C
  361.     {0x00000023,0x00003335},//;Pll_bypass_ontch:1,improve ACPR.
  362.     {0x00000024,0x00008aaf},//;
  363.     {0x00000027,0x00001112},//;Pll_bypass_ontch:1,improve ACPR.
  364.     {0x00000028,0x0000345f},//;Pll_bypass_ontch:1,improve ACPR.
  365.     {0x0000003f,0x00000001},
  366.     {0x00000000,0x0000043F},//;agc
  367.     {0x00000001,0x0000467F},//;agc
  368.     {0x00000002,0x000068FF},//;agc
  369.     {0x00000003,0x000067FF},//;agc
  370.     {0x00000004,0x000057FF},//;agc
  371.     {0x00000005,0x00007BFF},//;agc
  372.     {0x00000006,0x00003FFF},//;agc
  373.     {0x00000007,0x00007FFF},//;agc
  374.     {0x00000018,0x0000b1B1}, //; 98H,16'hB1B1;                                                            
  375.     {0x00000019,0x0000b1b1}, //; 99H,16'hB1B1;                                                            
  376.     {0x0000001a,0x0000b1b1}, //; 9AH,16'hB1B1;                                                            
  377.     {0x0000001b,0x0000b0b0}, //; 9BH,16'hB0B0;                                                            
  378.     {0x0000001c,0x0000d7b0}, //; 9CH,16'hD7B0;                                                            
  379.     {0x0000001d,0x0000e4e0}, //; 9DH,16'hE4E0;                                                            
  380.     {0x0000001e,0x0000e7e9}, //; 9EH,16'hE7E9;                                                            
  381.     {0x0000001F,0x0000e9E9},//;padrv_gain
  382. #ifdef EXTERNAL_32K
  383.     {0x00000023,0x00004224},//;ext32k
  384. #endif
  385. #ifdef RDA5875_USE_DCDC
  386.     {0x00000024,0x00009b10},
  387. #else
  388.     {0x00000024,0x00000110},
  389. #endif
  390.     {0x00000025,0x000043A0},//;ldo_vbit:110,2.04v
  391.     {0x00000026,0x000049B5},//;reg_ibit:100,reg_vbit:110,1.1v,reg_vbit_deepsleep:110,750mV
  392.     {0x00000032,0x00000059},//;TM mod
  393.     {0x0000003f,0x00000000}
  394. };
  395.  
  396. __u32 RDA5872P_ENABLE_SPI[][2] =
  397. {
  398.     {0x40240000,0x0004f39c},                              
  399. };
  400.  
  401. __u32 RDA5872P_DISABLE_SPI[][2] =
  402. {
  403.     {0x40240000,0x0000f29c},
  404. };
  405.  
  406. __u32 RDA5872P_PSKEY_RF[][2] =
  407. {
  408.     {0x40240000,0x0004f39c}, //; SPI2_CLK_EN PCLK_SPI2_EN
  409.     {0x800000C0,0x00000020}, //; CHIP_PS PSKEY: Total number -----------------
  410.     {0x800000C4,0x003F0000}, //;         PSKEY: Page 0
  411.     {0x800000C8,0x00410003}, //;         PSKEY: Swch_clk_ADC
  412.     {0x800000CC,0x004225BD}, //;         PSKEY: dig IF 625K IF  by lihua20101231
  413.     {0x800000D0,0x004908E4}, //;         PSKEY: freq_offset_for rateconv  by lihua20101231(replace 47H)
  414.     {0x800000D4,0x0043B074}, //;         PSKEY: AM dac gain, 20100605
  415.     {0x800000D8,0x0044D01A}, //;         PSKEY: gfsk dac gain, 20100605//22
  416.     {0x800000DC,0x004A0800}, //;         PSKEY: 4AH=0800
  417.     {0x800000E0,0x0054A020}, //;         PSKEY: 54H=A020;agc_th_max=A0;agc_th_min=20
  418.     {0x800000E4,0x0055A020}, //;         PSKEY: 55H=A020;agc_th_max_lg=A0;agc_th_min_lg=20
  419.     {0x800000E8,0x0056A542}, //;         PSKEY: 56H=A542
  420.     {0x800000EC,0x00574C18}, //;         PSKEY: 57H=4C18
  421.     {0x800000F0,0x003F0001}, //;         PSKEY: Page 1              
  422.     {0x800000F4,0x00410900}, //;         PSKEY: C1=0900;Phase Delay, 20101029
  423.     {0x800000F8,0x0046033F}, //;         PSKEY: C6=033F;modulation Index;delta f2=160KHZ,delta f1=164khz
  424.     {0x800000FC,0x004C0000}, //;         PSKEY: CC=0000;20101108  
  425.     {0x80000100,0x004D0015}, //;         PSKEY: CD=0015;          
  426.     {0x80000104,0x004E002B}, //;         PSKEY: CE=002B;          
  427.     {0x80000108,0x004F0042}, //;         PSKEY: CF=0042            
  428.     {0x8000010C,0x0050005A}, //;         PSKEY: D0=005A            
  429.     {0x80000110,0x00510073}, //;         PSKEY: D1=0073            
  430.     {0x80000114,0x0052008D}, //;         PSKEY: D2=008D            
  431.     {0x80000118,0x005300A7}, //;         PSKEY: D3=00A7            
  432.     {0x8000011C,0x005400C4}, //;         PSKEY: D4=00C4            
  433.     {0x80000120,0x005500E3}, //;         PSKEY: D5=00E3            
  434.     {0x80000124,0x00560103}, //;         PSKEY: D6=0103            
  435.     {0x80000128,0x00570127}, //;         PSKEY: D7=0127            
  436.     {0x8000012C,0x0058014E}, //;         PSKEY: D8=014E            
  437.     {0x80000130,0x00590178}, //;         PSKEY: D9=0178            
  438.     {0x80000134,0x005A01A1}, //;         PSKEY: DA=01A1            
  439.     {0x80000138,0x005B01CE}, //;         PSKEY: DB=01CE            
  440.     {0x8000013C,0x005C01FF}, //;         PSKEY: DC=01FF            
  441.     {0x80000140,0x003F0000}, //;         PSKEY: Page 0
  442.     {0x80000040,0x10000000}, //;         PSKEY: Flage
  443.     //{0x40240000,0x0000f29c}, //; SPI2_CLK_EN PCLK_SPI2_EN
  444. };
  445.  
  446. __u32 RDA5872P_DCCAL[][2]=
  447. {
  448.     {0x00000030,0x00000129},
  449.     {0x00000030,0x0000012b}
  450. };
  451.  
  452. __u32 RDA5872P_PSKEY_MISC[][2] =
  453. {
  454.     {0x80000070,0x00006058},
  455. #ifdef EXTERNAL_32K
  456.     {0x80000074,0xa5025010},
  457. #else
  458.     {0x80000074,0x05025010},//0x05025010 for no sleep ; 0xa5025010 for sleep
  459. #endif
  460.     {0x80000084,0x9098C007},
  461.     {0x800000a0,0x00000000},
  462.     {0x800000a4,0x00000000},
  463.     {0x800000a8,0x0bbfbf30},//min power level
  464.     {0x80000040,0x07023000},//PSKEY: modify flag
  465.     {0x800004ec,0x788dffff}, ///disable edr
  466. };
  467.  
  468. __u32 RDA5872P_TRAP[][2] =
  469. {
  470.     {0x800004ec,0x788dFFFF},//shut down edr
  471.  
  472.     {0x40180100,0x00013158},//:    e3a00064    d...    MOV      r0,#0x64
  473.     {0x40180120,0x00027e68},
  474.     {0x40180104,0x00013240},//:    e3a00064    d...    MOV      r0,#0x64
  475.     {0x40180124,0x00027e68},
  476.  
  477.     {0x40180108,0x0002ED2C},
  478.     {0x40180128,0x000309E4},
  479.     {0x80008ba8,0xe3a01007},
  480.     {0x4018010c,0x0001cec8},
  481.     {0x4018012c,0x80008ba8},
  482.     {0x40180110,0x00002A98},
  483.     {0x40180130,0x00003074},
  484.     {0x40180114,0x00012040},
  485.     {0x40180134,0x00021D40},
  486.  
  487. #ifndef EXTERNAL_32K
  488.        {0x40180118,0x0002475c},// for no 32K
  489.     {0x40180138,0x00024718},// for no 32K
  490. #endif
  491.  
  492.     {0X40180000,0x00003f00},
  493. };
  494.  
  495.  
  496.  
  497. void RDA5872P_RfInit(int fd)
  498. {
  499.     RDA_uart_write_array(fd,RDA5872P_ENABLE_SPI,sizeof(RDA5872P_ENABLE_SPI)/sizeof(RDA5872P_ENABLE_SPI[0]),0);
  500.     RDA_uart_write_array(fd,RDA5872P_5400_PSKEY,sizeof(RDA5872P_5400_PSKEY)/sizeof(RDA5872P_5400_PSKEY[0]),1);
  501.     usleep(50000);//50ms?
  502. }
  503.  
  504. void RDA5872P_Pskey_RfInit(int fd)
  505. {
  506.     RDA_uart_write_array(fd,RDA5872P_PSKEY_RF,sizeof(RDA5872P_PSKEY_RF)/sizeof(RDA5872P_PSKEY_RF[0]),0);
  507. }
  508.  
  509. void RDA5872P_Dccal(int fd)
  510. {
  511.     RDA_uart_write_array(fd,RDA5872P_DCCAL,sizeof(RDA5872P_DCCAL)/sizeof(RDA5872P_DCCAL[0]),1);
  512.     RDA_uart_write_array(fd,RDA5872P_DISABLE_SPI,sizeof(RDA5872P_DISABLE_SPI)/sizeof(RDA5872P_DISABLE_SPI[0]),0);
  513. }
  514.  
  515. void RDA5872P_Pskey_Misc(int fd)
  516. {
  517.     RDA_uart_write_array(fd,RDA5872P_PSKEY_MISC,sizeof(RDA5872P_PSKEY_MISC)/sizeof(RDA5872P_PSKEY_MISC[0]),0);
  518. }
  519.  
  520. void RDA5872P_Trap(int fd)
  521. {
  522.     RDA_uart_write_array(fd,RDA5872P_TRAP,sizeof(RDA5872P_TRAP)/sizeof(RDA5872P_TRAP[0]),0);
  523. }
  524. #endif
  525.  
  526. #ifdef __RDA_CHIP_R10_5870E__
  527. __u32 rda5870e_set_tm[][2] =
  528. {      
  529.     {0x0000003f,0x00000001},//page 1    
  530.     {0x00000032,0x0000000b},//;TM mod B2H [2:0]  
  531.     {0x0000003f,0x00000000},//page 0
  532. };
  533.  
  534. __u32 rdabt_rf_init_10_e[][2] =
  535. {  
  536.     {0x0000003f,0x00000000},//page 0
  537.     {0x00000001,0x00000FFF},//;Padrv_gain_tb_en
  538.     {0x00000006,0x000003FF},//;PSK
  539.     {0x00000008,0x000000FF},//;
  540.     {0x00000009,0x0000046C},//;
  541.     {0x0000000B,0x0000021F},//;
  542.     {0x0000000C,0x000085D8},//;
  543.     {0x0000000F,0x00001CC8},//;adc_refi_cal_reg<2:0> Set to 000,20100820.
  544.     {0x00000012,0x00000107},//;GFSK
  545.     {0x0000001B,0x0000E224},//;
  546.     {0x0000001C,0x0000F5F3},//;Xtal_capbank,20100820
  547.     {0x0000001D,0x000021BB},//;5870E EVM,20100827.
  548.     {0x00000021,0x00000000},//;Gain_psk_hi4_PSK_4>5>6>7
  549.     {0x00000022,0x00000000},//;Gain_psk_hi4_PSK_4>5>6>7
  550.     {0x00000023,0x00002458},//;Gain_psk_hi4_PSK_8>9>A>B
  551.     {0x00000024,0x00008ddd},//;Gain_psk_hi4_PSK_C>D>E>F
  552.     {0x00000025,0x00000000},//;Gain_fsk_hi4 GFSK 0>1>2>3
  553.     {0x00000026,0x00000000},//;Gain_fsk_hi4 GFSK 4>5>6>7
  554.     {0x00000027,0x00001235},//;Gain_fsk_hi4 GFSK 8>9>A>B
  555.     {0x00000028,0x00005888},//;Gain_fsk_hi4 GFSK C>D>E>F
  556.     {0x0000003f,0x00000001},//page 1
  557.     {0x00000000,0x00004005},//;;agc0
  558.     {0x00000001,0x00004025},//;;agc1
  559.     {0x00000002,0x00005025},//;;agc2
  560.     {0x00000003,0x0000506D},//;;agc3
  561.     {0x00000004,0x000050bD},//;;agc4
  562.     {0x00000005,0x0000713D},//;;agc5
  563.     {0x00000006,0x00007A3D},//;;agc6
  564.     {0x00000007,0x00007E3E},//;;agc7
  565.     {0x0000000A,0x0000001F},//;
  566.     {0x0000000D,0x00000017},//;APC
  567.     {0x00000011,0x00000000},//;;padrv_gain_1
  568.     {0x00000012,0x00000000},//;;padrv_gain_2
  569.     {0x00000013,0x00000000},//;;padrv_gain_3
  570.     {0x00000014,0x00000000},//;;padrv_gain_4
  571.     {0x00000015,0x00000000},//;;padrv_gain_5
  572.     {0x00000016,0x00000000},//;;padrv_gain_6
  573.     {0x00000017,0x00000000},//;;padrv_gain_7
  574.     {0x00000018,0x00000000},//;;padrv_gain_8
  575.     {0x00000019,0x00000000},//;;padrv_gain_9
  576.     {0x0000001A,0x00001818},//;;padrv_gain_A
  577.     {0x0000001B,0x00001818},//;;padrv_gain_B
  578.     {0x0000001C,0x00006e6e},//;;padrv_gain_C
  579.     {0x0000001D,0x00006e6e},//;;padrv_gain_D
  580.     {0x0000001E,0x0000a7a7},//;;padrv_gain_E
  581.     //{0x1F,0xb5b5},//;;padrv_gain_F
  582.     {0x0000001F,0x0000d8d8},//;;padrv_gain_F gfsk 4dBm,psk 2.4dBm
  583.     //{0x1F,0xdddd},//;;padrv_gain_F gfsk 5dBm,psk 3dBm
  584.     //{0x1F,0xe4e4},//;;padrv_gain_F gfsk 6dBm,psk 4.1dBm
  585.     //{0x1F,0xecec},//;;padrv_gain_F gfsk 7dBm,psk 5.2dBm (max power)
  586.     {0x00000023,0x00004221},//;;use EXT32k
  587. #ifdef __587x_USE_DCDC__
  588.     {0x00000024,0x000048d1},//dcdc_enable set to 1
  589.     {0x00000026,0x000045f5},//lower regulator voltage, current goes from DCDC
  590. #else
  591.     {0x00000024,0x00000090},//dcdc_enable set to 1
  592.     {0x00000026,0x00004535},//;;1,reg_vbit_normal<2:0>Set to 010£»2£¬reg_vbit_deepsleep<2:0> Set to 111¡£
  593. #endif
  594.     {0x0000002F,0x0000114E},//;;
  595.     {0x0000003f,0x00000000},//page 0
  596. };
  597.  
  598. __u32 rdabt_pskey_rf_10_e[][2] =
  599. {
  600. #if 1
  601. //rf para setting
  602. {0x40240000,0x0004F39c},//enable spi2
  603. {0x800000C0,0x0000000f},//PSKEY: Total number
  604. {0x800000C4,0x003F0000},//PSKEY: page0
  605. {0x800000C8,0x00410003},//PSKEY: Swch_clk_adc
  606. {0x800000CC,0x004224EC},//PSKEY: 625k if
  607. {0x800000D0,0x0047C939},//PSKEY: mod_adc_clk
  608. {0x800000D4,0x00431a74},//PSKEY: AM dac gain
  609. {0x800000D8,0x0044d01A},//PSKEY: gfsk dac gain
  610. {0x800000DC,0x004a0800},//PSKEY: 4A=0800
  611. {0x800000E0,0x0054a020},//PSKEY: 54=A020 AGCMAX=A0 AGCMIN=20
  612. {0x800000E4,0x0055a020},//PSKEY: 55=A020 AGC_TH_max_lg=a0 agc_th_min_lg =0x20
  613. {0x800000E8,0x0056a542},//PSKEY: 56=a542
  614. {0x800000EC,0x00574c18},//PSKEY: 57=4c18
  615. {0x800000F0,0x003f0001},//PSKEY: page=1
  616. {0x800000F4,0x00410c80},//PSKEY: phase delay
  617. {0x800000F8,0x003f0000},//PSKEY: page =0
  618. {0x800000Fc,0x00000000},//PSKEY: page =0
  619. {0x80000040,0x10000000},//PSKEY: flag
  620. {0x40240000,0x0000F29c},//enable spi2
  621.  
  622. #else
  623. //rf para setting
  624. {0x40240000,0x0004F39c},//enable spi2
  625. {0x800000C0,0x00000014},//PSKEY: Total number
  626. {0x800000C4,0x003F0000},//PSKEY: page0
  627. {0x800000C8,0x00410003},//PSKEY: Swch_clk_adc
  628. {0x800000CC,0x004224EC},//PSKEY: 625k if
  629. {0x800000D0,0x0047C939},//PSKEY: mod_adc_clk
  630. {0x800000D4,0x00431a74},//PSKEY: AM dac gain
  631. {0x800000D8,0x0044d01A},//PSKEY: gfsk dac gain
  632. {0x800000DC,0x004a0800},//PSKEY: 4A=0800
  633. {0x800000E0,0x004d008a},
  634. {0x800000E4,0x004e1f1f},
  635. {0x800000E8,0x00694094},
  636. {0x800000EC,0x006a1b1b},
  637. {0x800000F0,0x0054a020},//PSKEY: 54=A020 AGCMAX=A0 AGCMIN=20                    
  638. {0x800000F4,0x0055a020},//PSKEY: 55=A020 AGC_TH_max_lg=a0 agc_th_min_lg =0x20  
  639. {0x800000F8,0x0056a542},//PSKEY: 56=a542                                        
  640. {0x800000Fc,0x00574c18},//PSKEY: 57=4c18                                        
  641. {0x80000100,0x003f0001},//PSKEY: page=1                                        
  642. {0x80000104,0x00410c80},//PSKEY: phase delay                                    
  643. {0x80000108,0x004603f1},
  644. {0x8000010c,0x003f0000},//PSKEY: page =0                                        
  645. {0x80000110,0x00000000},//PSKEY: page =0                                        
  646. {0x80000040,0x10000000},//PSKEY: flag                                          
  647. {0x40240000,0x0000F29c},//enable spi2
  648.  
  649. #endif
  650. };
  651. __u32 rdabt_dccal_10_e[][2]=
  652. {
  653. {0x0000003f,0x00000000},
  654. {0x00000030,0x00000169},
  655. {0x0000003C,0x00000002},
  656. {0x00000030,0x0000016B},
  657. {0x00000030,0x0000012B}
  658. };
  659. __u32 rda_pskey_10[][2] =
  660. {
  661. //sleep
  662. {0x80000070,0x00002008},//disalbe esco
  663. {0x80000074,0xa5025010},//sleep
  664. {0x800000a8,0x0Bbfbf30},//min power level
  665. {0x80000040,0x04003000},//PSKEY: modify flag
  666.  
  667. {0x800000a4,0x08a0280a},
  668. {0x80000040,0x02000000},
  669.                              
  670. //{0x80003ff8,,0x788dffff},//disable edr
  671. #ifndef __RDA_SHARE_CRYSTAL__
  672.  
  673. #endif
  674. };
  675. __u32 rdabt_unsniff_prerxon_10[2] = {0x800067f4,0x00000864};
  676.  
  677. __u32 rda_filter_10[2] = {0x800004c4,0x00000000};//{0x01,0x72,0xfc,0x05,0x01,0x00,0x00,0x00,0x00};
  678.  
  679. __u32 rda_trap_10[][2] =
  680. {
  681. {0x800000C4,0xFC00FC1B},//tc map table
  682. {0x800000C8,0xFC00FC66},
  683. {0x800000CC,0xFD42FC42},
  684. {0x800000D0,0xFC00FC34},
  685. {0x800000D4,0xFC00FC76},
  686. {0x800000D8,0xFC1DFC56},
  687. {0x800000DC,0xFC0BFC5B},
  688. {0x800000E0,0xFC00FC1E},
  689. {0x800000E4,0x00000000},
  690. {0x800078A8,0x800000C4},
  691.  
  692. {0x80000000,0xea00001e},//sleep rom
  693. {0x80000080,0xe1a00000},
  694. {0x80000084,0xe1a00000},
  695. {0x80000088,0xe1a00000},
  696. {0x8000008c,0xe1a00000},
  697. {0x80000090,0xe2800001},
  698. {0x80000094,0xe3500020},
  699. {0x80000098,0xbafffff8},
  700. {0x8000009c,0xe3a00b8a},
  701. {0x800000a0,0xe280fffe},
  702. {0x800000a4,0xe3a0f480},
  703. {0x40180010,0x00022bc8},
  704. {0x40180030,0x800000a4},
  705.  
  706. {0x40180014,0x00003e20},//name length patch
  707. {0x40180034,0x00022df8},
  708.                      
  709. {0x40180018,0x0002bbac},//diable simple pair
  710. {0x40180038,0x0002dc14},
  711.                      
  712.                      
  713. {0x80000004,0xea00003A},//master poll interval to 0
  714. {0x800000F4,0xe59f5014},
  715. {0x800000F8,0xe5d55001},
  716. {0x800000Fc,0x03550000},
  717. {0x80000100,0xe3a05cfd},
  718. {0x80000104,0x1285f010},
  719. {0x80000108,0x03a02f7e},
  720. {0x8000010c,0xe285f00c},
  721. {0x80000110,0x800057Dc},
  722. {0x4018001c,0x0000fd08},
  723. {0x4018003c,0x00032e7c},
  724.  
  725. #if 0
  726. {0x80000008,0xea000041},//orign opcode =0
  727. {0x80000114,0xe3500000},
  728. {0x80000118,0xe3a00b95},
  729. {0x8000011c,0x1280f0e4},
  730. {0x80000120,0xe280f0d8},
  731. {0x40180020,0x000254d4},
  732. {0x40180040,0x00032e80},
  733. #else
  734. {0x80000008,0xea000069},
  735. {0x800001b4,0xe3a0eb95},
  736. {0x800001b8,0xe28ee0e4},
  737. {0x800001bc,0xea000003},
  738. {0x800001c0,0xe51ff004},
  739. {0x800001c4,0x00001974},
  740. {0x800001c8,0xe51ff004},
  741. {0x800001cc,0x00001688},
  742. {0x800001d0,0xe92d4008},
  743. {0x800001d4,0xe3a02004},
  744. {0x800001d8,0xe3a01000},
  745. {0x800001dc,0xe3a00000},
  746. {0x800001e0,0xebfffff6},
  747. {0x800001e4,0xe1a02000},
  748. {0x800001e8,0xe5921000},
  749. {0x800001ec,0xe59f0018},
  750. {0x800001f0,0xe5810000},
  751. {0x800001f4,0xe3a00001},
  752. {0x800001f8,0xe1c201b2},
  753. {0x800001fc,0xe8bd4008},
  754. {0x80000200,0xe3a00000},
  755. {0x80000204,0xe3a01000},
  756. {0x80000208,0xeaffffee},
  757. {0x8000020c,0x0000fcc0},
  758. {0x40180020,0x000254d4},
  759. {0x40180040,0x00032e80},
  760. #endif
  761.  
  762. {0x8000000c,0xea000044},//disable switch twice
  763. {0x80000124,0xe1a05001},
  764. {0x80000128,0xe5d11000},
  765. {0x8000012C,0xe3510001},
  766. {0x80000130,0xe3a01b66},
  767. {0x80000134,0x0281f014},
  768. {0x80000138,0x1281f044},
  769. {0x40180100,0x00019810},
  770. {0x40180120,0x00032e84},
  771.  
  772. {0x80000010,0xea00004a},///queues init
  773. {0x80000140,0xe3a03f56},
  774. {0x80000144,0xe3a01006},
  775. {0x80000148,0xe3a0ebab},
  776. {0x8000014c,0xe28eff53},
  777. {0x40180104,0x0002ad44},
  778. {0x40180124,0x00032e88},
  779.  
  780. #if defined( _RDA_PATCH_UART3_) || defined(_RDA_PATCH_UART4_)
  781. {0x80000014,0xea0014b4},//buff init start address
  782. #else
  783. {0x80000014,0xEA00004d},
  784. {0x80000150,0xe59f0048},
  785. {0x80000154,0xe3a01004},        
  786. {0x80000158,0xe1c010b6},  
  787. {0x8000015c,0xe1c010b4},
  788. {0x80000160,0xe59f103c},
  789. {0x80000164,0xe2812048},
  790. {0x80000168,0xe580200c},
  791. {0x8000016c,0xe3a00000},
  792. {0x80000170,0xe581005c},
  793. {0x80000174,0xe59f202c},
  794. {0x80000178,0xe3a00008},
  795. {0x8000017c,0xe1c200b6},
  796. {0x80000180,0xe1c200b4},
  797. {0x80000184,0xe2813060},
  798. {0x80000188,0xe5823008},
  799. {0x8000018c,0xe2812094},
  800. {0x80000190,0xe581208c},
  801. {0x80000194,0xe59f1010},
  802. {0x80000198,0xe1c108b8},
  803. {0x8000019c,0xe49df004},
  804. {0x800001a0,0x80002c58},
  805. {0x800001a4,0x80002c94},
  806. {0x800001a8,0x80002c6c},
  807. {0x800001ac,0x80003fd4},
  808. #endif
  809.  
  810. {0x40180108,0x00008468},
  811. {0x40180128,0x00032e8c},
  812.                      
  813.                      
  814. {0x4018010c,0x00011e2c},//sniff slave accept auto
  815. {0x4018012c,0x00012020},
  816.                      
  817. {0x40180110,0x00003448},//uart len>240
  818. {0x40180130,0x0001d548},
  819.  
  820. #if defined(_RDA_PATCH_UART4_)
  821. {0x80000018,0xea000080},///delay reset
  822. {0x80000220,0xe3a00e32},
  823. {0x80000224,0xe59fe010},
  824. {0x80000228,0xe3a01c55},
  825. {0x8000022c,0xe281f084},
  826. {0x80000230,0xe59f0008},
  827. {0x80000234,0xe3a01c0f},
  828. {0x80000238,0xe281f014},
  829. {0x8000023c,0x80000230},
  830. {0x80000240,0x00000c03},
  831. {0x40180114,0x00000f10},
  832. {0x40180134,0x00032e90},
  833.  
  834.  
  835. {0x8000001c,0xea00008b},////acl buff
  836. {0x80000250,0xe3a02004},
  837. {0x80000254,0xe3a03000},
  838. {0x80000258,0xe3a0ec3a},
  839. {0x8000025c,0xe28ef0a0},
  840. {0x40180118,0x00003a98},
  841. {0x40180138,0x00032e94},
  842.  
  843.  
  844. {0x80000020,0xea000098},////fcd1
  845. {0x80000288,0xe5d00000},
  846. {0x8000028c,0xe3500000},
  847. {0x80000290,0x059f0020},
  848. {0x80000294,0x0a000005},
  849. {0x80000298,0xe3500004},
  850. {0x8000029c,0x059f0018},
  851. {0x800002a0,0x0a000002},
  852. {0x800002a4,0xe3500008},
  853. {0x800002a8,0x159f0010},
  854. {0x800002ac,0x059f0010},
  855. {0x800002b0,0xe5810010},
  856. {0x800002b4,0xe1a0f00e},
  857. {0x800002b8,0x00008c03},
  858. {0x800002bc,0x00008c01},
  859. {0x800002c0,0x00008a01},
  860. {0x800002c4,0x00006612},
  861. {0x4018011c,0x00023254},
  862. {0x4018013c,0x00032e98},
  863. #endif
  864.  
  865. #if defined( _RDA_PATCH_UART3_) || defined(_RDA_PATCH_UART4_)
  866. {0x50000044,0x00000001},
  867. #else
  868. {0x50000044,0x00220003},
  869. #endif
  870. {0x8000005c,0x03300000},//
  871. {0x80000040,0x00000080},//flag
  872.  
  873.  
  874. #if defined(_RDA_PATCH_UART2_) || defined(_RDA_PATCH_UART3_)  || defined(_RDA_PATCH_UART4_)
  875.  
  876. #if 1
  877. #if defined( _RDA_PATCH_UART3_)  || defined(_RDA_PATCH_UART4_)
  878. {0x80000064,0x0030d400},//new baudrate 3200000
  879. #else
  880. {0x80000064,0x000e1000},//new baudrate 921600
  881. #endif
  882.  
  883. {0x8000005c,0x03300000},//convert baud delay 16slot
  884. {0x80000040,0x00000280},//flag
  885. #endif
  886. #if defined (_RDA_PATCH_UART3_)  || defined(_RDA_PATCH_UART4_)
  887. {0x80004c38,0x00000001},//flag chip
  888. #else
  889. {0x80004c38,0x00000000},
  890. #endif
  891. {0x80004c3c,0x00000000},
  892.  
  893.  
  894. {0x40180004,0x00003208},
  895. {0x40180024,0x800051B4},//patch uart rx
  896.                      
  897. {0x800000C0,0xEA001454},
  898. {0x40180008,0x000034E4},
  899. {0x40180028,0x80005214},//patch uart tx
  900.                      
  901. {0x4018000C,0x00031C58},
  902. {0x4018002C,0x800052A4},//patch uart convert baud
  903. #if defined(_RDA_PATCH_UART4_)
  904. {0x40180000,0x0000ffff},//patch flag
  905. #else
  906. {0x40180000,0x00001fff},//patch flag
  907. #endif
  908. #else
  909. {0x40180000,0x00001ff8},//patch flag
  910. #endif
  911.  
  912. };
  913. void RDA5870E_SET_TM(int fd)
  914. {  
  915.     RDA_uart_write_array(fd,rda5870e_set_tm,sizeof(rda5870e_set_tm)/sizeof(rda5870e_set_tm[0]),1);
  916.     usleep(50000);//50ms?
  917. }
  918.  
  919. void RDABT_rf_Intialization_r10_e(int fd)
  920. {
  921.     RDA_uart_write_array(fd,rdabt_rf_init_10_e,sizeof(rdabt_rf_init_10_e)/sizeof(rdabt_rf_init_10_e[0]),1);
  922.     usleep(50000);//50ms?
  923. }
  924. void Rdabt_Pskey_Write_rf_r10_e(int fd)
  925. {
  926.     RDA_uart_write_array(fd,rdabt_pskey_rf_10_e,sizeof(rdabt_pskey_rf_10_e)/sizeof(rdabt_pskey_rf_10_e[0]),0);
  927. }
  928. void rdabt_DC_write_r10_e(int fd)
  929. {
  930.     //RDA_uart_write_array(fd,rdabt_dccal_10_e,sizeof(rdabt_dccal_10_e)/sizeof(rdabt_dccal_10_e[0]),1);
  931.    __u32 i;
  932.    for(i=0;i<((sizeof(rdabt_dccal_10_e)/sizeof(rdabt_dccal_10_e[0])) -1);i++)
  933.    {
  934.       rdabt_write_memory(fd,rdabt_dccal_10_e[i][0],&rdabt_dccal_10_e[i][1],1,1);
  935.       usleep(12000);//12ms?
  936.    }   
  937.       usleep(20000);
  938.  
  939.       rdabt_write_memory(fd,rdabt_dccal_10_e[i][0],&rdabt_dccal_10_e[i][1],1,1);
  940.       usleep(12000);//12ms?
  941.  
  942. }
  943. void Rdabt_Pskey_Write_r10(int fd)
  944. {
  945.     RDA_uart_write_array(fd,rda_pskey_10,sizeof(rda_pskey_10)/sizeof(rda_pskey_10[0]),0);
  946. }
  947.  
  948. void Rdabt_unsniff_prerxon_write_r10(int fd)
  949. {
  950.     RDA_uart_write_array(fd,rdabt_unsniff_prerxon_10,sizeof(rdabt_unsniff_prerxon_10)/sizeof(rdabt_unsniff_prerxon_10[0]),0);
  951. }
  952. void Rdabt_setfilter_r10(int fd)
  953. {
  954.     RDA_uart_write_array(fd,rda_filter_10,sizeof(rda_filter_10)/sizeof(rda_filter_10[0]),0);
  955. }
  956. void Rdabt_trap_write_r10(int fd)
  957. {
  958.     RDA_uart_write_array(fd,rda_trap_10,sizeof(rda_trap_10)/sizeof(rda_trap_10[0]),0);
  959. }
  960.  
  961. #endif
  962. int RDABT_core_Intialization(int fd)
  963. {
  964.     int bt_fd = -1;
  965.     bt_fd = open(TCC_BT_DEVICE_PATH, O_RDWR);
  966.     if( bt_fd < 0 )
  967.     {
  968.         perror("[###### TCC BT #######] open error");
  969.         return -1;
  970.     }
  971.  
  972. #ifdef __RDA_CHIP_R11_5875__
  973.     RDA_pin_to_high(bt_fd);
  974.     RDA5872P_RfInit(fd);
  975.     RDA5872P_Pskey_RfInit(fd);
  976.     RDA_pin_to_low(bt_fd);
  977.     RDA_pin_to_high(bt_fd);
  978.     usleep(50000);
  979.     RDA5872P_RfInit(fd);  
  980.     RDA5872P_Pskey_RfInit(fd);
  981.     RDA5872P_Dccal(fd);
  982.     RDA5872P_Pskey_Misc(fd);
  983.     RDA5872P_Trap(fd);
  984. #elif defined(__RDA_CHIP_R10_5870E__)
  985.  
  986.     RDA_pin_to_high(bt_fd);
  987.     RDABT_rf_Intialization_r10_e(fd);
  988.     RDA_pin_to_low(bt_fd);
  989.     RDA_pin_to_high(bt_fd);  
  990.     usleep(50000);
  991.     //RDA5870E_SET_TM(fd);
  992.     RDABT_rf_Intialization_r10_e(fd);  
  993.     Rdabt_Pskey_Write_rf_r10_e(fd);
  994.     usleep(5000);
  995.     rdabt_DC_write_r10_e(fd);
  996.     Rdabt_Pskey_Write_r10(fd);
  997.     Rdabt_unsniff_prerxon_write_r10(fd);
  998.     Rdabt_setfilter_r10(fd);
  999.     Rdabt_trap_write_r10(fd);
  1000. #elif defined(__RDA_CHIP_R11_5876__)
  1001.  
  1002.   RDA_pin_to_high(bt_fd);
  1003.     RDA5876_RfInit(fd);
  1004.     RDA5876_Pskey_RfInit(fd);
  1005.  
  1006.     RDA_pin_to_low(bt_fd);
  1007.     RDA_pin_to_high(bt_fd);
  1008.     usleep(50000);
  1009.  
  1010.     RDA5876_RfInit(fd);  
  1011.     RDA5876_Pskey_RfInit(fd);
  1012.  
  1013.     RDA5876_Dccal(fd); 
  1014.     RDA5876_Trap(fd);              
  1015.   RDA5876_Pskey_Misc(fd);          
  1016. #endif
  1017.  
  1018.    
  1019.     return 0;
  1020. }
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