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Arch Linux Device Tree Overlay with working UART4

tmax
Sep 22nd, 2015
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  1. /dts-v1/;
  2.  
  3. / {
  4. #address-cells = <0x1>;
  5. #size-cells = <0x1>;
  6. compatible = "ti,omap4-panda-es", "ti,omap4-panda", "ti,omap4460", "ti,omap4430", "ti,omap4";
  7. interrupt-parent = <0x1>;
  8. model = "TI OMAP4 PandaBoard-ES";
  9.  
  10. chosen {
  11. };
  12.  
  13. aliases {
  14. i2c0 = "/ocp/i2c@48070000";
  15. i2c1 = "/ocp/i2c@48072000";
  16. i2c2 = "/ocp/i2c@48060000";
  17. i2c3 = "/ocp/i2c@48350000";
  18. serial0 = "/ocp/serial@4806a000";
  19. serial1 = "/ocp/serial@4806c000";
  20. serial2 = "/ocp/serial@48020000";
  21. serial3 = "/ocp/serial@4806e000";
  22. display0 = "/connector@0";
  23. display1 = "/connector@1";
  24. };
  25.  
  26. memory {
  27. device_type = "memory";
  28. reg = <0x80000000 0x40000000>;
  29. };
  30.  
  31. cpus {
  32. #address-cells = <0x1>;
  33. #size-cells = <0x0>;
  34.  
  35. cpu@0 {
  36. compatible = "arm,cortex-a9";
  37. device_type = "cpu";
  38. next-level-cache = <0x2>;
  39. reg = <0x0>;
  40. clocks = <0x3>;
  41. clock-names = "cpu";
  42. clock-latency = <0x493e0>;
  43. operating-points = <0x55730 0xfa3e8 0xaae60 0x124f80 0xe09c0 0x1408e8>;
  44. cooling-min-level = <0x0>;
  45. cooling-max-level = <0x2>;
  46. #cooling-cells = <0x2>;
  47. linux,phandle = <0xa7>;
  48. phandle = <0xa7>;
  49. };
  50.  
  51. cpu@1 {
  52. compatible = "arm,cortex-a9";
  53. device_type = "cpu";
  54. next-level-cache = <0x2>;
  55. reg = <0x1>;
  56. };
  57. };
  58.  
  59. interrupt-controller@48241000 {
  60. compatible = "arm,cortex-a9-gic";
  61. interrupt-controller;
  62. #interrupt-cells = <0x3>;
  63. reg = <0x48241000 0x1000 0x48240100 0x100>;
  64. interrupt-parent = <0x4>;
  65. linux,phandle = <0x4>;
  66. phandle = <0x4>;
  67. };
  68.  
  69. l2-cache-controller@48242000 {
  70. compatible = "arm,pl310-cache";
  71. reg = <0x48242000 0x1000>;
  72. cache-unified;
  73. cache-level = <0x2>;
  74. linux,phandle = <0x2>;
  75. phandle = <0x2>;
  76. };
  77.  
  78. local-timer@48240600 {
  79. compatible = "arm,cortex-a9-twd-timer";
  80. clocks = <0x5>;
  81. reg = <0x48240600 0x20>;
  82. interrupts = <0x1 0xd 0x304>;
  83. interrupt-parent = <0x4>;
  84. };
  85.  
  86. interrupt-controller@48281000 {
  87. compatible = "ti,omap4-wugen-mpu";
  88. interrupt-controller;
  89. #interrupt-cells = <0x3>;
  90. reg = <0x48281000 0x1000>;
  91. interrupt-parent = <0x4>;
  92. linux,phandle = <0x1>;
  93. phandle = <0x1>;
  94. };
  95.  
  96. soc {
  97. compatible = "ti,omap-infra";
  98.  
  99. mpu {
  100. compatible = "ti,omap4-mpu";
  101. ti,hwmods = "mpu";
  102. sram = <0x6>;
  103. };
  104.  
  105. dsp {
  106. compatible = "ti,omap3-c64";
  107. ti,hwmods = "dsp";
  108. };
  109.  
  110. iva {
  111. compatible = "ti,ivahd";
  112. ti,hwmods = "iva";
  113. };
  114. };
  115.  
  116. ocp {
  117. compatible = "ti,omap4-l3-noc", "simple-bus";
  118. #address-cells = <0x1>;
  119. #size-cells = <0x1>;
  120. ranges;
  121. ti,hwmods = "l3_main_1", "l3_main_2", "l3_main_3";
  122. reg = <0x44000000 0x1000 0x44800000 0x2000 0x45000000 0x1000>;
  123. interrupts = <0x0 0x9 0x4 0x0 0xa 0x4>;
  124.  
  125. l4@4a000000 { // pinctrl base address 4a000000
  126. compatible = "ti,omap4-l4-cfg", "simple-bus";
  127. #address-cells = <0x1>;
  128. #size-cells = <0x1>;
  129. ranges = <0x0 0x4a000000 0x1000000>;
  130. linux,phandle = <0xb6>;
  131. phandle = <0xb6>;
  132.  
  133. cm1@4000 {
  134. compatible = "ti,omap4-cm1";
  135. reg = <0x4000 0x2000>;
  136. linux,phandle = <0xb7>;
  137. phandle = <0xb7>;
  138.  
  139. clocks {
  140. #address-cells = <0x1>;
  141. #size-cells = <0x0>;
  142. linux,phandle = <0xb8>;
  143. phandle = <0xb8>;
  144.  
  145. extalt_clkin_ck {
  146. #clock-cells = <0x0>;
  147. compatible = "fixed-clock";
  148. clock-frequency = <0x38444c0>;
  149. linux,phandle = <0x3a>;
  150. phandle = <0x3a>;
  151. };
  152.  
  153. pad_clks_src_ck {
  154. #clock-cells = <0x0>;
  155. compatible = "fixed-clock";
  156. clock-frequency = <0xb71b00>;
  157. linux,phandle = <0x7>;
  158. phandle = <0x7>;
  159. };
  160.  
  161. pad_clks_ck {
  162. #clock-cells = <0x0>;
  163. compatible = "ti,gate-clock";
  164. clocks = <0x7>;
  165. ti,bit-shift = <0x8>;
  166. reg = <0x108>;
  167. linux,phandle = <0x26>;
  168. phandle = <0x26>;
  169. };
  170.  
  171. pad_slimbus_core_clks_ck {
  172. #clock-cells = <0x0>;
  173. compatible = "fixed-clock";
  174. clock-frequency = <0xb71b00>;
  175. linux,phandle = <0x46>;
  176. phandle = <0x46>;
  177. };
  178.  
  179. secure_32k_clk_src_ck {
  180. #clock-cells = <0x0>;
  181. compatible = "fixed-clock";
  182. clock-frequency = <0x8000>;
  183. linux,phandle = <0xb9>;
  184. phandle = <0xb9>;
  185. };
  186.  
  187. slimbus_src_clk {
  188. #clock-cells = <0x0>;
  189. compatible = "fixed-clock";
  190. clock-frequency = <0xb71b00>;
  191. linux,phandle = <0x8>;
  192. phandle = <0x8>;
  193. };
  194.  
  195. slimbus_clk {
  196. #clock-cells = <0x0>;
  197. compatible = "ti,gate-clock";
  198. clocks = <0x8>;
  199. ti,bit-shift = <0xa>;
  200. reg = <0x108>;
  201. linux,phandle = <0x27>;
  202. phandle = <0x27>;
  203. };
  204.  
  205. sys_32k_ck {
  206. #clock-cells = <0x0>;
  207. compatible = "fixed-clock";
  208. clock-frequency = <0x8000>;
  209. linux,phandle = <0x2c>;
  210. phandle = <0x2c>;
  211. };
  212.  
  213. virt_12000000_ck {
  214. #clock-cells = <0x0>;
  215. compatible = "fixed-clock";
  216. clock-frequency = <0xb71b00>;
  217. linux,phandle = <0x58>;
  218. phandle = <0x58>;
  219. };
  220.  
  221. virt_13000000_ck {
  222. #clock-cells = <0x0>;
  223. compatible = "fixed-clock";
  224. clock-frequency = <0xc65d40>;
  225. linux,phandle = <0x59>;
  226. phandle = <0x59>;
  227. };
  228.  
  229. virt_16800000_ck {
  230. #clock-cells = <0x0>;
  231. compatible = "fixed-clock";
  232. clock-frequency = <0x1005900>;
  233. linux,phandle = <0x5a>;
  234. phandle = <0x5a>;
  235. };
  236.  
  237. virt_19200000_ck {
  238. #clock-cells = <0x0>;
  239. compatible = "fixed-clock";
  240. clock-frequency = <0x124f800>;
  241. linux,phandle = <0x5b>;
  242. phandle = <0x5b>;
  243. };
  244.  
  245. virt_26000000_ck {
  246. #clock-cells = <0x0>;
  247. compatible = "fixed-clock";
  248. clock-frequency = <0x18cba80>;
  249. linux,phandle = <0x5c>;
  250. phandle = <0x5c>;
  251. };
  252.  
  253. virt_27000000_ck {
  254. #clock-cells = <0x0>;
  255. compatible = "fixed-clock";
  256. clock-frequency = <0x19bfcc0>;
  257. linux,phandle = <0x5d>;
  258. phandle = <0x5d>;
  259. };
  260.  
  261. virt_38400000_ck {
  262. #clock-cells = <0x0>;
  263. compatible = "fixed-clock";
  264. clock-frequency = <0x249f000>;
  265. linux,phandle = <0x5e>;
  266. phandle = <0x5e>;
  267. };
  268.  
  269. tie_low_clock_ck {
  270. #clock-cells = <0x0>;
  271. compatible = "fixed-clock";
  272. clock-frequency = <0x0>;
  273. linux,phandle = <0x62>;
  274. phandle = <0x62>;
  275. };
  276.  
  277. utmi_phy_clkout_ck {
  278. #clock-cells = <0x0>;
  279. compatible = "fixed-clock";
  280. clock-frequency = <0x3938700>;
  281. linux,phandle = <0x4d>;
  282. phandle = <0x4d>;
  283. };
  284.  
  285. xclk60mhsp1_ck {
  286. #clock-cells = <0x0>;
  287. compatible = "fixed-clock";
  288. clock-frequency = <0x3938700>;
  289. linux,phandle = <0x49>;
  290. phandle = <0x49>;
  291. };
  292.  
  293. xclk60mhsp2_ck {
  294. #clock-cells = <0x0>;
  295. compatible = "fixed-clock";
  296. clock-frequency = <0x3938700>;
  297. linux,phandle = <0x4b>;
  298. phandle = <0x4b>;
  299. };
  300.  
  301. xclk60motg_ck {
  302. #clock-cells = <0x0>;
  303. compatible = "fixed-clock";
  304. clock-frequency = <0x3938700>;
  305. linux,phandle = <0x4e>;
  306. phandle = <0x4e>;
  307. };
  308.  
  309. dpll_abe_ck {
  310. #clock-cells = <0x0>;
  311. compatible = "ti,omap4-dpll-m4xen-clock";
  312. clocks = <0x9 0xa>;
  313. reg = <0x1e0 0x1e4 0x1ec 0x1e8>;
  314. linux,phandle = <0xb>;
  315. phandle = <0xb>;
  316. };
  317.  
  318. dpll_abe_x2_ck {
  319. #clock-cells = <0x0>;
  320. compatible = "ti,omap4-dpll-x2-clock";
  321. clocks = <0xb>;
  322. reg = <0x1f0>;
  323. linux,phandle = <0xc>;
  324. phandle = <0xc>;
  325. };
  326.  
  327. dpll_abe_m2x2_ck {
  328. #clock-cells = <0x0>;
  329. compatible = "ti,divider-clock";
  330. clocks = <0xc>;
  331. ti,max-div = <0x1f>;
  332. ti,autoidle-shift = <0x8>;
  333. reg = <0x1f0>;
  334. ti,index-starts-at-one;
  335. ti,invert-autoidle-bit;
  336. linux,phandle = <0xd>;
  337. phandle = <0xd>;
  338. };
  339.  
  340. abe_24m_fclk {
  341. #clock-cells = <0x0>;
  342. compatible = "fixed-factor-clock";
  343. clocks = <0xd>;
  344. clock-mult = <0x1>;
  345. clock-div = <0x8>;
  346. linux,phandle = <0x22>;
  347. phandle = <0x22>;
  348. };
  349.  
  350. abe_clk {
  351. #clock-cells = <0x0>;
  352. compatible = "ti,divider-clock";
  353. clocks = <0xd>;
  354. ti,max-div = <0x4>;
  355. reg = <0x108>;
  356. ti,index-power-of-two;
  357. linux,phandle = <0xe>;
  358. phandle = <0xe>;
  359. };
  360.  
  361. aess_fclk {
  362. #clock-cells = <0x0>;
  363. compatible = "ti,divider-clock";
  364. clocks = <0xe>;
  365. ti,bit-shift = <0x18>;
  366. ti,max-div = <0x2>;
  367. reg = <0x528>;
  368. linux,phandle = <0x20>;
  369. phandle = <0x20>;
  370. };
  371.  
  372. dpll_abe_m3x2_ck {
  373. #clock-cells = <0x0>;
  374. compatible = "ti,divider-clock";
  375. clocks = <0xc>;
  376. ti,max-div = <0x1f>;
  377. ti,autoidle-shift = <0x8>;
  378. reg = <0x1f4>;
  379. ti,index-starts-at-one;
  380. ti,invert-autoidle-bit;
  381. linux,phandle = <0x10>;
  382. phandle = <0x10>;
  383. };
  384.  
  385. core_hsd_byp_clk_mux_ck {
  386. #clock-cells = <0x0>;
  387. compatible = "ti,mux-clock";
  388. clocks = <0xf 0x10>;
  389. ti,bit-shift = <0x17>;
  390. reg = <0x12c>;
  391. linux,phandle = <0x11>;
  392. phandle = <0x11>;
  393. };
  394.  
  395. dpll_core_ck {
  396. #clock-cells = <0x0>;
  397. compatible = "ti,omap4-dpll-core-clock";
  398. clocks = <0xf 0x11>;
  399. reg = <0x120 0x124 0x12c 0x128>;
  400. linux,phandle = <0x12>;
  401. phandle = <0x12>;
  402. };
  403.  
  404. dpll_core_x2_ck {
  405. #clock-cells = <0x0>;
  406. compatible = "ti,omap4-dpll-x2-clock";
  407. clocks = <0x12>;
  408. linux,phandle = <0x13>;
  409. phandle = <0x13>;
  410. };
  411.  
  412. dpll_core_m6x2_ck {
  413. #clock-cells = <0x0>;
  414. compatible = "ti,divider-clock";
  415. clocks = <0x13>;
  416. ti,max-div = <0x1f>;
  417. ti,autoidle-shift = <0x8>;
  418. reg = <0x140>;
  419. ti,index-starts-at-one;
  420. ti,invert-autoidle-bit;
  421. linux,phandle = <0x61>;
  422. phandle = <0x61>;
  423. };
  424.  
  425. dpll_core_m2_ck {
  426. #clock-cells = <0x0>;
  427. compatible = "ti,divider-clock";
  428. clocks = <0x12>;
  429. ti,max-div = <0x1f>;
  430. ti,autoidle-shift = <0x8>;
  431. reg = <0x130>;
  432. ti,index-starts-at-one;
  433. ti,invert-autoidle-bit;
  434. linux,phandle = <0x14>;
  435. phandle = <0x14>;
  436. };
  437.  
  438. ddrphy_ck {
  439. #clock-cells = <0x0>;
  440. compatible = "fixed-factor-clock";
  441. clocks = <0x14>;
  442. clock-mult = <0x1>;
  443. clock-div = <0x2>;
  444. linux,phandle = <0xba>;
  445. phandle = <0xba>;
  446. };
  447.  
  448. dpll_core_m5x2_ck {
  449. #clock-cells = <0x0>;
  450. compatible = "ti,divider-clock";
  451. clocks = <0x13>;
  452. ti,max-div = <0x1f>;
  453. ti,autoidle-shift = <0x8>;
  454. reg = <0x13c>;
  455. ti,index-starts-at-one;
  456. ti,invert-autoidle-bit;
  457. linux,phandle = <0x15>;
  458. phandle = <0x15>;
  459. };
  460.  
  461. div_core_ck {
  462. #clock-cells = <0x0>;
  463. compatible = "ti,divider-clock";
  464. clocks = <0x15>;
  465. reg = <0x100>;
  466. ti,max-div = <0x2>;
  467. linux,phandle = <0x1e>;
  468. phandle = <0x1e>;
  469. };
  470.  
  471. div_iva_hs_clk {
  472. #clock-cells = <0x0>;
  473. compatible = "ti,divider-clock";
  474. clocks = <0x15>;
  475. ti,max-div = <0x4>;
  476. reg = <0x1dc>;
  477. ti,index-power-of-two;
  478. linux,phandle = <0x19>;
  479. phandle = <0x19>;
  480. };
  481.  
  482. div_mpu_hs_clk {
  483. #clock-cells = <0x0>;
  484. compatible = "ti,divider-clock";
  485. clocks = <0x15>;
  486. ti,max-div = <0x4>;
  487. reg = <0x19c>;
  488. ti,index-power-of-two;
  489. linux,phandle = <0x1d>;
  490. phandle = <0x1d>;
  491. };
  492.  
  493. dpll_core_m4x2_ck {
  494. #clock-cells = <0x0>;
  495. compatible = "ti,divider-clock";
  496. clocks = <0x13>;
  497. ti,max-div = <0x1f>;
  498. ti,autoidle-shift = <0x8>;
  499. reg = <0x138>;
  500. ti,index-starts-at-one;
  501. ti,invert-autoidle-bit;
  502. linux,phandle = <0x16>;
  503. phandle = <0x16>;
  504. };
  505.  
  506. dll_clk_div_ck {
  507. #clock-cells = <0x0>;
  508. compatible = "fixed-factor-clock";
  509. clocks = <0x16>;
  510. clock-mult = <0x1>;
  511. clock-div = <0x2>;
  512. linux,phandle = <0xbb>;
  513. phandle = <0xbb>;
  514. };
  515.  
  516. dpll_abe_m2_ck {
  517. #clock-cells = <0x0>;
  518. compatible = "ti,divider-clock";
  519. clocks = <0xb>;
  520. ti,max-div = <0x1f>;
  521. reg = <0x1f0>;
  522. ti,index-starts-at-one;
  523. linux,phandle = <0x21>;
  524. phandle = <0x21>;
  525. };
  526.  
  527. dpll_core_m3x2_gate_ck {
  528. #clock-cells = <0x0>;
  529. compatible = "ti,composite-no-wait-gate-clock";
  530. clocks = <0x13>;
  531. ti,bit-shift = <0x8>;
  532. reg = <0x134>;
  533. linux,phandle = <0x17>;
  534. phandle = <0x17>;
  535. };
  536.  
  537. dpll_core_m3x2_div_ck {
  538. #clock-cells = <0x0>;
  539. compatible = "ti,composite-divider-clock";
  540. clocks = <0x13>;
  541. ti,max-div = <0x1f>;
  542. reg = <0x134>;
  543. ti,index-starts-at-one;
  544. linux,phandle = <0x18>;
  545. phandle = <0x18>;
  546. };
  547.  
  548. dpll_core_m3x2_ck {
  549. #clock-cells = <0x0>;
  550. compatible = "ti,composite-clock";
  551. clocks = <0x17 0x18>;
  552. linux,phandle = <0x68>;
  553. phandle = <0x68>;
  554. };
  555.  
  556. dpll_core_m7x2_ck {
  557. #clock-cells = <0x0>;
  558. compatible = "ti,divider-clock";
  559. clocks = <0x13>;
  560. ti,max-div = <0x1f>;
  561. ti,autoidle-shift = <0x8>;
  562. reg = <0x144>;
  563. ti,index-starts-at-one;
  564. ti,invert-autoidle-bit;
  565. linux,phandle = <0x3d>;
  566. phandle = <0x3d>;
  567. };
  568.  
  569. iva_hsd_byp_clk_mux_ck {
  570. #clock-cells = <0x0>;
  571. compatible = "ti,mux-clock";
  572. clocks = <0xf 0x19>;
  573. ti,bit-shift = <0x17>;
  574. reg = <0x1ac>;
  575. linux,phandle = <0x1a>;
  576. phandle = <0x1a>;
  577. };
  578.  
  579. dpll_iva_ck {
  580. #clock-cells = <0x0>;
  581. compatible = "ti,omap4-dpll-clock";
  582. clocks = <0xf 0x1a>;
  583. reg = <0x1a0 0x1a4 0x1ac 0x1a8>;
  584. linux,phandle = <0x1b>;
  585. phandle = <0x1b>;
  586. };
  587.  
  588. dpll_iva_x2_ck {
  589. #clock-cells = <0x0>;
  590. compatible = "ti,omap4-dpll-x2-clock";
  591. clocks = <0x1b>;
  592. linux,phandle = <0x1c>;
  593. phandle = <0x1c>;
  594. };
  595.  
  596. dpll_iva_m4x2_ck {
  597. #clock-cells = <0x0>;
  598. compatible = "ti,divider-clock";
  599. clocks = <0x1c>;
  600. ti,max-div = <0x1f>;
  601. ti,autoidle-shift = <0x8>;
  602. reg = <0x1b8>;
  603. ti,index-starts-at-one;
  604. ti,invert-autoidle-bit;
  605. linux,phandle = <0xbc>;
  606. phandle = <0xbc>;
  607. };
  608.  
  609. dpll_iva_m5x2_ck {
  610. #clock-cells = <0x0>;
  611. compatible = "ti,divider-clock";
  612. clocks = <0x1c>;
  613. ti,max-div = <0x1f>;
  614. ti,autoidle-shift = <0x8>;
  615. reg = <0x1bc>;
  616. ti,index-starts-at-one;
  617. ti,invert-autoidle-bit;
  618. linux,phandle = <0xbd>;
  619. phandle = <0xbd>;
  620. };
  621.  
  622. dpll_mpu_ck {
  623. #clock-cells = <0x0>;
  624. compatible = "ti,omap4-dpll-clock";
  625. clocks = <0xf 0x1d>;
  626. reg = <0x160 0x164 0x16c 0x168>;
  627. linux,phandle = <0x3>;
  628. phandle = <0x3>;
  629. };
  630.  
  631. dpll_mpu_m2_ck {
  632. #clock-cells = <0x0>;
  633. compatible = "ti,divider-clock";
  634. clocks = <0x3>;
  635. ti,max-div = <0x1f>;
  636. ti,autoidle-shift = <0x8>;
  637. reg = <0x170>;
  638. ti,index-starts-at-one;
  639. ti,invert-autoidle-bit;
  640. linux,phandle = <0xbe>;
  641. phandle = <0xbe>;
  642. };
  643.  
  644. per_hs_clk_div_ck {
  645. #clock-cells = <0x0>;
  646. compatible = "fixed-factor-clock";
  647. clocks = <0x10>;
  648. clock-mult = <0x1>;
  649. clock-div = <0x2>;
  650. linux,phandle = <0x2d>;
  651. phandle = <0x2d>;
  652. };
  653.  
  654. usb_hs_clk_div_ck {
  655. #clock-cells = <0x0>;
  656. compatible = "fixed-factor-clock";
  657. clocks = <0x10>;
  658. clock-mult = <0x1>;
  659. clock-div = <0x3>;
  660. linux,phandle = <0x33>;
  661. phandle = <0x33>;
  662. };
  663.  
  664. l3_div_ck {
  665. #clock-cells = <0x0>;
  666. compatible = "ti,divider-clock";
  667. clocks = <0x1e>;
  668. ti,bit-shift = <0x4>;
  669. ti,max-div = <0x2>;
  670. reg = <0x100>;
  671. linux,phandle = <0x1f>;
  672. phandle = <0x1f>;
  673. };
  674.  
  675. l4_div_ck {
  676. #clock-cells = <0x0>;
  677. compatible = "ti,divider-clock";
  678. clocks = <0x1f>;
  679. ti,bit-shift = <0x8>;
  680. ti,max-div = <0x2>;
  681. reg = <0x100>;
  682. linux,phandle = <0x50>;
  683. phandle = <0x50>;
  684. };
  685.  
  686. lp_clk_div_ck {
  687. #clock-cells = <0x0>;
  688. compatible = "fixed-factor-clock";
  689. clocks = <0xd>;
  690. clock-mult = <0x1>;
  691. clock-div = <0x10>;
  692. linux,phandle = <0x5f>;
  693. phandle = <0x5f>;
  694. };
  695.  
  696. mpu_periphclk {
  697. #clock-cells = <0x0>;
  698. compatible = "fixed-factor-clock";
  699. clocks = <0x3>;
  700. clock-mult = <0x1>;
  701. clock-div = <0x2>;
  702. linux,phandle = <0x5>;
  703. phandle = <0x5>;
  704. };
  705.  
  706. ocp_abe_iclk {
  707. #clock-cells = <0x0>;
  708. compatible = "ti,divider-clock";
  709. clocks = <0x20>;
  710. ti,bit-shift = <0x18>;
  711. reg = <0x528>;
  712. ti,dividers = <0x2 0x1>;
  713. linux,phandle = <0xbf>;
  714. phandle = <0xbf>;
  715. };
  716.  
  717. per_abe_24m_fclk {
  718. #clock-cells = <0x0>;
  719. compatible = "fixed-factor-clock";
  720. clocks = <0x21>;
  721. clock-mult = <0x1>;
  722. clock-div = <0x4>;
  723. linux,phandle = <0x44>;
  724. phandle = <0x44>;
  725. };
  726.  
  727. dmic_sync_mux_ck {
  728. #clock-cells = <0x0>;
  729. compatible = "ti,mux-clock";
  730. clocks = <0x22 0x23 0x24>;
  731. ti,bit-shift = <0x19>;
  732. reg = <0x538>;
  733. linux,phandle = <0x25>;
  734. phandle = <0x25>;
  735. };
  736.  
  737. func_dmic_abe_gfclk {
  738. #clock-cells = <0x0>;
  739. compatible = "ti,mux-clock";
  740. clocks = <0x25 0x26 0x27>;
  741. ti,bit-shift = <0x18>;
  742. reg = <0x538>;
  743. linux,phandle = <0xc0>;
  744. phandle = <0xc0>;
  745. };
  746.  
  747. mcasp_sync_mux_ck {
  748. #clock-cells = <0x0>;
  749. compatible = "ti,mux-clock";
  750. clocks = <0x22 0x23 0x24>;
  751. ti,bit-shift = <0x19>;
  752. reg = <0x540>;
  753. linux,phandle = <0x28>;
  754. phandle = <0x28>;
  755. };
  756.  
  757. func_mcasp_abe_gfclk {
  758. #clock-cells = <0x0>;
  759. compatible = "ti,mux-clock";
  760. clocks = <0x28 0x26 0x27>;
  761. ti,bit-shift = <0x18>;
  762. reg = <0x540>;
  763. linux,phandle = <0xc1>;
  764. phandle = <0xc1>;
  765. };
  766.  
  767. mcbsp1_sync_mux_ck {
  768. #clock-cells = <0x0>;
  769. compatible = "ti,mux-clock";
  770. clocks = <0x22 0x23 0x24>;
  771. ti,bit-shift = <0x19>;
  772. reg = <0x548>;
  773. linux,phandle = <0x29>;
  774. phandle = <0x29>;
  775. };
  776.  
  777. func_mcbsp1_gfclk {
  778. #clock-cells = <0x0>;
  779. compatible = "ti,mux-clock";
  780. clocks = <0x29 0x26 0x27>;
  781. ti,bit-shift = <0x18>;
  782. reg = <0x548>;
  783. linux,phandle = <0xc2>;
  784. phandle = <0xc2>;
  785. };
  786.  
  787. mcbsp2_sync_mux_ck {
  788. #clock-cells = <0x0>;
  789. compatible = "ti,mux-clock";
  790. clocks = <0x22 0x23 0x24>;
  791. ti,bit-shift = <0x19>;
  792. reg = <0x550>;
  793. linux,phandle = <0x2a>;
  794. phandle = <0x2a>;
  795. };
  796.  
  797. func_mcbsp2_gfclk {
  798. #clock-cells = <0x0>;
  799. compatible = "ti,mux-clock";
  800. clocks = <0x2a 0x26 0x27>;
  801. ti,bit-shift = <0x18>;
  802. reg = <0x550>;
  803. linux,phandle = <0xc3>;
  804. phandle = <0xc3>;
  805. };
  806.  
  807. mcbsp3_sync_mux_ck {
  808. #clock-cells = <0x0>;
  809. compatible = "ti,mux-clock";
  810. clocks = <0x22 0x23 0x24>;
  811. ti,bit-shift = <0x19>;
  812. reg = <0x558>;
  813. linux,phandle = <0x2b>;
  814. phandle = <0x2b>;
  815. };
  816.  
  817. func_mcbsp3_gfclk {
  818. #clock-cells = <0x0>;
  819. compatible = "ti,mux-clock";
  820. clocks = <0x2b 0x26 0x27>;
  821. ti,bit-shift = <0x18>;
  822. reg = <0x558>;
  823. linux,phandle = <0xc4>;
  824. phandle = <0xc4>;
  825. };
  826.  
  827. slimbus1_fclk_1 {
  828. #clock-cells = <0x0>;
  829. compatible = "ti,gate-clock";
  830. clocks = <0x24>;
  831. ti,bit-shift = <0x9>;
  832. reg = <0x560>;
  833. linux,phandle = <0xc5>;
  834. phandle = <0xc5>;
  835. };
  836.  
  837. slimbus1_fclk_0 {
  838. #clock-cells = <0x0>;
  839. compatible = "ti,gate-clock";
  840. clocks = <0x22>;
  841. ti,bit-shift = <0x8>;
  842. reg = <0x560>;
  843. linux,phandle = <0xc6>;
  844. phandle = <0xc6>;
  845. };
  846.  
  847. slimbus1_fclk_2 {
  848. #clock-cells = <0x0>;
  849. compatible = "ti,gate-clock";
  850. clocks = <0x26>;
  851. ti,bit-shift = <0xa>;
  852. reg = <0x560>;
  853. linux,phandle = <0xc7>;
  854. phandle = <0xc7>;
  855. };
  856.  
  857. slimbus1_slimbus_clk {
  858. #clock-cells = <0x0>;
  859. compatible = "ti,gate-clock";
  860. clocks = <0x27>;
  861. ti,bit-shift = <0xb>;
  862. reg = <0x560>;
  863. linux,phandle = <0xc8>;
  864. phandle = <0xc8>;
  865. };
  866.  
  867. timer5_sync_mux {
  868. #clock-cells = <0x0>;
  869. compatible = "ti,mux-clock";
  870. clocks = <0x23 0x2c>;
  871. ti,bit-shift = <0x18>;
  872. reg = <0x568>;
  873. linux,phandle = <0xc9>;
  874. phandle = <0xc9>;
  875. };
  876.  
  877. timer6_sync_mux {
  878. #clock-cells = <0x0>;
  879. compatible = "ti,mux-clock";
  880. clocks = <0x23 0x2c>;
  881. ti,bit-shift = <0x18>;
  882. reg = <0x570>;
  883. linux,phandle = <0xca>;
  884. phandle = <0xca>;
  885. };
  886.  
  887. timer7_sync_mux {
  888. #clock-cells = <0x0>;
  889. compatible = "ti,mux-clock";
  890. clocks = <0x23 0x2c>;
  891. ti,bit-shift = <0x18>;
  892. reg = <0x578>;
  893. linux,phandle = <0xcb>;
  894. phandle = <0xcb>;
  895. };
  896.  
  897. timer8_sync_mux {
  898. #clock-cells = <0x0>;
  899. compatible = "ti,mux-clock";
  900. clocks = <0x23 0x2c>;
  901. ti,bit-shift = <0x18>;
  902. reg = <0x580>;
  903. linux,phandle = <0xcc>;
  904. phandle = <0xcc>;
  905. };
  906.  
  907. dummy_ck {
  908. #clock-cells = <0x0>;
  909. compatible = "fixed-clock";
  910. clock-frequency = <0x0>;
  911. linux,phandle = <0xcd>;
  912. phandle = <0xcd>;
  913. };
  914. };
  915.  
  916. clockdomains {
  917. linux,phandle = <0xce>;
  918. phandle = <0xce>;
  919. };
  920. };
  921.  
  922. cm2@8000 {
  923. compatible = "ti,omap4-cm2";
  924. reg = <0x8000 0x3000>;
  925. linux,phandle = <0xcf>;
  926. phandle = <0xcf>;
  927.  
  928. clocks {
  929. #address-cells = <0x1>;
  930. #size-cells = <0x0>;
  931. linux,phandle = <0xd0>;
  932. phandle = <0xd0>;
  933.  
  934. per_hsd_byp_clk_mux_ck {
  935. #clock-cells = <0x0>;
  936. compatible = "ti,mux-clock";
  937. clocks = <0xf 0x2d>;
  938. ti,bit-shift = <0x17>;
  939. reg = <0x14c>;
  940. linux,phandle = <0x2e>;
  941. phandle = <0x2e>;
  942. };
  943.  
  944. dpll_per_ck {
  945. #clock-cells = <0x0>;
  946. compatible = "ti,omap4-dpll-clock";
  947. clocks = <0xf 0x2e>;
  948. reg = <0x140 0x144 0x14c 0x148>;
  949. linux,phandle = <0x2f>;
  950. phandle = <0x2f>;
  951. };
  952.  
  953. dpll_per_m2_ck {
  954. #clock-cells = <0x0>;
  955. compatible = "ti,divider-clock";
  956. clocks = <0x2f>;
  957. ti,max-div = <0x1f>;
  958. reg = <0x150>;
  959. ti,index-starts-at-one;
  960. linux,phandle = <0x37>;
  961. phandle = <0x37>;
  962. };
  963.  
  964. dpll_per_x2_ck {
  965. #clock-cells = <0x0>;
  966. compatible = "ti,omap4-dpll-x2-clock";
  967. clocks = <0x2f>;
  968. reg = <0x150>;
  969. linux,phandle = <0x30>;
  970. phandle = <0x30>;
  971. };
  972.  
  973. dpll_per_m2x2_ck {
  974. #clock-cells = <0x0>;
  975. compatible = "ti,divider-clock";
  976. clocks = <0x30>;
  977. ti,max-div = <0x1f>;
  978. ti,autoidle-shift = <0x8>;
  979. reg = <0x150>;
  980. ti,index-starts-at-one;
  981. ti,invert-autoidle-bit;
  982. linux,phandle = <0x36>;
  983. phandle = <0x36>;
  984. };
  985.  
  986. dpll_per_m3x2_gate_ck {
  987. #clock-cells = <0x0>;
  988. compatible = "ti,composite-no-wait-gate-clock";
  989. clocks = <0x30>;
  990. ti,bit-shift = <0x8>;
  991. reg = <0x154>;
  992. linux,phandle = <0x31>;
  993. phandle = <0x31>;
  994. };
  995.  
  996. dpll_per_m3x2_div_ck {
  997. #clock-cells = <0x0>;
  998. compatible = "ti,composite-divider-clock";
  999. clocks = <0x30>;
  1000. ti,max-div = <0x1f>;
  1001. reg = <0x154>;
  1002. ti,index-starts-at-one;
  1003. linux,phandle = <0x32>;
  1004. phandle = <0x32>;
  1005. };
  1006.  
  1007. dpll_per_m3x2_ck {
  1008. #clock-cells = <0x0>;
  1009. compatible = "ti,composite-clock";
  1010. clocks = <0x31 0x32>;
  1011. linux,phandle = <0x69>;
  1012. phandle = <0x69>;
  1013. };
  1014.  
  1015. dpll_per_m4x2_ck {
  1016. #clock-cells = <0x0>;
  1017. compatible = "ti,divider-clock";
  1018. clocks = <0x30>;
  1019. ti,max-div = <0x1f>;
  1020. ti,autoidle-shift = <0x8>;
  1021. reg = <0x158>;
  1022. ti,index-starts-at-one;
  1023. ti,invert-autoidle-bit;
  1024. linux,phandle = <0x38>;
  1025. phandle = <0x38>;
  1026. };
  1027.  
  1028. dpll_per_m5x2_ck {
  1029. #clock-cells = <0x0>;
  1030. compatible = "ti,divider-clock";
  1031. clocks = <0x30>;
  1032. ti,max-div = <0x1f>;
  1033. ti,autoidle-shift = <0x8>;
  1034. reg = <0x15c>;
  1035. ti,index-starts-at-one;
  1036. ti,invert-autoidle-bit;
  1037. linux,phandle = <0x3b>;
  1038. phandle = <0x3b>;
  1039. };
  1040.  
  1041. dpll_per_m6x2_ck {
  1042. #clock-cells = <0x0>;
  1043. compatible = "ti,divider-clock";
  1044. clocks = <0x30>;
  1045. ti,max-div = <0x1f>;
  1046. ti,autoidle-shift = <0x8>;
  1047. reg = <0x160>;
  1048. ti,index-starts-at-one;
  1049. ti,invert-autoidle-bit;
  1050. linux,phandle = <0x35>;
  1051. phandle = <0x35>;
  1052. };
  1053.  
  1054. dpll_per_m7x2_ck {
  1055. #clock-cells = <0x0>;
  1056. compatible = "ti,divider-clock";
  1057. clocks = <0x30>;
  1058. ti,max-div = <0x1f>;
  1059. ti,autoidle-shift = <0x8>;
  1060. reg = <0x164>;
  1061. ti,index-starts-at-one;
  1062. ti,invert-autoidle-bit;
  1063. linux,phandle = <0x3e>;
  1064. phandle = <0x3e>;
  1065. };
  1066.  
  1067. dpll_usb_ck {
  1068. #clock-cells = <0x0>;
  1069. compatible = "ti,omap4-dpll-j-type-clock";
  1070. clocks = <0xf 0x33>;
  1071. reg = <0x180 0x184 0x18c 0x188>;
  1072. linux,phandle = <0x34>;
  1073. phandle = <0x34>;
  1074. };
  1075.  
  1076. dpll_usb_clkdcoldo_ck {
  1077. #clock-cells = <0x0>;
  1078. compatible = "ti,fixed-factor-clock";
  1079. clocks = <0x34>;
  1080. ti,clock-div = <0x1>;
  1081. ti,autoidle-shift = <0x8>;
  1082. reg = <0x1b4>;
  1083. ti,clock-mult = <0x1>;
  1084. ti,invert-autoidle-bit;
  1085. linux,phandle = <0xd1>;
  1086. phandle = <0xd1>;
  1087. };
  1088.  
  1089. dpll_usb_m2_ck {
  1090. #clock-cells = <0x0>;
  1091. compatible = "ti,divider-clock";
  1092. clocks = <0x34>;
  1093. ti,max-div = <0x7f>;
  1094. ti,autoidle-shift = <0x8>;
  1095. reg = <0x190>;
  1096. ti,index-starts-at-one;
  1097. ti,invert-autoidle-bit;
  1098. linux,phandle = <0x39>;
  1099. phandle = <0x39>;
  1100. };
  1101.  
  1102. ducati_clk_mux_ck {
  1103. #clock-cells = <0x0>;
  1104. compatible = "ti,mux-clock";
  1105. clocks = <0x1e 0x35>;
  1106. reg = <0x100>;
  1107. linux,phandle = <0xd2>;
  1108. phandle = <0xd2>;
  1109. };
  1110.  
  1111. func_12m_fclk {
  1112. #clock-cells = <0x0>;
  1113. compatible = "fixed-factor-clock";
  1114. clocks = <0x36>;
  1115. clock-mult = <0x1>;
  1116. clock-div = <0x10>;
  1117. linux,phandle = <0xd3>;
  1118. phandle = <0xd3>;
  1119. };
  1120.  
  1121. func_24m_clk {
  1122. #clock-cells = <0x0>;
  1123. compatible = "fixed-factor-clock";
  1124. clocks = <0x37>;
  1125. clock-mult = <0x1>;
  1126. clock-div = <0x4>;
  1127. linux,phandle = <0x24>;
  1128. phandle = <0x24>;
  1129. };
  1130.  
  1131. func_24mc_fclk {
  1132. #clock-cells = <0x0>;
  1133. compatible = "fixed-factor-clock";
  1134. clocks = <0x36>;
  1135. clock-mult = <0x1>;
  1136. clock-div = <0x8>;
  1137. linux,phandle = <0x45>;
  1138. phandle = <0x45>;
  1139. };
  1140.  
  1141. func_48m_fclk {
  1142. #clock-cells = <0x0>;
  1143. compatible = "ti,divider-clock";
  1144. clocks = <0x36>;
  1145. reg = <0x108>;
  1146. ti,dividers = <0x4 0x8>;
  1147. linux,phandle = <0x43>;
  1148. phandle = <0x43>;
  1149. };
  1150.  
  1151. func_48mc_fclk {
  1152. #clock-cells = <0x0>;
  1153. compatible = "fixed-factor-clock";
  1154. clocks = <0x36>;
  1155. clock-mult = <0x1>;
  1156. clock-div = <0x4>;
  1157. linux,phandle = <0x3c>;
  1158. phandle = <0x3c>;
  1159. };
  1160.  
  1161. func_64m_fclk {
  1162. #clock-cells = <0x0>;
  1163. compatible = "ti,divider-clock";
  1164. clocks = <0x38>;
  1165. reg = <0x108>;
  1166. ti,dividers = <0x2 0x4>;
  1167. linux,phandle = <0x42>;
  1168. phandle = <0x42>;
  1169. };
  1170.  
  1171. func_96m_fclk {
  1172. #clock-cells = <0x0>;
  1173. compatible = "ti,divider-clock";
  1174. clocks = <0x36>;
  1175. reg = <0x108>;
  1176. ti,dividers = <0x2 0x4>;
  1177. linux,phandle = <0x3f>;
  1178. phandle = <0x3f>;
  1179. };
  1180.  
  1181. init_60m_fclk {
  1182. #clock-cells = <0x0>;
  1183. compatible = "ti,divider-clock";
  1184. clocks = <0x39>;
  1185. reg = <0x104>;
  1186. ti,dividers = <0x1 0x8>;
  1187. linux,phandle = <0x48>;
  1188. phandle = <0x48>;
  1189. };
  1190.  
  1191. per_abe_nc_fclk {
  1192. #clock-cells = <0x0>;
  1193. compatible = "ti,divider-clock";
  1194. clocks = <0x21>;
  1195. reg = <0x108>;
  1196. ti,max-div = <0x2>;
  1197. linux,phandle = <0x40>;
  1198. phandle = <0x40>;
  1199. };
  1200.  
  1201. aes1_fck {
  1202. #clock-cells = <0x0>;
  1203. compatible = "ti,gate-clock";
  1204. clocks = <0x1f>;
  1205. ti,bit-shift = <0x1>;
  1206. reg = <0x15a0>;
  1207. linux,phandle = <0xd4>;
  1208. phandle = <0xd4>;
  1209. };
  1210.  
  1211. aes2_fck {
  1212. #clock-cells = <0x0>;
  1213. compatible = "ti,gate-clock";
  1214. clocks = <0x1f>;
  1215. ti,bit-shift = <0x1>;
  1216. reg = <0x15a8>;
  1217. linux,phandle = <0xd5>;
  1218. phandle = <0xd5>;
  1219. };
  1220.  
  1221. dss_sys_clk {
  1222. #clock-cells = <0x0>;
  1223. compatible = "ti,gate-clock";
  1224. clocks = <0x23>;
  1225. ti,bit-shift = <0xa>;
  1226. reg = <0x1120>;
  1227. linux,phandle = <0x9e>;
  1228. phandle = <0x9e>;
  1229. };
  1230.  
  1231. dss_tv_clk {
  1232. #clock-cells = <0x0>;
  1233. compatible = "ti,gate-clock";
  1234. clocks = <0x3a>;
  1235. ti,bit-shift = <0xb>;
  1236. reg = <0x1120>;
  1237. linux,phandle = <0x9d>;
  1238. phandle = <0x9d>;
  1239. };
  1240.  
  1241. dss_dss_clk {
  1242. #clock-cells = <0x0>;
  1243. compatible = "ti,gate-clock";
  1244. clocks = <0x3b>;
  1245. ti,bit-shift = <0x8>;
  1246. reg = <0x1120>;
  1247. ti,set-rate-parent;
  1248. linux,phandle = <0x9c>;
  1249. phandle = <0x9c>;
  1250. };
  1251.  
  1252. dss_48mhz_clk {
  1253. #clock-cells = <0x0>;
  1254. compatible = "ti,gate-clock";
  1255. clocks = <0x3c>;
  1256. ti,bit-shift = <0x9>;
  1257. reg = <0x1120>;
  1258. linux,phandle = <0xa0>;
  1259. phandle = <0xa0>;
  1260. };
  1261.  
  1262. fdif_fck {
  1263. #clock-cells = <0x0>;
  1264. compatible = "ti,divider-clock";
  1265. clocks = <0x38>;
  1266. ti,bit-shift = <0x18>;
  1267. ti,max-div = <0x4>;
  1268. reg = <0x1028>;
  1269. ti,index-power-of-two;
  1270. linux,phandle = <0xd6>;
  1271. phandle = <0xd6>;
  1272. };
  1273.  
  1274. gpio2_dbclk {
  1275. #clock-cells = <0x0>;
  1276. compatible = "ti,gate-clock";
  1277. clocks = <0x2c>;
  1278. ti,bit-shift = <0x8>;
  1279. reg = <0x1460>;
  1280. linux,phandle = <0xd7>;
  1281. phandle = <0xd7>;
  1282. };
  1283.  
  1284. gpio3_dbclk {
  1285. #clock-cells = <0x0>;
  1286. compatible = "ti,gate-clock";
  1287. clocks = <0x2c>;
  1288. ti,bit-shift = <0x8>;
  1289. reg = <0x1468>;
  1290. linux,phandle = <0xd8>;
  1291. phandle = <0xd8>;
  1292. };
  1293.  
  1294. gpio4_dbclk {
  1295. #clock-cells = <0x0>;
  1296. compatible = "ti,gate-clock";
  1297. clocks = <0x2c>;
  1298. ti,bit-shift = <0x8>;
  1299. reg = <0x1470>;
  1300. linux,phandle = <0xd9>;
  1301. phandle = <0xd9>;
  1302. };
  1303.  
  1304. gpio5_dbclk {
  1305. #clock-cells = <0x0>;
  1306. compatible = "ti,gate-clock";
  1307. clocks = <0x2c>;
  1308. ti,bit-shift = <0x8>;
  1309. reg = <0x1478>;
  1310. linux,phandle = <0xda>;
  1311. phandle = <0xda>;
  1312. };
  1313.  
  1314. gpio6_dbclk {
  1315. #clock-cells = <0x0>;
  1316. compatible = "ti,gate-clock";
  1317. clocks = <0x2c>;
  1318. ti,bit-shift = <0x8>;
  1319. reg = <0x1480>;
  1320. linux,phandle = <0xdb>;
  1321. phandle = <0xdb>;
  1322. };
  1323.  
  1324. sgx_clk_mux {
  1325. #clock-cells = <0x0>;
  1326. compatible = "ti,mux-clock";
  1327. clocks = <0x3d 0x3e>;
  1328. ti,bit-shift = <0x18>;
  1329. reg = <0x1220>;
  1330. linux,phandle = <0xdc>;
  1331. phandle = <0xdc>;
  1332. };
  1333.  
  1334. hsi_fck {
  1335. #clock-cells = <0x0>;
  1336. compatible = "ti,divider-clock";
  1337. clocks = <0x36>;
  1338. ti,bit-shift = <0x18>;
  1339. ti,max-div = <0x4>;
  1340. reg = <0x1338>;
  1341. ti,index-power-of-two;
  1342. linux,phandle = <0xdd>;
  1343. phandle = <0xdd>;
  1344. };
  1345.  
  1346. iss_ctrlclk {
  1347. #clock-cells = <0x0>;
  1348. compatible = "ti,gate-clock";
  1349. clocks = <0x3f>;
  1350. ti,bit-shift = <0x8>;
  1351. reg = <0x1020>;
  1352. linux,phandle = <0xde>;
  1353. phandle = <0xde>;
  1354. };
  1355.  
  1356. mcbsp4_sync_mux_ck {
  1357. #clock-cells = <0x0>;
  1358. compatible = "ti,mux-clock";
  1359. clocks = <0x3f 0x40>;
  1360. ti,bit-shift = <0x19>;
  1361. reg = <0x14e0>;
  1362. linux,phandle = <0x41>;
  1363. phandle = <0x41>;
  1364. };
  1365.  
  1366. per_mcbsp4_gfclk {
  1367. #clock-cells = <0x0>;
  1368. compatible = "ti,mux-clock";
  1369. clocks = <0x41 0x26>;
  1370. ti,bit-shift = <0x18>;
  1371. reg = <0x14e0>;
  1372. linux,phandle = <0xdf>;
  1373. phandle = <0xdf>;
  1374. };
  1375.  
  1376. hsmmc1_fclk {
  1377. #clock-cells = <0x0>;
  1378. compatible = "ti,mux-clock";
  1379. clocks = <0x42 0x3f>;
  1380. ti,bit-shift = <0x18>;
  1381. reg = <0x1328>;
  1382. linux,phandle = <0xe0>;
  1383. phandle = <0xe0>;
  1384. };
  1385.  
  1386. hsmmc2_fclk {
  1387. #clock-cells = <0x0>;
  1388. compatible = "ti,mux-clock";
  1389. clocks = <0x42 0x3f>;
  1390. ti,bit-shift = <0x18>;
  1391. reg = <0x1330>;
  1392. linux,phandle = <0xe1>;
  1393. phandle = <0xe1>;
  1394. };
  1395.  
  1396. ocp2scp_usb_phy_phy_48m {
  1397. #clock-cells = <0x0>;
  1398. compatible = "ti,gate-clock";
  1399. clocks = <0x43>;
  1400. ti,bit-shift = <0x8>;
  1401. reg = <0x13e0>;
  1402. linux,phandle = <0xe2>;
  1403. phandle = <0xe2>;
  1404. };
  1405.  
  1406. sha2md5_fck {
  1407. #clock-cells = <0x0>;
  1408. compatible = "ti,gate-clock";
  1409. clocks = <0x1f>;
  1410. ti,bit-shift = <0x1>;
  1411. reg = <0x15c8>;
  1412. linux,phandle = <0xe3>;
  1413. phandle = <0xe3>;
  1414. };
  1415.  
  1416. slimbus2_fclk_1 {
  1417. #clock-cells = <0x0>;
  1418. compatible = "ti,gate-clock";
  1419. clocks = <0x44>;
  1420. ti,bit-shift = <0x9>;
  1421. reg = <0x1538>;
  1422. linux,phandle = <0xe4>;
  1423. phandle = <0xe4>;
  1424. };
  1425.  
  1426. slimbus2_fclk_0 {
  1427. #clock-cells = <0x0>;
  1428. compatible = "ti,gate-clock";
  1429. clocks = <0x45>;
  1430. ti,bit-shift = <0x8>;
  1431. reg = <0x1538>;
  1432. linux,phandle = <0xe5>;
  1433. phandle = <0xe5>;
  1434. };
  1435.  
  1436. slimbus2_slimbus_clk {
  1437. #clock-cells = <0x0>;
  1438. compatible = "ti,gate-clock";
  1439. clocks = <0x46>;
  1440. ti,bit-shift = <0xa>;
  1441. reg = <0x1538>;
  1442. linux,phandle = <0xe6>;
  1443. phandle = <0xe6>;
  1444. };
  1445.  
  1446. smartreflex_core_fck {
  1447. #clock-cells = <0x0>;
  1448. compatible = "ti,gate-clock";
  1449. clocks = <0x47>;
  1450. ti,bit-shift = <0x1>;
  1451. reg = <0x638>;
  1452. linux,phandle = <0xe7>;
  1453. phandle = <0xe7>;
  1454. };
  1455.  
  1456. smartreflex_iva_fck {
  1457. #clock-cells = <0x0>;
  1458. compatible = "ti,gate-clock";
  1459. clocks = <0x47>;
  1460. ti,bit-shift = <0x1>;
  1461. reg = <0x630>;
  1462. linux,phandle = <0xe8>;
  1463. phandle = <0xe8>;
  1464. };
  1465.  
  1466. smartreflex_mpu_fck {
  1467. #clock-cells = <0x0>;
  1468. compatible = "ti,gate-clock";
  1469. clocks = <0x47>;
  1470. ti,bit-shift = <0x1>;
  1471. reg = <0x628>;
  1472. linux,phandle = <0xe9>;
  1473. phandle = <0xe9>;
  1474. };
  1475.  
  1476. cm2_dm10_mux {
  1477. #clock-cells = <0x0>;
  1478. compatible = "ti,mux-clock";
  1479. clocks = <0xf 0x2c>;
  1480. ti,bit-shift = <0x18>;
  1481. reg = <0x1428>;
  1482. linux,phandle = <0xea>;
  1483. phandle = <0xea>;
  1484. };
  1485.  
  1486. cm2_dm11_mux {
  1487. #clock-cells = <0x0>;
  1488. compatible = "ti,mux-clock";
  1489. clocks = <0xf 0x2c>;
  1490. ti,bit-shift = <0x18>;
  1491. reg = <0x1430>;
  1492. linux,phandle = <0xeb>;
  1493. phandle = <0xeb>;
  1494. };
  1495.  
  1496. cm2_dm2_mux {
  1497. #clock-cells = <0x0>;
  1498. compatible = "ti,mux-clock";
  1499. clocks = <0xf 0x2c>;
  1500. ti,bit-shift = <0x18>;
  1501. reg = <0x1438>;
  1502. linux,phandle = <0xec>;
  1503. phandle = <0xec>;
  1504. };
  1505.  
  1506. cm2_dm3_mux {
  1507. #clock-cells = <0x0>;
  1508. compatible = "ti,mux-clock";
  1509. clocks = <0xf 0x2c>;
  1510. ti,bit-shift = <0x18>;
  1511. reg = <0x1440>;
  1512. linux,phandle = <0xed>;
  1513. phandle = <0xed>;
  1514. };
  1515.  
  1516. cm2_dm4_mux {
  1517. #clock-cells = <0x0>;
  1518. compatible = "ti,mux-clock";
  1519. clocks = <0xf 0x2c>;
  1520. ti,bit-shift = <0x18>;
  1521. reg = <0x1448>;
  1522. linux,phandle = <0xee>;
  1523. phandle = <0xee>;
  1524. };
  1525.  
  1526. cm2_dm9_mux {
  1527. #clock-cells = <0x0>;
  1528. compatible = "ti,mux-clock";
  1529. clocks = <0xf 0x2c>;
  1530. ti,bit-shift = <0x18>;
  1531. reg = <0x1450>;
  1532. linux,phandle = <0xef>;
  1533. phandle = <0xef>;
  1534. };
  1535.  
  1536. usb_host_fs_fck {
  1537. #clock-cells = <0x0>;
  1538. compatible = "ti,gate-clock";
  1539. clocks = <0x3c>;
  1540. ti,bit-shift = <0x1>;
  1541. reg = <0x13d0>;
  1542. linux,phandle = <0x51>;
  1543. phandle = <0x51>;
  1544. };
  1545.  
  1546. utmi_p1_gfclk {
  1547. #clock-cells = <0x0>;
  1548. compatible = "ti,mux-clock";
  1549. clocks = <0x48 0x49>;
  1550. ti,bit-shift = <0x18>;
  1551. reg = <0x1358>;
  1552. linux,phandle = <0x4a>;
  1553. phandle = <0x4a>;
  1554. };
  1555.  
  1556. usb_host_hs_utmi_p1_clk {
  1557. #clock-cells = <0x0>;
  1558. compatible = "ti,gate-clock";
  1559. clocks = <0x4a>;
  1560. ti,bit-shift = <0x8>;
  1561. reg = <0x1358>;
  1562. linux,phandle = <0xf0>;
  1563. phandle = <0xf0>;
  1564. };
  1565.  
  1566. utmi_p2_gfclk {
  1567. #clock-cells = <0x0>;
  1568. compatible = "ti,mux-clock";
  1569. clocks = <0x48 0x4b>;
  1570. ti,bit-shift = <0x19>;
  1571. reg = <0x1358>;
  1572. linux,phandle = <0x4c>;
  1573. phandle = <0x4c>;
  1574. };
  1575.  
  1576. usb_host_hs_utmi_p2_clk {
  1577. #clock-cells = <0x0>;
  1578. compatible = "ti,gate-clock";
  1579. clocks = <0x4c>;
  1580. ti,bit-shift = <0x9>;
  1581. reg = <0x1358>;
  1582. linux,phandle = <0xf1>;
  1583. phandle = <0xf1>;
  1584. };
  1585.  
  1586. usb_host_hs_utmi_p3_clk {
  1587. #clock-cells = <0x0>;
  1588. compatible = "ti,gate-clock";
  1589. clocks = <0x48>;
  1590. ti,bit-shift = <0xa>;
  1591. reg = <0x1358>;
  1592. linux,phandle = <0xf2>;
  1593. phandle = <0xf2>;
  1594. };
  1595.  
  1596. usb_host_hs_hsic480m_p1_clk {
  1597. #clock-cells = <0x0>;
  1598. compatible = "ti,gate-clock";
  1599. clocks = <0x39>;
  1600. ti,bit-shift = <0xd>;
  1601. reg = <0x1358>;
  1602. linux,phandle = <0xf3>;
  1603. phandle = <0xf3>;
  1604. };
  1605.  
  1606. usb_host_hs_hsic60m_p1_clk {
  1607. #clock-cells = <0x0>;
  1608. compatible = "ti,gate-clock";
  1609. clocks = <0x48>;
  1610. ti,bit-shift = <0xb>;
  1611. reg = <0x1358>;
  1612. linux,phandle = <0xf4>;
  1613. phandle = <0xf4>;
  1614. };
  1615.  
  1616. usb_host_hs_hsic60m_p2_clk {
  1617. #clock-cells = <0x0>;
  1618. compatible = "ti,gate-clock";
  1619. clocks = <0x48>;
  1620. ti,bit-shift = <0xc>;
  1621. reg = <0x1358>;
  1622. linux,phandle = <0xf5>;
  1623. phandle = <0xf5>;
  1624. };
  1625.  
  1626. usb_host_hs_hsic480m_p2_clk {
  1627. #clock-cells = <0x0>;
  1628. compatible = "ti,gate-clock";
  1629. clocks = <0x39>;
  1630. ti,bit-shift = <0xe>;
  1631. reg = <0x1358>;
  1632. linux,phandle = <0xf6>;
  1633. phandle = <0xf6>;
  1634. };
  1635.  
  1636. usb_host_hs_func48mclk {
  1637. #clock-cells = <0x0>;
  1638. compatible = "ti,gate-clock";
  1639. clocks = <0x3c>;
  1640. ti,bit-shift = <0xf>;
  1641. reg = <0x1358>;
  1642. linux,phandle = <0xf7>;
  1643. phandle = <0xf7>;
  1644. };
  1645.  
  1646. usb_host_hs_fck {
  1647. #clock-cells = <0x0>;
  1648. compatible = "ti,gate-clock";
  1649. clocks = <0x48>;
  1650. ti,bit-shift = <0x1>;
  1651. reg = <0x1358>;
  1652. linux,phandle = <0xf8>;
  1653. phandle = <0xf8>;
  1654. };
  1655.  
  1656. otg_60m_gfclk {
  1657. #clock-cells = <0x0>;
  1658. compatible = "ti,mux-clock";
  1659. clocks = <0x4d 0x4e>;
  1660. ti,bit-shift = <0x18>;
  1661. reg = <0x1360>;
  1662. linux,phandle = <0x4f>;
  1663. phandle = <0x4f>;
  1664. };
  1665.  
  1666. usb_otg_hs_xclk {
  1667. #clock-cells = <0x0>;
  1668. compatible = "ti,gate-clock";
  1669. clocks = <0x4f>;
  1670. ti,bit-shift = <0x8>;
  1671. reg = <0x1360>;
  1672. linux,phandle = <0xf9>;
  1673. phandle = <0xf9>;
  1674. };
  1675.  
  1676. usb_otg_hs_ick {
  1677. #clock-cells = <0x0>;
  1678. compatible = "ti,gate-clock";
  1679. clocks = <0x1f>;
  1680. ti,bit-shift = <0x0>;
  1681. reg = <0x1360>;
  1682. linux,phandle = <0xfa>;
  1683. phandle = <0xfa>;
  1684. };
  1685.  
  1686. usb_phy_cm_clk32k {
  1687. #clock-cells = <0x0>;
  1688. compatible = "ti,gate-clock";
  1689. clocks = <0x2c>;
  1690. ti,bit-shift = <0x8>;
  1691. reg = <0x640>;
  1692. linux,phandle = <0x98>;
  1693. phandle = <0x98>;
  1694. };
  1695.  
  1696. usb_tll_hs_usb_ch2_clk {
  1697. #clock-cells = <0x0>;
  1698. compatible = "ti,gate-clock";
  1699. clocks = <0x48>;
  1700. ti,bit-shift = <0xa>;
  1701. reg = <0x1368>;
  1702. linux,phandle = <0xfb>;
  1703. phandle = <0xfb>;
  1704. };
  1705.  
  1706. usb_tll_hs_usb_ch0_clk {
  1707. #clock-cells = <0x0>;
  1708. compatible = "ti,gate-clock";
  1709. clocks = <0x48>;
  1710. ti,bit-shift = <0x8>;
  1711. reg = <0x1368>;
  1712. linux,phandle = <0xfc>;
  1713. phandle = <0xfc>;
  1714. };
  1715.  
  1716. usb_tll_hs_usb_ch1_clk {
  1717. #clock-cells = <0x0>;
  1718. compatible = "ti,gate-clock";
  1719. clocks = <0x48>;
  1720. ti,bit-shift = <0x9>;
  1721. reg = <0x1368>;
  1722. linux,phandle = <0xfd>;
  1723. phandle = <0xfd>;
  1724. };
  1725.  
  1726. usb_tll_hs_ick {
  1727. #clock-cells = <0x0>;
  1728. compatible = "ti,gate-clock";
  1729. clocks = <0x50>;
  1730. ti,bit-shift = <0x0>;
  1731. reg = <0x1368>;
  1732. linux,phandle = <0xfe>;
  1733. phandle = <0xfe>;
  1734. };
  1735. };
  1736.  
  1737. clockdomains {
  1738. linux,phandle = <0xff>;
  1739. phandle = <0xff>;
  1740.  
  1741. l3_init_clkdm {
  1742. compatible = "ti,clockdomain";
  1743. clocks = <0x34 0x51>;
  1744. linux,phandle = <0x100>;
  1745. phandle = <0x100>;
  1746. };
  1747. };
  1748. };
  1749.  
  1750. scm@2000 {
  1751. compatible = "ti,omap4-scm-core", "simple-bus";
  1752. reg = <0x2000 0x1000>;
  1753. #address-cells = <0x1>;
  1754. #size-cells = <0x1>;
  1755. ranges = <0x0 0x2000 0x1000>;
  1756. linux,phandle = <0x101>;
  1757. phandle = <0x101>;
  1758.  
  1759. scm_conf@0 {
  1760. compatible = "syscon";
  1761. reg = <0x0 0x800>;
  1762. #address-cells = <0x1>;
  1763. #size-cells = <0x1>;
  1764. linux,phandle = <0x102>;
  1765. phandle = <0x102>;
  1766. };
  1767. };
  1768.  
  1769. scm@100000 {
  1770. compatible = "ti,omap4-scm-padconf-core", "simple-bus";
  1771. #address-cells = <0x1>;
  1772. #size-cells = <0x1>;
  1773. ranges = <0x0 0x100000 0x1000>;
  1774. linux,phandle = <0x103>;
  1775. phandle = <0x103>;
  1776.  
  1777. pinmux@40 {
  1778. compatible = "ti,omap4-padconf", "pinctrl-single";
  1779. reg = <0x40 0x196>;
  1780. #address-cells = <0x1>;
  1781. #size-cells = <0x0>;
  1782. #interrupt-cells = <0x1>;
  1783. interrupt-controller;
  1784. pinctrl-single,register-width = <0x10>;
  1785. pinctrl-single,function-mask = <0x7fff>;
  1786. pinctrl-names = "default";
  1787. pinctrl-0 = <0x52 0x53 0x54 0x55 0x56>;
  1788. linux,phandle = <0x82>;
  1789. phandle = <0x82>;
  1790.  
  1791. pinmux_twl6040_pins {
  1792. pinctrl-single,pins = <0xe0 0x3 0x160 0x100>;
  1793. linux,phandle = <0x87>;
  1794. phandle = <0x87>;
  1795. };
  1796.  
  1797. pinmux_mcpdm_pins {
  1798. pinctrl-single,pins = <0xc6 0x108 0xc8 0x108 0xca 0x118 0xcc 0x108 0xce 0x108>;
  1799. linux,phandle = <0x94>;
  1800. phandle = <0x94>;
  1801. };
  1802.  
  1803. pinmux_mcbsp1_pins {
  1804. pinctrl-single,pins = <0xbe 0x100 0xc0 0x108 0xc2 0x8 0xc4 0x100>;
  1805. linux,phandle = <0x95>;
  1806. phandle = <0x95>;
  1807. };
  1808.  
  1809. pinmux_dss_dpi_pins {
  1810. pinctrl-single,pins = <0x122 0x5 0x124 0x5 0x126 0x5 0x128 0x5 0x12a 0x5 0x12c 0x5 0x12e 0x5 0x130 0x5 0x132 0x5 0x134 0x5 0x136 0x5 0x174 0x5 0x176 0x5 0x178 0x5 0x17a 0x5 0x17c 0x5 0x17e 0x5 0x180 0x5 0x182 0x5 0x184 0x5 0x186 0x5 0x188 0x5 0x18a 0x5 0x18c 0x5 0x18e 0x5 0x190 0x5 0x192 0x5 0x194 0x5>;
  1811. linux,phandle = <0x52>;
  1812. phandle = <0x52>;
  1813. };
  1814.  
  1815. pinmux_tfp410_pins {
  1816. pinctrl-single,pins = <0x144 0x3>;
  1817. linux,phandle = <0x53>;
  1818. phandle = <0x53>;
  1819. };
  1820.  
  1821. pinmux_dss_hdmi_pins {
  1822. pinctrl-single,pins = <0x5a 0x118 0x5c 0x100 0x5e 0x100>;
  1823. linux,phandle = <0x54>;
  1824. phandle = <0x54>;
  1825. };
  1826.  
  1827. pinmux_tpd12s015_pins {
  1828. pinctrl-single,pins = <0x22 0x3 0x48 0x3 0x58 0x10b>;
  1829. linux,phandle = <0x55>;
  1830. phandle = <0x55>;
  1831. };
  1832.  
  1833. pinmux_hsusbb1_pins {
  1834. pinctrl-single,pins = <0x82 0x10c 0x84 0x4 0x86 0x10c 0x88 0x10c 0x8a 0x10c 0x8c 0x10c 0x8e 0x10c 0x90 0x10c 0x92 0x10c 0x94 0x10c 0x96 0x10c 0x98 0x10c>;
  1835. linux,phandle = <0x56>;
  1836. phandle = <0x56>;
  1837. };
  1838.  
  1839. pinmux_i2c1_pins {
  1840. pinctrl-single,pins = <0xe2 0x118 0xe4 0x118>;
  1841. linux,phandle = <0x83>;
  1842. phandle = <0x83>;
  1843. };
  1844.  
  1845. pinmux_i2c2_pins {
  1846. pinctrl-single,pins = <0xe6 0x118 0xe8 0x118>;
  1847. linux,phandle = <0x8b>;
  1848. phandle = <0x8b>;
  1849. };
  1850.  
  1851. pinmux_i2c3_pins {
  1852. pinctrl-single,pins = <0xea 0x118 0xec 0x118>;
  1853. linux,phandle = <0x8c>;
  1854. phandle = <0x8c>;
  1855. };
  1856.  
  1857. pinmux_i2c4_pins {
  1858. pinctrl-single,pins = <0xee 0x118 0xf0 0x118>;
  1859. linux,phandle = <0x8d>;
  1860. phandle = <0x8d>;
  1861. };
  1862.  
  1863. pinmux_wl12xx_gpio {
  1864. pinctrl-single,pins = <0x26 0x3 0x2c 0x3 0x30 0x1b 0x32 0x1b>;
  1865. linux,phandle = <0xae>;
  1866. phandle = <0xae>;
  1867. };
  1868.  
  1869. pinmux_wl12xx_pins {
  1870. pinctrl-single,pins = <0x38 0x103 0x3a 0x103 0x108 0x118 0x10a 0x118 0x10c 0x118 0x10e 0x118 0x110 0x118 0x112 0x118>;
  1871. linux,phandle = <0x91>;
  1872. phandle = <0x91>;
  1873. };
  1874.  
  1875. pinmux_twl6030_pins {
  1876. pinctrl-single,pins = <0x15e 0x4118>;
  1877. linux,phandle = <0x84>;
  1878. phandle = <0x84>;
  1879. };
  1880.  
  1881. // Set the UART4 MUX, it doesn't come by default so I had to add it
  1882. // "linux,phandle" has the same value aas "phandle", it's just a reference number, just make sure
  1883. // it is not being used in another part of the tree (it will refuse to compile if you do it wrong)
  1884. // The phandle is used for reference in "serial@4806e000" at "pinctrl-0"
  1885. pinmux_uart4_pins {
  1886. pinctrl-single,pins = <
  1887. 0x11c 0x100 // uart4_rx.uart4_rx INPUT | MODE0
  1888. 0x11e 0 // uart4_tx.uart4_tx OUTPUT | MODE0
  1889. >;
  1890. linux,phandle = <0xfff>;
  1891. phandle = <0xfff>;
  1892. };
  1893.  
  1894. gpio_led_pmx {
  1895. pinctrl-single,pins = <0xb6 0x3>;
  1896. linux,phandle = <0xa8>;
  1897. phandle = <0xa8>;
  1898. };
  1899. };
  1900.  
  1901. omap4_padconf_global@5a0 {
  1902. compatible = "syscon", "simple-bus";
  1903. reg = <0x5a0 0x170>;
  1904. #address-cells = <0x1>;
  1905. #size-cells = <0x1>;
  1906. linux,phandle = <0x57>;
  1907. phandle = <0x57>;
  1908.  
  1909. pbias_regulator {
  1910. compatible = "ti,pbias-omap";
  1911. reg = <0x60 0x4>;
  1912. syscon = <0x57>;
  1913. linux,phandle = <0x104>;
  1914. phandle = <0x104>;
  1915.  
  1916. pbias_mmc_omap4 {
  1917. regulator-name = "pbias_mmc_omap4";
  1918. regulator-min-microvolt = <0x1b7740>;
  1919. regulator-max-microvolt = <0x2dc6c0>;
  1920. linux,phandle = <0x8f>;
  1921. phandle = <0x8f>;
  1922. };
  1923. };
  1924. };
  1925. };
  1926.  
  1927. l4@300000 {
  1928. compatible = "ti,omap4-l4-wkup", "simple-bus";
  1929. #address-cells = <0x1>;
  1930. #size-cells = <0x1>;
  1931. ranges = <0x0 0x300000 0x40000>;
  1932. linux,phandle = <0x105>;
  1933. phandle = <0x105>;
  1934.  
  1935. counter@4000 {
  1936. compatible = "ti,omap-counter32k";
  1937. reg = <0x4000 0x20>;
  1938. ti,hwmods = "counter_32k";
  1939. linux,phandle = <0x106>;
  1940. phandle = <0x106>;
  1941. };
  1942.  
  1943. prm@6000 {
  1944. compatible = "ti,omap4-prm";
  1945. reg = <0x6000 0x3000>;
  1946. interrupts = <0x0 0xb 0x4>;
  1947. linux,phandle = <0x107>;
  1948. phandle = <0x107>;
  1949.  
  1950. clocks {
  1951. #address-cells = <0x1>;
  1952. #size-cells = <0x0>;
  1953. linux,phandle = <0x108>;
  1954. phandle = <0x108>;
  1955.  
  1956. sys_clkin_ck {
  1957. #clock-cells = <0x0>;
  1958. compatible = "ti,mux-clock";
  1959. clocks = <0x58 0x59 0x5a 0x5b 0x5c 0x5d 0x5e>;
  1960. reg = <0x110>;
  1961. ti,index-starts-at-one;
  1962. linux,phandle = <0xf>;
  1963. phandle = <0xf>;
  1964. };
  1965.  
  1966. abe_dpll_bypass_clk_mux_ck {
  1967. #clock-cells = <0x0>;
  1968. compatible = "ti,mux-clock";
  1969. clocks = <0xf 0x2c>;
  1970. ti,bit-shift = <0x18>;
  1971. reg = <0x108>;
  1972. linux,phandle = <0xa>;
  1973. phandle = <0xa>;
  1974. };
  1975.  
  1976. abe_dpll_refclk_mux_ck {
  1977. #clock-cells = <0x0>;
  1978. compatible = "ti,mux-clock";
  1979. clocks = <0xf 0x2c>;
  1980. reg = <0x10c>;
  1981. linux,phandle = <0x9>;
  1982. phandle = <0x9>;
  1983. };
  1984.  
  1985. dbgclk_mux_ck {
  1986. #clock-cells = <0x0>;
  1987. compatible = "fixed-factor-clock";
  1988. clocks = <0xf>;
  1989. clock-mult = <0x1>;
  1990. clock-div = <0x1>;
  1991. linux,phandle = <0x109>;
  1992. phandle = <0x109>;
  1993. };
  1994.  
  1995. l4_wkup_clk_mux_ck {
  1996. #clock-cells = <0x0>;
  1997. compatible = "ti,mux-clock";
  1998. clocks = <0xf 0x5f>;
  1999. reg = <0x108>;
  2000. linux,phandle = <0x47>;
  2001. phandle = <0x47>;
  2002. };
  2003.  
  2004. syc_clk_div_ck {
  2005. #clock-cells = <0x0>;
  2006. compatible = "ti,divider-clock";
  2007. clocks = <0xf>;
  2008. reg = <0x100>;
  2009. ti,max-div = <0x2>;
  2010. linux,phandle = <0x23>;
  2011. phandle = <0x23>;
  2012. };
  2013.  
  2014. gpio1_dbclk {
  2015. #clock-cells = <0x0>;
  2016. compatible = "ti,gate-clock";
  2017. clocks = <0x2c>;
  2018. ti,bit-shift = <0x8>;
  2019. reg = <0x1838>;
  2020. linux,phandle = <0x10a>;
  2021. phandle = <0x10a>;
  2022. };
  2023.  
  2024. dmt1_clk_mux {
  2025. #clock-cells = <0x0>;
  2026. compatible = "ti,mux-clock";
  2027. clocks = <0xf 0x2c>;
  2028. ti,bit-shift = <0x18>;
  2029. reg = <0x1840>;
  2030. linux,phandle = <0x10b>;
  2031. phandle = <0x10b>;
  2032. };
  2033.  
  2034. usim_ck {
  2035. #clock-cells = <0x0>;
  2036. compatible = "ti,divider-clock";
  2037. clocks = <0x38>;
  2038. ti,bit-shift = <0x18>;
  2039. reg = <0x1858>;
  2040. ti,dividers = <0xe 0x12>;
  2041. linux,phandle = <0x60>;
  2042. phandle = <0x60>;
  2043. };
  2044.  
  2045. usim_fclk {
  2046. #clock-cells = <0x0>;
  2047. compatible = "ti,gate-clock";
  2048. clocks = <0x60>;
  2049. ti,bit-shift = <0x8>;
  2050. reg = <0x1858>;
  2051. linux,phandle = <0x10c>;
  2052. phandle = <0x10c>;
  2053. };
  2054.  
  2055. pmd_stm_clock_mux_ck {
  2056. #clock-cells = <0x0>;
  2057. compatible = "ti,mux-clock";
  2058. clocks = <0xf 0x61 0x62>;
  2059. ti,bit-shift = <0x14>;
  2060. reg = <0x1a20>;
  2061. linux,phandle = <0x63>;
  2062. phandle = <0x63>;
  2063. };
  2064.  
  2065. pmd_trace_clk_mux_ck {
  2066. #clock-cells = <0x0>;
  2067. compatible = "ti,mux-clock";
  2068. clocks = <0xf 0x61 0x62>;
  2069. ti,bit-shift = <0x16>;
  2070. reg = <0x1a20>;
  2071. linux,phandle = <0x64>;
  2072. phandle = <0x64>;
  2073. };
  2074.  
  2075. stm_clk_div_ck {
  2076. #clock-cells = <0x0>;
  2077. compatible = "ti,divider-clock";
  2078. clocks = <0x63>;
  2079. ti,bit-shift = <0x1b>;
  2080. ti,max-div = <0x40>;
  2081. reg = <0x1a20>;
  2082. ti,index-power-of-two;
  2083. linux,phandle = <0x10d>;
  2084. phandle = <0x10d>;
  2085. };
  2086.  
  2087. trace_clk_div_div_ck {
  2088. #clock-cells = <0x0>;
  2089. compatible = "ti,divider-clock";
  2090. clocks = <0x64>;
  2091. ti,bit-shift = <0x18>;
  2092. reg = <0x1a20>;
  2093. ti,dividers = <0x0 0x1 0x2 0x0 0x4>;
  2094. linux,phandle = <0x65>;
  2095. phandle = <0x65>;
  2096. };
  2097.  
  2098. trace_clk_div_ck {
  2099. #clock-cells = <0x0>;
  2100. compatible = "ti,clkdm-gate-clock";
  2101. clocks = <0x65>;
  2102. linux,phandle = <0x67>;
  2103. phandle = <0x67>;
  2104. };
  2105.  
  2106. div_ts_ck {
  2107. #clock-cells = <0x0>;
  2108. compatible = "ti,divider-clock";
  2109. clocks = <0x47>;
  2110. ti,bit-shift = <0x18>;
  2111. reg = <0x1888>;
  2112. ti,dividers = <0x8 0x10 0x20>;
  2113. linux,phandle = <0x66>;
  2114. phandle = <0x66>;
  2115. };
  2116.  
  2117. bandgap_ts_fclk {
  2118. #clock-cells = <0x0>;
  2119. compatible = "ti,gate-clock";
  2120. clocks = <0x66>;
  2121. ti,bit-shift = <0x8>;
  2122. reg = <0x1888>;
  2123. linux,phandle = <0x10e>;
  2124. phandle = <0x10e>;
  2125. };
  2126. };
  2127.  
  2128. clockdomains {
  2129. linux,phandle = <0x10f>;
  2130. phandle = <0x10f>;
  2131.  
  2132. emu_sys_clkdm {
  2133. compatible = "ti,clockdomain";
  2134. clocks = <0x67>;
  2135. linux,phandle = <0x110>;
  2136. phandle = <0x110>;
  2137. };
  2138. };
  2139. };
  2140.  
  2141. scrm@a000 {
  2142. compatible = "ti,omap4-scrm";
  2143. reg = <0xa000 0x2000>;
  2144. linux,phandle = <0x111>;
  2145. phandle = <0x111>;
  2146.  
  2147. clocks {
  2148. #address-cells = <0x1>;
  2149. #size-cells = <0x0>;
  2150. linux,phandle = <0x112>;
  2151. phandle = <0x112>;
  2152.  
  2153. auxclk0_src_gate_ck {
  2154. #clock-cells = <0x0>;
  2155. compatible = "ti,composite-no-wait-gate-clock";
  2156. clocks = <0x68>;
  2157. ti,bit-shift = <0x8>;
  2158. reg = <0x310>;
  2159. linux,phandle = <0x6a>;
  2160. phandle = <0x6a>;
  2161. };
  2162.  
  2163. auxclk0_src_mux_ck {
  2164. #clock-cells = <0x0>;
  2165. compatible = "ti,composite-mux-clock";
  2166. clocks = <0xf 0x68 0x69>;
  2167. ti,bit-shift = <0x1>;
  2168. reg = <0x310>;
  2169. linux,phandle = <0x6b>;
  2170. phandle = <0x6b>;
  2171. };
  2172.  
  2173. auxclk0_src_ck {
  2174. #clock-cells = <0x0>;
  2175. compatible = "ti,composite-clock";
  2176. clocks = <0x6a 0x6b>;
  2177. linux,phandle = <0x6c>;
  2178. phandle = <0x6c>;
  2179. };
  2180.  
  2181. auxclk0_ck {
  2182. #clock-cells = <0x0>;
  2183. compatible = "ti,divider-clock";
  2184. clocks = <0x6c>;
  2185. ti,bit-shift = <0x10>;
  2186. ti,max-div = <0x10>;
  2187. reg = <0x310>;
  2188. linux,phandle = <0x7c>;
  2189. phandle = <0x7c>;
  2190. };
  2191.  
  2192. auxclk1_src_gate_ck {
  2193. #clock-cells = <0x0>;
  2194. compatible = "ti,composite-no-wait-gate-clock";
  2195. clocks = <0x68>;
  2196. ti,bit-shift = <0x8>;
  2197. reg = <0x314>;
  2198. linux,phandle = <0x6d>;
  2199. phandle = <0x6d>;
  2200. };
  2201.  
  2202. auxclk1_src_mux_ck {
  2203. #clock-cells = <0x0>;
  2204. compatible = "ti,composite-mux-clock";
  2205. clocks = <0xf 0x68 0x69>;
  2206. ti,bit-shift = <0x1>;
  2207. reg = <0x314>;
  2208. linux,phandle = <0x6e>;
  2209. phandle = <0x6e>;
  2210. };
  2211.  
  2212. auxclk1_src_ck {
  2213. #clock-cells = <0x0>;
  2214. compatible = "ti,composite-clock";
  2215. clocks = <0x6d 0x6e>;
  2216. linux,phandle = <0x6f>;
  2217. phandle = <0x6f>;
  2218. };
  2219.  
  2220. auxclk1_ck {
  2221. #clock-cells = <0x0>;
  2222. compatible = "ti,divider-clock";
  2223. clocks = <0x6f>;
  2224. ti,bit-shift = <0x10>;
  2225. ti,max-div = <0x10>;
  2226. reg = <0x314>;
  2227. linux,phandle = <0x7d>;
  2228. phandle = <0x7d>;
  2229. };
  2230.  
  2231. auxclk2_src_gate_ck {
  2232. #clock-cells = <0x0>;
  2233. compatible = "ti,composite-no-wait-gate-clock";
  2234. clocks = <0x68>;
  2235. ti,bit-shift = <0x8>;
  2236. reg = <0x318>;
  2237. linux,phandle = <0x70>;
  2238. phandle = <0x70>;
  2239. };
  2240.  
  2241. auxclk2_src_mux_ck {
  2242. #clock-cells = <0x0>;
  2243. compatible = "ti,composite-mux-clock";
  2244. clocks = <0xf 0x68 0x69>;
  2245. ti,bit-shift = <0x1>;
  2246. reg = <0x318>;
  2247. linux,phandle = <0x71>;
  2248. phandle = <0x71>;
  2249. };
  2250.  
  2251. auxclk2_src_ck {
  2252. #clock-cells = <0x0>;
  2253. compatible = "ti,composite-clock";
  2254. clocks = <0x70 0x71>;
  2255. linux,phandle = <0x72>;
  2256. phandle = <0x72>;
  2257. };
  2258.  
  2259. auxclk2_ck {
  2260. #clock-cells = <0x0>;
  2261. compatible = "ti,divider-clock";
  2262. clocks = <0x72>;
  2263. ti,bit-shift = <0x10>;
  2264. ti,max-div = <0x10>;
  2265. reg = <0x318>;
  2266. linux,phandle = <0x7e>;
  2267. phandle = <0x7e>;
  2268. };
  2269.  
  2270. auxclk3_src_gate_ck {
  2271. #clock-cells = <0x0>;
  2272. compatible = "ti,composite-no-wait-gate-clock";
  2273. clocks = <0x68>;
  2274. ti,bit-shift = <0x8>;
  2275. reg = <0x31c>;
  2276. linux,phandle = <0x73>;
  2277. phandle = <0x73>;
  2278. };
  2279.  
  2280. auxclk3_src_mux_ck {
  2281. #clock-cells = <0x0>;
  2282. compatible = "ti,composite-mux-clock";
  2283. clocks = <0xf 0x68 0x69>;
  2284. ti,bit-shift = <0x1>;
  2285. reg = <0x31c>;
  2286. linux,phandle = <0x74>;
  2287. phandle = <0x74>;
  2288. };
  2289.  
  2290. auxclk3_src_ck {
  2291. #clock-cells = <0x0>;
  2292. compatible = "ti,composite-clock";
  2293. clocks = <0x73 0x74>;
  2294. linux,phandle = <0x75>;
  2295. phandle = <0x75>;
  2296. };
  2297.  
  2298. auxclk3_ck {
  2299. #clock-cells = <0x0>;
  2300. compatible = "ti,divider-clock";
  2301. clocks = <0x75>;
  2302. ti,bit-shift = <0x10>;
  2303. ti,max-div = <0x10>;
  2304. reg = <0x31c>;
  2305. linux,phandle = <0x7f>;
  2306. phandle = <0x7f>;
  2307. };
  2308.  
  2309. auxclk4_src_gate_ck {
  2310. #clock-cells = <0x0>;
  2311. compatible = "ti,composite-no-wait-gate-clock";
  2312. clocks = <0x68>;
  2313. ti,bit-shift = <0x8>;
  2314. reg = <0x320>;
  2315. linux,phandle = <0x76>;
  2316. phandle = <0x76>;
  2317. };
  2318.  
  2319. auxclk4_src_mux_ck {
  2320. #clock-cells = <0x0>;
  2321. compatible = "ti,composite-mux-clock";
  2322. clocks = <0xf 0x68 0x69>;
  2323. ti,bit-shift = <0x1>;
  2324. reg = <0x320>;
  2325. linux,phandle = <0x77>;
  2326. phandle = <0x77>;
  2327. };
  2328.  
  2329. auxclk4_src_ck {
  2330. #clock-cells = <0x0>;
  2331. compatible = "ti,composite-clock";
  2332. clocks = <0x76 0x77>;
  2333. linux,phandle = <0x78>;
  2334. phandle = <0x78>;
  2335. };
  2336.  
  2337. auxclk4_ck {
  2338. #clock-cells = <0x0>;
  2339. compatible = "ti,divider-clock";
  2340. clocks = <0x78>;
  2341. ti,bit-shift = <0x10>;
  2342. ti,max-div = <0x10>;
  2343. reg = <0x320>;
  2344. linux,phandle = <0x80>;
  2345. phandle = <0x80>;
  2346. };
  2347.  
  2348. auxclk5_src_gate_ck {
  2349. #clock-cells = <0x0>;
  2350. compatible = "ti,composite-no-wait-gate-clock";
  2351. clocks = <0x68>;
  2352. ti,bit-shift = <0x8>;
  2353. reg = <0x324>;
  2354. linux,phandle = <0x79>;
  2355. phandle = <0x79>;
  2356. };
  2357.  
  2358. auxclk5_src_mux_ck {
  2359. #clock-cells = <0x0>;
  2360. compatible = "ti,composite-mux-clock";
  2361. clocks = <0xf 0x68 0x69>;
  2362. ti,bit-shift = <0x1>;
  2363. reg = <0x324>;
  2364. linux,phandle = <0x7a>;
  2365. phandle = <0x7a>;
  2366. };
  2367.  
  2368. auxclk5_src_ck {
  2369. #clock-cells = <0x0>;
  2370. compatible = "ti,composite-clock";
  2371. clocks = <0x79 0x7a>;
  2372. linux,phandle = <0x7b>;
  2373. phandle = <0x7b>;
  2374. };
  2375.  
  2376. auxclk5_ck {
  2377. #clock-cells = <0x0>;
  2378. compatible = "ti,divider-clock";
  2379. clocks = <0x7b>;
  2380. ti,bit-shift = <0x10>;
  2381. ti,max-div = <0x10>;
  2382. reg = <0x324>;
  2383. linux,phandle = <0x81>;
  2384. phandle = <0x81>;
  2385. };
  2386.  
  2387. auxclkreq0_ck {
  2388. #clock-cells = <0x0>;
  2389. compatible = "ti,mux-clock";
  2390. clocks = <0x7c 0x7d 0x7e 0x7f 0x80 0x81>;
  2391. ti,bit-shift = <0x2>;
  2392. reg = <0x210>;
  2393. linux,phandle = <0x113>;
  2394. phandle = <0x113>;
  2395. };
  2396.  
  2397. auxclkreq1_ck {
  2398. #clock-cells = <0x0>;
  2399. compatible = "ti,mux-clock";
  2400. clocks = <0x7c 0x7d 0x7e 0x7f 0x80 0x81>;
  2401. ti,bit-shift = <0x2>;
  2402. reg = <0x214>;
  2403. linux,phandle = <0x114>;
  2404. phandle = <0x114>;
  2405. };
  2406.  
  2407. auxclkreq2_ck {
  2408. #clock-cells = <0x0>;
  2409. compatible = "ti,mux-clock";
  2410. clocks = <0x7c 0x7d 0x7e 0x7f 0x80 0x81>;
  2411. ti,bit-shift = <0x2>;
  2412. reg = <0x218>;
  2413. linux,phandle = <0x115>;
  2414. phandle = <0x115>;
  2415. };
  2416.  
  2417. auxclkreq3_ck {
  2418. #clock-cells = <0x0>;
  2419. compatible = "ti,mux-clock";
  2420. clocks = <0x7c 0x7d 0x7e 0x7f 0x80 0x81>;
  2421. ti,bit-shift = <0x2>;
  2422. reg = <0x21c>;
  2423. linux,phandle = <0x116>;
  2424. phandle = <0x116>;
  2425. };
  2426.  
  2427. auxclkreq4_ck {
  2428. #clock-cells = <0x0>;
  2429. compatible = "ti,mux-clock";
  2430. clocks = <0x7c 0x7d 0x7e 0x7f 0x80 0x81>;
  2431. ti,bit-shift = <0x2>;
  2432. reg = <0x220>;
  2433. linux,phandle = <0x117>;
  2434. phandle = <0x117>;
  2435. };
  2436.  
  2437. auxclkreq5_ck {
  2438. #clock-cells = <0x0>;
  2439. compatible = "ti,mux-clock";
  2440. clocks = <0x7c 0x7d 0x7e 0x7f 0x80 0x81>;
  2441. ti,bit-shift = <0x2>;
  2442. reg = <0x224>;
  2443. linux,phandle = <0x118>;
  2444. phandle = <0x118>;
  2445. };
  2446. };
  2447.  
  2448. clockdomains {
  2449. linux,phandle = <0x119>;
  2450. phandle = <0x119>;
  2451. };
  2452. };
  2453.  
  2454. pinmux@1e040 {
  2455. compatible = "ti,omap4-padconf", "pinctrl-single";
  2456. reg = <0x1e040 0x38>;
  2457. #address-cells = <0x1>;
  2458. #size-cells = <0x0>;
  2459. #interrupt-cells = <0x1>;
  2460. interrupt-controller;
  2461. pinctrl-single,register-width = <0x10>;
  2462. pinctrl-single,function-mask = <0x7fff>;
  2463. linux,phandle = <0x11a>;
  2464. phandle = <0x11a>;
  2465.  
  2466. pinmux_leds_wkpins {
  2467. pinctrl-single,pins = <0x1c 0x3>;
  2468. linux,phandle = <0xa9>;
  2469. phandle = <0xa9>;
  2470. };
  2471.  
  2472. pinmux_twl6030_wkup_pins {
  2473. pinctrl-single,pins = <0x14 0x2>;
  2474. linux,phandle = <0x85>;
  2475. phandle = <0x85>;
  2476. };
  2477. };
  2478. };
  2479. };
  2480.  
  2481. ocmcram@40304000 {
  2482. compatible = "mmio-sram";
  2483. reg = <0x40304000 0xa000>;
  2484. linux,phandle = <0x6>;
  2485. phandle = <0x6>;
  2486. };
  2487.  
  2488. dma-controller@4a056000 {
  2489. compatible = "ti,omap4430-sdma";
  2490. reg = <0x4a056000 0x1000>;
  2491. interrupts = <0x0 0xc 0x4 0x0 0xd 0x4 0x0 0xe 0x4 0x0 0xf 0x4>;
  2492. #dma-cells = <0x1>;
  2493. dma-channels = <0x20>;
  2494. dma-requests = <0x7f>;
  2495. linux,phandle = <0x8e>;
  2496. phandle = <0x8e>;
  2497. };
  2498.  
  2499. gpio@4a310000 {
  2500. compatible = "ti,omap4-gpio";
  2501. reg = <0x4a310000 0x200>;
  2502. interrupts = <0x0 0x1d 0x4>;
  2503. ti,hwmods = "gpio1";
  2504. ti,gpio-always-on;
  2505. gpio-controller;
  2506. #gpio-cells = <0x2>;
  2507. interrupt-controller;
  2508. #interrupt-cells = <0x2>;
  2509. ti,no-reset-on-init;
  2510. linux,phandle = <0xaa>;
  2511. phandle = <0xaa>;
  2512. };
  2513.  
  2514. gpio@48055000 {
  2515. compatible = "ti,omap4-gpio";
  2516. reg = <0x48055000 0x200>;
  2517. interrupts = <0x0 0x1e 0x4>;
  2518. ti,hwmods = "gpio2";
  2519. gpio-controller;
  2520. #gpio-cells = <0x2>;
  2521. interrupt-controller;
  2522. #interrupt-cells = <0x2>;
  2523. linux,phandle = <0x93>;
  2524. phandle = <0x93>;
  2525. };
  2526.  
  2527. gpio@48057000 {
  2528. compatible = "ti,omap4-gpio";
  2529. reg = <0x48057000 0x200>;
  2530. interrupts = <0x0 0x1f 0x4>;
  2531. ti,hwmods = "gpio3";
  2532. gpio-controller;
  2533. #gpio-cells = <0x2>;
  2534. interrupt-controller;
  2535. #interrupt-cells = <0x2>;
  2536. linux,phandle = <0xa4>;
  2537. phandle = <0xa4>;
  2538. };
  2539.  
  2540. gpio@48059000 {
  2541. compatible = "ti,omap4-gpio";
  2542. reg = <0x48059000 0x200>;
  2543. interrupts = <0x0 0x20 0x4>;
  2544. ti,hwmods = "gpio4";
  2545. gpio-controller;
  2546. #gpio-cells = <0x2>;
  2547. interrupt-controller;
  2548. #interrupt-cells = <0x2>;
  2549. linux,phandle = <0x88>;
  2550. phandle = <0x88>;
  2551. };
  2552.  
  2553. gpio@4805b000 {
  2554. compatible = "ti,omap4-gpio";
  2555. reg = <0x4805b000 0x200>;
  2556. interrupts = <0x0 0x21 0x4>;
  2557. ti,hwmods = "gpio5";
  2558. gpio-controller;
  2559. #gpio-cells = <0x2>;
  2560. interrupt-controller;
  2561. #interrupt-cells = <0x2>;
  2562. linux,phandle = <0x11b>;
  2563. phandle = <0x11b>;
  2564. };
  2565.  
  2566. gpio@4805d000 {
  2567. compatible = "ti,omap4-gpio";
  2568. reg = <0x4805d000 0x200>;
  2569. interrupts = <0x0 0x22 0x4>;
  2570. ti,hwmods = "gpio6";
  2571. gpio-controller;
  2572. #gpio-cells = <0x2>;
  2573. interrupt-controller;
  2574. #interrupt-cells = <0x2>;
  2575. linux,phandle = <0x11c>;
  2576. phandle = <0x11c>;
  2577. };
  2578.  
  2579. gpmc@50000000 {
  2580. compatible = "ti,omap4430-gpmc";
  2581. reg = <0x50000000 0x1000>;
  2582. #address-cells = <0x2>;
  2583. #size-cells = <0x1>;
  2584. interrupts = <0x0 0x14 0x4>;
  2585. gpmc,num-cs = <0x8>;
  2586. gpmc,num-waitpins = <0x4>;
  2587. ti,hwmods = "gpmc";
  2588. ti,no-idle-on-init;
  2589. clocks = <0x1f>;
  2590. clock-names = "fck";
  2591. linux,phandle = <0x11d>;
  2592. phandle = <0x11d>;
  2593. };
  2594.  
  2595. serial@4806a000 {
  2596. compatible = "ti,omap4-uart";
  2597. reg = <0x4806a000 0x100>;
  2598. interrupts = <0x0 0x48 0x4>;
  2599. ti,hwmods = "uart1";
  2600. clock-frequency = <0x2dc6c00>;
  2601. linux,phandle = <0x11e>;
  2602. phandle = <0x11e>;
  2603. };
  2604.  
  2605. serial@4806c000 {
  2606. compatible = "ti,omap4-uart";
  2607. reg = <0x4806c000 0x100>;
  2608. interrupts = <0x0 0x49 0x4>;
  2609. ti,hwmods = "uart2";
  2610. clock-frequency = <0x2dc6c00>;
  2611. interrupts-extended = <0x1 0x0 0x49 0x4 0x82 0xdc>;
  2612. linux,phandle = <0x11f>;
  2613. phandle = <0x11f>;
  2614. };
  2615.  
  2616. serial@48020000 {
  2617. compatible = "ti,omap4-uart";
  2618. reg = <0x48020000 0x100>;
  2619. interrupts = <0x0 0x4a 0x4>;
  2620. ti,hwmods = "uart3";
  2621. clock-frequency = <0x2dc6c00>;
  2622. interrupts-extended = <0x1 0x0 0x4a 0x4 0x82 0x104>;
  2623. linux,phandle = <0x120>;
  2624. phandle = <0x120>;
  2625. };
  2626.  
  2627. serial@4806e000 {
  2628. compatible = "ti,omap4-uart";
  2629. reg = <0x4806e000 0x100>;
  2630. interrupts = <0x0 0x46 0x4>;
  2631. ti,hwmods = "uart4";
  2632. pinctrl-names = "default";
  2633. pinctrl-0 = <0xfff>;
  2634. clock-frequency = <0x2dc6c00>;
  2635. interrupts-extended = <0x1 0x0 0x46 0x4 0x82 0x11c>;
  2636. linux,phandle = <0x121>;
  2637. phandle = <0x121>;
  2638. };
  2639.  
  2640. spinlock@4a0f6000 {
  2641. compatible = "ti,omap4-hwspinlock";
  2642. reg = <0x4a0f6000 0x1000>;
  2643. ti,hwmods = "spinlock";
  2644. #hwlock-cells = <0x1>;
  2645. linux,phandle = <0x122>;
  2646. phandle = <0x122>;
  2647. };
  2648.  
  2649. i2c@48070000 {
  2650. compatible = "ti,omap4-i2c";
  2651. reg = <0x48070000 0x100>;
  2652. interrupts = <0x0 0x38 0x4>;
  2653. #address-cells = <0x1>;
  2654. #size-cells = <0x0>;
  2655. ti,hwmods = "i2c1";
  2656. pinctrl-names = "default";
  2657. pinctrl-0 = <0x83>;
  2658. clock-frequency = <0x61a80>;
  2659. linux,phandle = <0x123>;
  2660. phandle = <0x123>;
  2661.  
  2662. twl@48 {
  2663. reg = <0x48>;
  2664. interrupts = <0x0 0x7 0x4>;
  2665. compatible = "ti,twl6030";
  2666. interrupt-controller;
  2667. #interrupt-cells = <0x1>;
  2668. pinctrl-names = "default";
  2669. pinctrl-0 = <0x84 0x85>;
  2670. linux,phandle = <0x124>;
  2671. phandle = <0x124>;
  2672.  
  2673. rtc {
  2674. compatible = "ti,twl4030-rtc";
  2675. interrupts = <0xb>;
  2676. };
  2677.  
  2678. regulator-vaux1 {
  2679. compatible = "ti,twl6030-vaux1";
  2680. regulator-min-microvolt = <0xf4240>;
  2681. regulator-max-microvolt = <0x2dc6c0>;
  2682. linux,phandle = <0x125>;
  2683. phandle = <0x125>;
  2684. };
  2685.  
  2686. regulator-vaux2 {
  2687. compatible = "ti,twl6030-vaux2";
  2688. regulator-min-microvolt = <0x124f80>;
  2689. regulator-max-microvolt = <0x2ab980>;
  2690. linux,phandle = <0x126>;
  2691. phandle = <0x126>;
  2692. };
  2693.  
  2694. regulator-vaux3 {
  2695. compatible = "ti,twl6030-vaux3";
  2696. regulator-min-microvolt = <0xf4240>;
  2697. regulator-max-microvolt = <0x2dc6c0>;
  2698. linux,phandle = <0x127>;
  2699. phandle = <0x127>;
  2700. };
  2701.  
  2702. regulator-vmmc {
  2703. compatible = "ti,twl6030-vmmc";
  2704. regulator-min-microvolt = <0x124f80>;
  2705. regulator-max-microvolt = <0x2dc6c0>;
  2706. linux,phandle = <0x90>;
  2707. phandle = <0x90>;
  2708. };
  2709.  
  2710. regulator-vpp {
  2711. compatible = "ti,twl6030-vpp";
  2712. regulator-min-microvolt = <0x1b7740>;
  2713. regulator-max-microvolt = <0x2625a0>;
  2714. linux,phandle = <0x128>;
  2715. phandle = <0x128>;
  2716. };
  2717.  
  2718. regulator-vusim {
  2719. compatible = "ti,twl6030-vusim";
  2720. regulator-min-microvolt = <0x124f80>;
  2721. regulator-max-microvolt = <0x2c4020>;
  2722. linux,phandle = <0x129>;
  2723. phandle = <0x129>;
  2724. };
  2725.  
  2726. regulator-vdac {
  2727. compatible = "ti,twl6030-vdac";
  2728. linux,phandle = <0xa1>;
  2729. phandle = <0xa1>;
  2730. };
  2731.  
  2732. regulator-vana {
  2733. compatible = "ti,twl6030-vana";
  2734. linux,phandle = <0x12a>;
  2735. phandle = <0x12a>;
  2736. };
  2737.  
  2738. regulator-vcxio {
  2739. compatible = "ti,twl6030-vcxio";
  2740. regulator-always-on;
  2741. linux,phandle = <0x9f>;
  2742. phandle = <0x9f>;
  2743. };
  2744.  
  2745. regulator-vusb {
  2746. compatible = "ti,twl6030-vusb";
  2747. linux,phandle = <0x86>;
  2748. phandle = <0x86>;
  2749. };
  2750.  
  2751. regulator-v1v8 {
  2752. compatible = "ti,twl6030-v1v8";
  2753. regulator-always-on;
  2754. linux,phandle = <0x89>;
  2755. phandle = <0x89>;
  2756. };
  2757.  
  2758. regulator-v2v1 {
  2759. compatible = "ti,twl6030-v2v1";
  2760. regulator-always-on;
  2761. linux,phandle = <0x8a>;
  2762. phandle = <0x8a>;
  2763. };
  2764.  
  2765. usb-comparator {
  2766. compatible = "ti,twl6030-usb";
  2767. interrupts = <0x4 0xa>;
  2768. usb-supply = <0x86>;
  2769. linux,phandle = <0x12b>;
  2770. phandle = <0x12b>;
  2771. };
  2772.  
  2773. pwm {
  2774. compatible = "ti,twl6030-pwm";
  2775. #pwm-cells = <0x2>;
  2776. linux,phandle = <0x12c>;
  2777. phandle = <0x12c>;
  2778. };
  2779.  
  2780. pwmled {
  2781. compatible = "ti,twl6030-pwmled";
  2782. #pwm-cells = <0x2>;
  2783. linux,phandle = <0x12d>;
  2784. phandle = <0x12d>;
  2785. };
  2786. };
  2787.  
  2788. twl@4b {
  2789. compatible = "ti,twl6040";
  2790. reg = <0x4b>;
  2791. pinctrl-names = "default";
  2792. pinctrl-0 = <0x87>;
  2793. interrupts = <0x0 0x77 0x4>;
  2794. ti,audpwron-gpio = <0x88 0x1f 0x0>;
  2795. vio-supply = <0x89>;
  2796. v2v1-supply = <0x8a>;
  2797. enable-active-high;
  2798. linux,phandle = <0xac>;
  2799. phandle = <0xac>;
  2800. };
  2801. };
  2802.  
  2803. i2c@48072000 {
  2804. compatible = "ti,omap4-i2c";
  2805. reg = <0x48072000 0x100>;
  2806. interrupts = <0x0 0x39 0x4>;
  2807. #address-cells = <0x1>;
  2808. #size-cells = <0x0>;
  2809. ti,hwmods = "i2c2";
  2810. pinctrl-names = "default";
  2811. pinctrl-0 = <0x8b>;
  2812. clock-frequency = <0x61a80>;
  2813. linux,phandle = <0x12e>;
  2814. phandle = <0x12e>;
  2815. };
  2816.  
  2817. i2c@48060000 {
  2818. compatible = "ti,omap4-i2c";
  2819. reg = <0x48060000 0x100>;
  2820. interrupts = <0x0 0x3d 0x4>;
  2821. #address-cells = <0x1>;
  2822. #size-cells = <0x0>;
  2823. ti,hwmods = "i2c3";
  2824. pinctrl-names = "default";
  2825. pinctrl-0 = <0x8c>;
  2826. clock-frequency = <0x186a0>;
  2827. linux,phandle = <0xb1>;
  2828. phandle = <0xb1>;
  2829.  
  2830. eeprom@50 {
  2831. compatible = "ti,eeprom";
  2832. reg = <0x50>;
  2833. };
  2834. };
  2835.  
  2836. i2c@48350000 {
  2837. compatible = "ti,omap4-i2c";
  2838. reg = <0x48350000 0x100>;
  2839. interrupts = <0x0 0x3e 0x4>;
  2840. #address-cells = <0x1>;
  2841. #size-cells = <0x0>;
  2842. ti,hwmods = "i2c4";
  2843. pinctrl-names = "default";
  2844. pinctrl-0 = <0x8d>;
  2845. clock-frequency = <0x61a80>;
  2846. linux,phandle = <0x12f>;
  2847. phandle = <0x12f>;
  2848. };
  2849.  
  2850. spi@48098000 {
  2851. compatible = "ti,omap4-mcspi";
  2852. reg = <0x48098000 0x200>;
  2853. interrupts = <0x0 0x41 0x4>;
  2854. #address-cells = <0x1>;
  2855. #size-cells = <0x0>;
  2856. ti,hwmods = "mcspi1";
  2857. ti,spi-num-cs = <0x4>;
  2858. dmas = <0x8e 0x23 0x8e 0x24 0x8e 0x25 0x8e 0x26 0x8e 0x27 0x8e 0x28 0x8e 0x29 0x8e 0x2a>;
  2859. dma-names = "tx0", "rx0", "tx1", "rx1", "tx2", "rx2", "tx3", "rx3";
  2860. linux,phandle = <0x130>;
  2861. phandle = <0x130>;
  2862. };
  2863.  
  2864. spi@4809a000 {
  2865. compatible = "ti,omap4-mcspi";
  2866. reg = <0x4809a000 0x200>;
  2867. interrupts = <0x0 0x42 0x4>;
  2868. #address-cells = <0x1>;
  2869. #size-cells = <0x0>;
  2870. ti,hwmods = "mcspi2";
  2871. ti,spi-num-cs = <0x2>;
  2872. dmas = <0x8e 0x2b 0x8e 0x2c 0x8e 0x2d 0x8e 0x2e>;
  2873. dma-names = "tx0", "rx0", "tx1", "rx1";
  2874. linux,phandle = <0x131>;
  2875. phandle = <0x131>;
  2876. };
  2877.  
  2878. spi@480b8000 {
  2879. compatible = "ti,omap4-mcspi";
  2880. reg = <0x480b8000 0x200>;
  2881. interrupts = <0x0 0x5b 0x4>;
  2882. #address-cells = <0x1>;
  2883. #size-cells = <0x0>;
  2884. ti,hwmods = "mcspi3";
  2885. ti,spi-num-cs = <0x2>;
  2886. dmas = <0x8e 0xf 0x8e 0x10>;
  2887. dma-names = "tx0", "rx0";
  2888. linux,phandle = <0x132>;
  2889. phandle = <0x132>;
  2890. };
  2891.  
  2892. spi@480ba000 {
  2893. compatible = "ti,omap4-mcspi";
  2894. reg = <0x480ba000 0x200>;
  2895. interrupts = <0x0 0x30 0x4>;
  2896. #address-cells = <0x1>;
  2897. #size-cells = <0x0>;
  2898. ti,hwmods = "mcspi4";
  2899. ti,spi-num-cs = <0x1>;
  2900. dmas = <0x8e 0x46 0x8e 0x47>;
  2901. dma-names = "tx0", "rx0";
  2902. linux,phandle = <0x133>;
  2903. phandle = <0x133>;
  2904. };
  2905.  
  2906. mmc@4809c000 {
  2907. compatible = "ti,omap4-hsmmc";
  2908. reg = <0x4809c000 0x400>;
  2909. interrupts = <0x0 0x53 0x4>;
  2910. ti,hwmods = "mmc1";
  2911. ti,dual-volt;
  2912. ti,needs-special-reset;
  2913. dmas = <0x8e 0x3d 0x8e 0x3e>;
  2914. dma-names = "tx", "rx";
  2915. pbias-supply = <0x8f>;
  2916. vmmc-supply = <0x90>;
  2917. bus-width = <0x8>;
  2918. linux,phandle = <0x134>;
  2919. phandle = <0x134>;
  2920. };
  2921.  
  2922. mmc@480b4000 {
  2923. compatible = "ti,omap4-hsmmc";
  2924. reg = <0x480b4000 0x400>;
  2925. interrupts = <0x0 0x56 0x4>;
  2926. ti,hwmods = "mmc2";
  2927. ti,needs-special-reset;
  2928. dmas = <0x8e 0x2f 0x8e 0x30>;
  2929. dma-names = "tx", "rx";
  2930. status = "disabled";
  2931. linux,phandle = <0x135>;
  2932. phandle = <0x135>;
  2933. };
  2934.  
  2935. mmc@480ad000 {
  2936. compatible = "ti,omap4-hsmmc";
  2937. reg = <0x480ad000 0x400>;
  2938. interrupts = <0x0 0x5e 0x4>;
  2939. ti,hwmods = "mmc3";
  2940. ti,needs-special-reset;
  2941. dmas = <0x8e 0x4d 0x8e 0x4e>;
  2942. dma-names = "tx", "rx";
  2943. status = "disabled";
  2944. linux,phandle = <0x136>;
  2945. phandle = <0x136>;
  2946. };
  2947.  
  2948. mmc@480d1000 {
  2949. compatible = "ti,omap4-hsmmc";
  2950. reg = <0x480d1000 0x400>;
  2951. interrupts = <0x0 0x60 0x4>;
  2952. ti,hwmods = "mmc4";
  2953. ti,needs-special-reset;
  2954. dmas = <0x8e 0x39 0x8e 0x3a>;
  2955. dma-names = "tx", "rx";
  2956. status = "disabled";
  2957. linux,phandle = <0x137>;
  2958. phandle = <0x137>;
  2959. };
  2960.  
  2961. mmc@480d5000 {
  2962. compatible = "ti,omap4-hsmmc";
  2963. reg = <0x480d5000 0x400>;
  2964. interrupts = <0x0 0x3b 0x4>;
  2965. ti,hwmods = "mmc5";
  2966. ti,needs-special-reset;
  2967. dmas = <0x8e 0x3b 0x8e 0x3c>;
  2968. dma-names = "tx", "rx";
  2969. pinctrl-names = "default";
  2970. pinctrl-0 = <0x91>;
  2971. vmmc-supply = <0x92>;
  2972. non-removable;
  2973. bus-width = <0x4>;
  2974. cap-power-off-card;
  2975. #address-cells = <0x1>;
  2976. #size-cells = <0x0>;
  2977. linux,phandle = <0x138>;
  2978. phandle = <0x138>;
  2979.  
  2980. wlcore@2 {
  2981. compatible = "ti,wl1271";
  2982. reg = <0x2>;
  2983. interrupt-parent = <0x93>;
  2984. interrupts = <0x15 0x4>;
  2985. ref-clock-frequency = <0x249f000>;
  2986. linux,phandle = <0x139>;
  2987. phandle = <0x139>;
  2988. };
  2989. };
  2990.  
  2991. mmu@4a066000 {
  2992. compatible = "ti,omap4-iommu";
  2993. reg = <0x4a066000 0x100>;
  2994. interrupts = <0x0 0x1c 0x4>;
  2995. ti,hwmods = "mmu_dsp";
  2996. #iommu-cells = <0x0>;
  2997. linux,phandle = <0x13a>;
  2998. phandle = <0x13a>;
  2999. };
  3000.  
  3001. mmu@55082000 {
  3002. compatible = "ti,omap4-iommu";
  3003. reg = <0x55082000 0x100>;
  3004. interrupts = <0x0 0x64 0x4>;
  3005. ti,hwmods = "mmu_ipu";
  3006. #iommu-cells = <0x0>;
  3007. ti,iommu-bus-err-back;
  3008. linux,phandle = <0x13b>;
  3009. phandle = <0x13b>;
  3010. };
  3011.  
  3012. wdt@4a314000 {
  3013. compatible = "ti,omap4-wdt", "ti,omap3-wdt";
  3014. reg = <0x4a314000 0x80>;
  3015. interrupts = <0x0 0x50 0x4>;
  3016. ti,hwmods = "wd_timer2";
  3017. linux,phandle = <0x13c>;
  3018. phandle = <0x13c>;
  3019. };
  3020.  
  3021. mcpdm@40132000 {
  3022. compatible = "ti,omap4-mcpdm";
  3023. reg = <0x40132000 0x7f 0x49032000 0x7f>;
  3024. reg-names = "mpu", "dma";
  3025. interrupts = <0x0 0x70 0x4>;
  3026. ti,hwmods = "mcpdm";
  3027. dmas = <0x8e 0x41 0x8e 0x42>;
  3028. dma-names = "up_link", "dn_link";
  3029. status = "okay";
  3030. pinctrl-names = "default";
  3031. pinctrl-0 = <0x94>;
  3032. linux,phandle = <0xab>;
  3033. phandle = <0xab>;
  3034. };
  3035.  
  3036. dmic@4012e000 {
  3037. compatible = "ti,omap4-dmic";
  3038. reg = <0x4012e000 0x7f 0x4902e000 0x7f>;
  3039. reg-names = "mpu", "dma";
  3040. interrupts = <0x0 0x72 0x4>;
  3041. ti,hwmods = "dmic";
  3042. dmas = <0x8e 0x43>;
  3043. dma-names = "up_link";
  3044. status = "disabled";
  3045. linux,phandle = <0x13d>;
  3046. phandle = <0x13d>;
  3047. };
  3048.  
  3049. mcbsp@40122000 {
  3050. compatible = "ti,omap4-mcbsp";
  3051. reg = <0x40122000 0xff 0x49022000 0xff>;
  3052. reg-names = "mpu", "dma";
  3053. interrupts = <0x0 0x11 0x4>;
  3054. interrupt-names = "common";
  3055. ti,buffer-size = <0x80>;
  3056. ti,hwmods = "mcbsp1";
  3057. dmas = <0x8e 0x21 0x8e 0x22>;
  3058. dma-names = "tx", "rx";
  3059. status = "okay";
  3060. pinctrl-names = "default";
  3061. pinctrl-0 = <0x95>;
  3062. linux,phandle = <0x13e>;
  3063. phandle = <0x13e>;
  3064. };
  3065.  
  3066. mcbsp@40124000 {
  3067. compatible = "ti,omap4-mcbsp";
  3068. reg = <0x40124000 0xff 0x49024000 0xff>;
  3069. reg-names = "mpu", "dma";
  3070. interrupts = <0x0 0x16 0x4>;
  3071. interrupt-names = "common";
  3072. ti,buffer-size = <0x80>;
  3073. ti,hwmods = "mcbsp2";
  3074. dmas = <0x8e 0x11 0x8e 0x12>;
  3075. dma-names = "tx", "rx";
  3076. status = "disabled";
  3077. linux,phandle = <0x13f>;
  3078. phandle = <0x13f>;
  3079. };
  3080.  
  3081. mcbsp@40126000 {
  3082. compatible = "ti,omap4-mcbsp";
  3083. reg = <0x40126000 0xff 0x49026000 0xff>;
  3084. reg-names = "mpu", "dma";
  3085. interrupts = <0x0 0x17 0x4>;
  3086. interrupt-names = "common";
  3087. ti,buffer-size = <0x80>;
  3088. ti,hwmods = "mcbsp3";
  3089. dmas = <0x8e 0x13 0x8e 0x14>;
  3090. dma-names = "tx", "rx";
  3091. status = "disabled";
  3092. linux,phandle = <0x140>;
  3093. phandle = <0x140>;
  3094. };
  3095.  
  3096. mcbsp@48096000 {
  3097. compatible = "ti,omap4-mcbsp";
  3098. reg = <0x48096000 0xff>;
  3099. reg-names = "mpu";
  3100. interrupts = <0x0 0x10 0x4>;
  3101. interrupt-names = "common";
  3102. ti,buffer-size = <0x80>;
  3103. ti,hwmods = "mcbsp4";
  3104. dmas = <0x8e 0x1f 0x8e 0x20>;
  3105. dma-names = "tx", "rx";
  3106. status = "disabled";
  3107. linux,phandle = <0x141>;
  3108. phandle = <0x141>;
  3109. };
  3110.  
  3111. keypad@4a31c000 {
  3112. compatible = "ti,omap4-keypad";
  3113. reg = <0x4a31c000 0x80>;
  3114. interrupts = <0x0 0x78 0x4>;
  3115. reg-names = "mpu";
  3116. ti,hwmods = "kbd";
  3117. linux,phandle = <0x142>;
  3118. phandle = <0x142>;
  3119. };
  3120.  
  3121. dmm@4e000000 {
  3122. compatible = "ti,omap4-dmm";
  3123. reg = <0x4e000000 0x800>;
  3124. interrupts = <0x0 0x71 0x4>;
  3125. ti,hwmods = "dmm";
  3126. };
  3127.  
  3128. emif@4c000000 {
  3129. compatible = "ti,emif-4d";
  3130. reg = <0x4c000000 0x100>;
  3131. interrupts = <0x0 0x6e 0x4>;
  3132. ti,hwmods = "emif1";
  3133. ti,no-idle-on-init;
  3134. phy-type = <0x1>;
  3135. hw-caps-read-idle-ctrl;
  3136. hw-caps-ll-interface;
  3137. hw-caps-temp-alert;
  3138. status = "ok";
  3139. cs1-used;
  3140. device-handle = <0x96>;
  3141. linux,phandle = <0x143>;
  3142. phandle = <0x143>;
  3143. };
  3144.  
  3145. emif@4d000000 {
  3146. compatible = "ti,emif-4d";
  3147. reg = <0x4d000000 0x100>;
  3148. interrupts = <0x0 0x6f 0x4>;
  3149. ti,hwmods = "emif2";
  3150. ti,no-idle-on-init;
  3151. phy-type = <0x1>;
  3152. hw-caps-read-idle-ctrl;
  3153. hw-caps-ll-interface;
  3154. hw-caps-temp-alert;
  3155. status = "ok";
  3156. cs1-used;
  3157. device-handle = <0x96>;
  3158. linux,phandle = <0x144>;
  3159. phandle = <0x144>;
  3160. };
  3161.  
  3162. ocp2scp@4a0ad000 {
  3163. compatible = "ti,omap-ocp2scp";
  3164. reg = <0x4a0ad000 0x1f>;
  3165. #address-cells = <0x1>;
  3166. #size-cells = <0x1>;
  3167. ranges;
  3168. ti,hwmods = "ocp2scp_usb_phy";
  3169.  
  3170. usb2phy@4a0ad080 {
  3171. compatible = "ti,omap-usb2";
  3172. reg = <0x4a0ad080 0x58>;
  3173. ctrl-module = <0x97>;
  3174. clocks = <0x98>;
  3175. clock-names = "wkupclk";
  3176. #phy-cells = <0x0>;
  3177. linux,phandle = <0x9a>;
  3178. phandle = <0x9a>;
  3179. };
  3180. };
  3181.  
  3182. mailbox@4a0f4000 {
  3183. compatible = "ti,omap4-mailbox";
  3184. reg = <0x4a0f4000 0x200>;
  3185. interrupts = <0x0 0x1a 0x4>;
  3186. ti,hwmods = "mailbox";
  3187. #mbox-cells = <0x1>;
  3188. ti,mbox-num-users = <0x3>;
  3189. ti,mbox-num-fifos = <0x8>;
  3190. linux,phandle = <0x145>;
  3191. phandle = <0x145>;
  3192.  
  3193. mbox_ipu {
  3194. ti,mbox-tx = <0x0 0x0 0x0>;
  3195. ti,mbox-rx = <0x1 0x0 0x0>;
  3196. linux,phandle = <0x146>;
  3197. phandle = <0x146>;
  3198. };
  3199.  
  3200. mbox_dsp {
  3201. ti,mbox-tx = <0x3 0x0 0x0>;
  3202. ti,mbox-rx = <0x2 0x0 0x0>;
  3203. linux,phandle = <0x147>;
  3204. phandle = <0x147>;
  3205. };
  3206. };
  3207.  
  3208. timer@4a318000 {
  3209. compatible = "ti,omap3430-timer";
  3210. reg = <0x4a318000 0x80>;
  3211. interrupts = <0x0 0x25 0x4>;
  3212. ti,hwmods = "timer1";
  3213. ti,timer-alwon;
  3214. linux,phandle = <0x148>;
  3215. phandle = <0x148>;
  3216. };
  3217.  
  3218. timer@48032000 {
  3219. compatible = "ti,omap3430-timer";
  3220. reg = <0x48032000 0x80>;
  3221. interrupts = <0x0 0x26 0x4>;
  3222. ti,hwmods = "timer2";
  3223. linux,phandle = <0x149>;
  3224. phandle = <0x149>;
  3225. };
  3226.  
  3227. timer@48034000 {
  3228. compatible = "ti,omap4430-timer";
  3229. reg = <0x48034000 0x80>;
  3230. interrupts = <0x0 0x27 0x4>;
  3231. ti,hwmods = "timer3";
  3232. linux,phandle = <0x14a>;
  3233. phandle = <0x14a>;
  3234. };
  3235.  
  3236. timer@48036000 {
  3237. compatible = "ti,omap4430-timer";
  3238. reg = <0x48036000 0x80>;
  3239. interrupts = <0x0 0x28 0x4>;
  3240. ti,hwmods = "timer4";
  3241. linux,phandle = <0x14b>;
  3242. phandle = <0x14b>;
  3243. };
  3244.  
  3245. timer@40138000 {
  3246. compatible = "ti,omap4430-timer";
  3247. reg = <0x40138000 0x80 0x49038000 0x80>;
  3248. interrupts = <0x0 0x29 0x4>;
  3249. ti,hwmods = "timer5";
  3250. ti,timer-dsp;
  3251. linux,phandle = <0x14c>;
  3252. phandle = <0x14c>;
  3253. };
  3254.  
  3255. timer@4013a000 {
  3256. compatible = "ti,omap4430-timer";
  3257. reg = <0x4013a000 0x80 0x4903a000 0x80>;
  3258. interrupts = <0x0 0x2a 0x4>;
  3259. ti,hwmods = "timer6";
  3260. ti,timer-dsp;
  3261. linux,phandle = <0x14d>;
  3262. phandle = <0x14d>;
  3263. };
  3264.  
  3265. timer@4013c000 {
  3266. compatible = "ti,omap4430-timer";
  3267. reg = <0x4013c000 0x80 0x4903c000 0x80>;
  3268. interrupts = <0x0 0x2b 0x4>;
  3269. ti,hwmods = "timer7";
  3270. ti,timer-dsp;
  3271. linux,phandle = <0x14e>;
  3272. phandle = <0x14e>;
  3273. };
  3274.  
  3275. timer@4013e000 {
  3276. compatible = "ti,omap4430-timer";
  3277. reg = <0x4013e000 0x80 0x4903e000 0x80>;
  3278. interrupts = <0x0 0x2c 0x4>;
  3279. ti,hwmods = "timer8";
  3280. ti,timer-pwm;
  3281. ti,timer-dsp;
  3282. linux,phandle = <0x14f>;
  3283. phandle = <0x14f>;
  3284. };
  3285.  
  3286. timer@4803e000 {
  3287. compatible = "ti,omap4430-timer";
  3288. reg = <0x4803e000 0x80>;
  3289. interrupts = <0x0 0x2d 0x4>;
  3290. ti,hwmods = "timer9";
  3291. ti,timer-pwm;
  3292. linux,phandle = <0x150>;
  3293. phandle = <0x150>;
  3294. };
  3295.  
  3296. timer@48086000 {
  3297. compatible = "ti,omap3430-timer";
  3298. reg = <0x48086000 0x80>;
  3299. interrupts = <0x0 0x2e 0x4>;
  3300. ti,hwmods = "timer10";
  3301. ti,timer-pwm;
  3302. linux,phandle = <0x151>;
  3303. phandle = <0x151>;
  3304. };
  3305.  
  3306. timer@48088000 {
  3307. compatible = "ti,omap4430-timer";
  3308. reg = <0x48088000 0x80>;
  3309. interrupts = <0x0 0x2f 0x4>;
  3310. ti,hwmods = "timer11";
  3311. ti,timer-pwm;
  3312. linux,phandle = <0x152>;
  3313. phandle = <0x152>;
  3314. };
  3315.  
  3316. usbhstll@4a062000 {
  3317. compatible = "ti,usbhs-tll";
  3318. reg = <0x4a062000 0x1000>;
  3319. interrupts = <0x0 0x4e 0x4>;
  3320. ti,hwmods = "usb_tll_hs";
  3321. linux,phandle = <0x153>;
  3322. phandle = <0x153>;
  3323. };
  3324.  
  3325. usbhshost@4a064000 {
  3326. compatible = "ti,usbhs-host";
  3327. reg = <0x4a064000 0x800>;
  3328. ti,hwmods = "usb_host_hs";
  3329. #address-cells = <0x1>;
  3330. #size-cells = <0x1>;
  3331. ranges;
  3332. clocks = <0x48 0x49 0x4b>;
  3333. clock-names = "refclk_60m_int", "refclk_60m_ext_p1", "refclk_60m_ext_p2";
  3334. port1-mode = "ehci-phy";
  3335. linux,phandle = <0x154>;
  3336. phandle = <0x154>;
  3337.  
  3338. ohci@4a064800 {
  3339. compatible = "ti,ohci-omap3";
  3340. reg = <0x4a064800 0x400>;
  3341. interrupt-parent = <0x4>;
  3342. interrupts = <0x0 0x4c 0x4>;
  3343. linux,phandle = <0x155>;
  3344. phandle = <0x155>;
  3345. };
  3346.  
  3347. ehci@4a064c00 {
  3348. compatible = "ti,ehci-omap";
  3349. reg = <0x4a064c00 0x400>;
  3350. interrupt-parent = <0x4>;
  3351. interrupts = <0x0 0x4d 0x4>;
  3352. phys = <0x99>;
  3353. linux,phandle = <0x156>;
  3354. phandle = <0x156>;
  3355. };
  3356. };
  3357.  
  3358. control-phy@4a002300 {
  3359. compatible = "ti,control-phy-usb2";
  3360. reg = <0x4a002300 0x4>;
  3361. reg-names = "power";
  3362. linux,phandle = <0x97>;
  3363. phandle = <0x97>;
  3364. };
  3365.  
  3366. control-phy@4a00233c {
  3367. compatible = "ti,control-phy-otghs";
  3368. reg = <0x4a00233c 0x4>;
  3369. reg-names = "otghs_control";
  3370. linux,phandle = <0x9b>;
  3371. phandle = <0x9b>;
  3372. };
  3373.  
  3374. usb_otg_hs@4a0ab000 {
  3375. compatible = "ti,omap4-musb";
  3376. reg = <0x4a0ab000 0x7ff>;
  3377. interrupts = <0x0 0x5c 0x4 0x0 0x5d 0x4>;
  3378. interrupt-names = "mc", "dma";
  3379. ti,hwmods = "usb_otg_hs";
  3380. usb-phy = <0x9a>;
  3381. phys = <0x9a>;
  3382. phy-names = "usb2-phy";
  3383. multipoint = <0x1>;
  3384. num-eps = <0x10>;
  3385. ram-bits = <0xc>;
  3386. ctrl-module = <0x9b>;
  3387. interface-type = <0x1>;
  3388. mode = <0x3>;
  3389. power = <0x32>;
  3390. linux,phandle = <0x157>;
  3391. phandle = <0x157>;
  3392. };
  3393.  
  3394. aes@4b501000 {
  3395. compatible = "ti,omap4-aes";
  3396. ti,hwmods = "aes";
  3397. reg = <0x4b501000 0xa0>;
  3398. interrupts = <0x0 0x55 0x4>;
  3399. dmas = <0x8e 0x6f 0x8e 0x6e>;
  3400. dma-names = "tx", "rx";
  3401. linux,phandle = <0x158>;
  3402. phandle = <0x158>;
  3403. };
  3404.  
  3405. des@480a5000 {
  3406. compatible = "ti,omap4-des";
  3407. ti,hwmods = "des";
  3408. reg = <0x480a5000 0xa0>;
  3409. interrupts = <0x0 0x52 0x4>;
  3410. dmas = <0x8e 0x75 0x8e 0x74>;
  3411. dma-names = "tx", "rx";
  3412. linux,phandle = <0x159>;
  3413. phandle = <0x159>;
  3414. };
  3415.  
  3416. regulator-abb-mpu {
  3417. compatible = "ti,abb-v2";
  3418. regulator-name = "abb_mpu";
  3419. #address-cells = <0x0>;
  3420. #size-cells = <0x0>;
  3421. ti,tranxdone-status-mask = <0x80>;
  3422. clocks = <0xf>;
  3423. ti,settling-time = <0x32>;
  3424. ti,clock-cycles = <0x10>;
  3425. status = "okay";
  3426. reg = <0x4a307bd0 0x8 0x4a306014 0x4 0x4a002268 0x4>;
  3427. reg-names = "base-address", "int-address", "efuse-address";
  3428. ti,abb_info = <0xfa3e8 0x0 0x0 0x0 0x0 0x0 0x124f80 0x0 0x0 0x0 0x0 0x0 0x1408e8 0x0 0x0 0x100000 0x40000 0x0 0x14fb18 0x1 0x0 0x0 0x0 0x0 0x1531c8 0x1 0x0 0x0 0x0 0x0>;
  3429. linux,phandle = <0x15a>;
  3430. phandle = <0x15a>;
  3431. };
  3432.  
  3433. regulator-abb-iva {
  3434. compatible = "ti,abb-v2";
  3435. regulator-name = "abb_iva";
  3436. #address-cells = <0x0>;
  3437. #size-cells = <0x0>;
  3438. ti,tranxdone-status-mask = <0x80000000>;
  3439. clocks = <0xf>;
  3440. ti,settling-time = <0x32>;
  3441. ti,clock-cycles = <0x10>;
  3442. status = "okay";
  3443. reg = <0x4a307bd8 0x8 0x4a306010 0x4 0x4a002268 0x4>;
  3444. reg-names = "base-address", "int-address", "efuse-address";
  3445. ti,abb_info = <0xe7ef0 0x0 0x0 0x0 0x0 0x0 0x116520 0x0 0x0 0x0 0x0 0x0 0x13b2f8 0x0 0x0 0x200000 0x0 0x0 0x14fb18 0x1 0x0 0x0 0x0 0x0 0x14ff00 0x1 0x0 0x0 0x0 0x0>;
  3446. linux,phandle = <0x15b>;
  3447. phandle = <0x15b>;
  3448. };
  3449.  
  3450. dss@58000000 {
  3451. compatible = "ti,omap4-dss";
  3452. reg = <0x58000000 0x80>;
  3453. status = "ok";
  3454. ti,hwmods = "dss_core";
  3455. clocks = <0x9c>;
  3456. clock-names = "fck";
  3457. #address-cells = <0x1>;
  3458. #size-cells = <0x1>;
  3459. ranges;
  3460. linux,phandle = <0x15c>;
  3461. phandle = <0x15c>;
  3462.  
  3463. dispc@58001000 {
  3464. compatible = "ti,omap4-dispc";
  3465. reg = <0x58001000 0x1000>;
  3466. interrupts = <0x0 0x19 0x4>;
  3467. ti,hwmods = "dss_dispc";
  3468. clocks = <0x9c>;
  3469. clock-names = "fck";
  3470. };
  3471.  
  3472. encoder@58002000 {
  3473. compatible = "ti,omap4-rfbi";
  3474. reg = <0x58002000 0x1000>;
  3475. status = "disabled";
  3476. ti,hwmods = "dss_rfbi";
  3477. clocks = <0x9c 0x1f>;
  3478. clock-names = "fck", "ick";
  3479. linux,phandle = <0x15d>;
  3480. phandle = <0x15d>;
  3481. };
  3482.  
  3483. encoder@58003000 {
  3484. compatible = "ti,omap4-venc";
  3485. reg = <0x58003000 0x1000>;
  3486. status = "disabled";
  3487. ti,hwmods = "dss_venc";
  3488. clocks = <0x9d>;
  3489. clock-names = "fck";
  3490. linux,phandle = <0x15e>;
  3491. phandle = <0x15e>;
  3492. };
  3493.  
  3494. encoder@58004000 {
  3495. compatible = "ti,omap4-dsi";
  3496. reg = <0x58004000 0x200 0x58004200 0x40 0x58004300 0x20>;
  3497. reg-names = "proto", "phy", "pll";
  3498. interrupts = <0x0 0x35 0x4>;
  3499. status = "disabled";
  3500. ti,hwmods = "dss_dsi1";
  3501. clocks = <0x9c 0x9e>;
  3502. clock-names = "fck", "sys_clk";
  3503. linux,phandle = <0x15f>;
  3504. phandle = <0x15f>;
  3505. };
  3506.  
  3507. encoder@58005000 {
  3508. compatible = "ti,omap4-dsi";
  3509. reg = <0x58005000 0x200 0x58005200 0x40 0x58005300 0x20>;
  3510. reg-names = "proto", "phy", "pll";
  3511. interrupts = <0x0 0x54 0x4>;
  3512. status = "ok";
  3513. ti,hwmods = "dss_dsi2";
  3514. clocks = <0x9c 0x9e>;
  3515. clock-names = "fck", "sys_clk";
  3516. vdd-supply = <0x9f>;
  3517. linux,phandle = <0x160>;
  3518. phandle = <0x160>;
  3519. };
  3520.  
  3521. encoder@58006000 {
  3522. compatible = "ti,omap4-hdmi";
  3523. reg = <0x58006000 0x200 0x58006200 0x100 0x58006300 0x100 0x58006400 0x1000>;
  3524. reg-names = "wp", "pll", "phy", "core";
  3525. interrupts = <0x0 0x65 0x4>;
  3526. status = "ok";
  3527. ti,hwmods = "dss_hdmi";
  3528. clocks = <0xa0 0x9e>;
  3529. clock-names = "fck", "sys_clk";
  3530. dmas = <0x8e 0x4c>;
  3531. dma-names = "audio_tx";
  3532. vdda-supply = <0xa1>;
  3533. linux,phandle = <0x161>;
  3534. phandle = <0x161>;
  3535.  
  3536. port {
  3537.  
  3538. endpoint {
  3539. remote-endpoint = <0xa2>;
  3540. linux,phandle = <0xb3>;
  3541. phandle = <0xb3>;
  3542. };
  3543. };
  3544. };
  3545.  
  3546. port {
  3547.  
  3548. endpoint {
  3549. remote-endpoint = <0xa3>;
  3550. data-lines = <0x18>;
  3551. linux,phandle = <0xaf>;
  3552. phandle = <0xaf>;
  3553. };
  3554. };
  3555. };
  3556.  
  3557. bandgap {
  3558. reg = <0x4a002260 0x4 0x4a00232c 0x4 0x4a002378 0x18>;
  3559. compatible = "ti,omap4460-bandgap";
  3560. interrupts = <0x0 0x7e 0x4>;
  3561. gpios = <0xa4 0x16 0x0>;
  3562. #thermal-sensor-cells = <0x0>;
  3563. linux,phandle = <0xa5>;
  3564. phandle = <0xa5>;
  3565. };
  3566. };
  3567.  
  3568. pmu {
  3569. compatible = "arm,cortex-a9-pmu";
  3570. interrupts = <0x0 0x36 0x4 0x0 0x37 0x4>;
  3571. ti,hwmods = "debugss";
  3572. };
  3573.  
  3574. thermal-zones {
  3575.  
  3576. cpu_thermal {
  3577. polling-delay-passive = <0xfa>;
  3578. polling-delay = <0x3e8>;
  3579. thermal-sensors = <0xa5 0x0>;
  3580. linux,phandle = <0x162>;
  3581. phandle = <0x162>;
  3582.  
  3583. trips {
  3584. linux,phandle = <0x163>;
  3585. phandle = <0x163>;
  3586.  
  3587. cpu_alert {
  3588. temperature = <0x186a0>;
  3589. hysteresis = <0x7d0>;
  3590. type = "passive";
  3591. linux,phandle = <0xa6>;
  3592. phandle = <0xa6>;
  3593. };
  3594.  
  3595. cpu_crit {
  3596. temperature = <0x1e848>;
  3597. hysteresis = <0x7d0>;
  3598. type = "critical";
  3599. linux,phandle = <0x164>;
  3600. phandle = <0x164>;
  3601. };
  3602. };
  3603.  
  3604. cooling-maps {
  3605. linux,phandle = <0x165>;
  3606. phandle = <0x165>;
  3607.  
  3608. map0 {
  3609. trip = <0xa6>;
  3610. cooling-device = <0xa7 0xffffffff 0xffffffff>;
  3611. };
  3612. };
  3613. };
  3614. };
  3615.  
  3616. lpddr2 {
  3617. compatible = "Elpida,ECB240ABACN", "jedec,lpddr2-s4";
  3618. density = <0x800>;
  3619. io-width = <0x20>;
  3620. tRPab-min-tck = <0x3>;
  3621. tRCD-min-tck = <0x3>;
  3622. tWR-min-tck = <0x3>;
  3623. tRASmin-min-tck = <0x3>;
  3624. tRRD-min-tck = <0x2>;
  3625. tWTR-min-tck = <0x2>;
  3626. tXP-min-tck = <0x2>;
  3627. tRTP-min-tck = <0x2>;
  3628. tCKE-min-tck = <0x3>;
  3629. tCKESR-min-tck = <0x3>;
  3630. tFAW-min-tck = <0x8>;
  3631. linux,phandle = <0x96>;
  3632. phandle = <0x96>;
  3633.  
  3634. lpddr2-timings@0 {
  3635. compatible = "jedec,lpddr2-timings";
  3636. min-freq = <0x989680>;
  3637. max-freq = <0x17d78400>;
  3638. tRPab = <0x5208>;
  3639. tRCD = <0x4650>;
  3640. tWR = <0x3a98>;
  3641. tRAS-min = <0xa410>;
  3642. tRRD = <0x2710>;
  3643. tWTR = <0x1d4c>;
  3644. tXP = <0x1d4c>;
  3645. tRTP = <0x1d4c>;
  3646. tCKESR = <0x3a98>;
  3647. tDQSCK-max = <0x157c>;
  3648. tFAW = <0xc350>;
  3649. tZQCS = <0x15f90>;
  3650. tZQCL = <0x57e40>;
  3651. tZQinit = <0xf4240>;
  3652. tRAS-max-ns = <0x11170>;
  3653. tDQSCK-max-derated = <0x1770>;
  3654. linux,phandle = <0x166>;
  3655. phandle = <0x166>;
  3656. };
  3657.  
  3658. lpddr2-timings@1 {
  3659. compatible = "jedec,lpddr2-timings";
  3660. min-freq = <0x989680>;
  3661. max-freq = <0xbebc200>;
  3662. tRPab = <0x5208>;
  3663. tRCD = <0x4650>;
  3664. tWR = <0x3a98>;
  3665. tRAS-min = <0xa410>;
  3666. tRRD = <0x2710>;
  3667. tWTR = <0x2710>;
  3668. tXP = <0x1d4c>;
  3669. tRTP = <0x1d4c>;
  3670. tCKESR = <0x3a98>;
  3671. tDQSCK-max = <0x157c>;
  3672. tFAW = <0xc350>;
  3673. tZQCS = <0x15f90>;
  3674. tZQCL = <0x57e40>;
  3675. tZQinit = <0xf4240>;
  3676. tRAS-max-ns = <0x11170>;
  3677. tDQSCK-max-derated = <0x1770>;
  3678. linux,phandle = <0x167>;
  3679. phandle = <0x167>;
  3680. };
  3681. };
  3682.  
  3683. leds {
  3684. compatible = "gpio-leds";
  3685. pinctrl-names = "default";
  3686. pinctrl-0 = <0xa8 0xa9>;
  3687. linux,phandle = <0x168>;
  3688. phandle = <0x168>;
  3689.  
  3690. heartbeat {
  3691. label = "pandaboard::status1";
  3692. gpios = <0x88 0xe 0x0>;
  3693. linux,default-trigger = "heartbeat";
  3694. };
  3695.  
  3696. mmc {
  3697. label = "pandaboard::status2";
  3698. gpios = <0xaa 0x8 0x0>;
  3699. linux,default-trigger = "mmc0";
  3700. };
  3701. };
  3702.  
  3703. sound {
  3704. compatible = "ti,abe-twl6040";
  3705. ti,model = "PandaBoardES";
  3706. ti,mclk-freq = <0x249f000>;
  3707. ti,mcpdm = <0xab>;
  3708. ti,twl6040 = <0xac>;
  3709. ti,audio-routing = "Headset Stereophone", "HSOL", "Headset Stereophone", "HSOR", "Ext Spk", "HFL", "Ext Spk", "HFR", "Line Out", "AUXL", "Line Out", "AUXR", "AFML", "Line In", "AFMR", "Line In";
  3710. linux,phandle = <0x169>;
  3711. phandle = <0x169>;
  3712. };
  3713.  
  3714. hsusb1_power_reg {
  3715. compatible = "regulator-fixed";
  3716. regulator-name = "hsusb1_vbus";
  3717. regulator-min-microvolt = <0x325aa0>;
  3718. regulator-max-microvolt = <0x325aa0>;
  3719. gpio = <0xaa 0x1 0x0>;
  3720. startup-delay-us = <0x11170>;
  3721. enable-active-high;
  3722. regulator-always-on;
  3723. regulator-boot-on;
  3724. linux,phandle = <0xad>;
  3725. phandle = <0xad>;
  3726. };
  3727.  
  3728. hsusb1_phy {
  3729. compatible = "usb-nop-xceiv";
  3730. reset-gpios = <0x93 0x1e 0x1>;
  3731. vcc-supply = <0xad>;
  3732. clocks = <0x7f>;
  3733. clock-names = "main_clk";
  3734. clock-frequency = <0x124f800>;
  3735. linux,phandle = <0x99>;
  3736. phandle = <0x99>;
  3737. };
  3738.  
  3739. wl12xx_vmmc {
  3740. pinctrl-names = "default";
  3741. pinctrl-0 = <0xae>;
  3742. compatible = "regulator-fixed";
  3743. regulator-name = "vwl1271";
  3744. regulator-min-microvolt = <0x1b7740>;
  3745. regulator-max-microvolt = <0x1b7740>;
  3746. gpio = <0x93 0xb 0x0>;
  3747. startup-delay-us = <0x11170>;
  3748. enable-active-high;
  3749. linux,phandle = <0x92>;
  3750. phandle = <0x92>;
  3751. };
  3752.  
  3753. encoder@0 {
  3754. compatible = "ti,tfp410";
  3755. powerdown-gpios = <0xaa 0x0 0x1>;
  3756. linux,phandle = <0x16a>;
  3757. phandle = <0x16a>;
  3758.  
  3759. ports {
  3760. #address-cells = <0x1>;
  3761. #size-cells = <0x0>;
  3762.  
  3763. port@0 {
  3764. reg = <0x0>;
  3765.  
  3766. endpoint@0 {
  3767. remote-endpoint = <0xaf>;
  3768. linux,phandle = <0xa3>;
  3769. phandle = <0xa3>;
  3770. };
  3771. };
  3772.  
  3773. port@1 {
  3774. reg = <0x1>;
  3775.  
  3776. endpoint@0 {
  3777. remote-endpoint = <0xb0>;
  3778. linux,phandle = <0xb2>;
  3779. phandle = <0xb2>;
  3780. };
  3781. };
  3782. };
  3783. };
  3784.  
  3785. connector@0 {
  3786. compatible = "dvi-connector";
  3787. label = "dvi";
  3788. digital;
  3789. ddc-i2c-bus = <0xb1>;
  3790. linux,phandle = <0x16b>;
  3791. phandle = <0x16b>;
  3792.  
  3793. port {
  3794.  
  3795. endpoint {
  3796. remote-endpoint = <0xb2>;
  3797. linux,phandle = <0xb0>;
  3798. phandle = <0xb0>;
  3799. };
  3800. };
  3801. };
  3802.  
  3803. encoder@1 {
  3804. compatible = "ti,tpd12s015";
  3805. gpios = <0x93 0x1c 0x0 0x93 0x9 0x0 0x93 0x1f 0x0>;
  3806. linux,phandle = <0x16c>;
  3807. phandle = <0x16c>;
  3808.  
  3809. ports {
  3810. #address-cells = <0x1>;
  3811. #size-cells = <0x0>;
  3812.  
  3813. port@0 {
  3814. reg = <0x0>;
  3815.  
  3816. endpoint@0 {
  3817. remote-endpoint = <0xb3>;
  3818. linux,phandle = <0xa2>;
  3819. phandle = <0xa2>;
  3820. };
  3821. };
  3822.  
  3823. port@1 {
  3824. reg = <0x1>;
  3825.  
  3826. endpoint@0 {
  3827. remote-endpoint = <0xb4>;
  3828. linux,phandle = <0xb5>;
  3829. phandle = <0xb5>;
  3830. };
  3831. };
  3832. };
  3833. };
  3834.  
  3835. connector@1 {
  3836. compatible = "hdmi-connector";
  3837. label = "hdmi";
  3838. type = [61 00];
  3839. linux,phandle = <0x16d>;
  3840. phandle = <0x16d>;
  3841.  
  3842. port {
  3843.  
  3844. endpoint {
  3845. remote-endpoint = <0xb5>;
  3846. linux,phandle = <0xb4>;
  3847. phandle = <0xb4>;
  3848. };
  3849. };
  3850. };
  3851.  
  3852. __symbols__ {
  3853. cpu0 = "/cpus/cpu@0";
  3854. gic = "/interrupt-controller@48241000";
  3855. L2 = "/l2-cache-controller@48242000";
  3856. wakeupgen = "/interrupt-controller@48281000";
  3857. l4_cfg = "/ocp/l4@4a000000";
  3858. cm1 = "/ocp/l4@4a000000/cm1@4000";
  3859. cm1_clocks = "/ocp/l4@4a000000/cm1@4000/clocks";
  3860. extalt_clkin_ck = "/ocp/l4@4a000000/cm1@4000/clocks/extalt_clkin_ck";
  3861. pad_clks_src_ck = "/ocp/l4@4a000000/cm1@4000/clocks/pad_clks_src_ck";
  3862. pad_clks_ck = "/ocp/l4@4a000000/cm1@4000/clocks/pad_clks_ck";
  3863. pad_slimbus_core_clks_ck = "/ocp/l4@4a000000/cm1@4000/clocks/pad_slimbus_core_clks_ck";
  3864. secure_32k_clk_src_ck = "/ocp/l4@4a000000/cm1@4000/clocks/secure_32k_clk_src_ck";
  3865. slimbus_src_clk = "/ocp/l4@4a000000/cm1@4000/clocks/slimbus_src_clk";
  3866. slimbus_clk = "/ocp/l4@4a000000/cm1@4000/clocks/slimbus_clk";
  3867. sys_32k_ck = "/ocp/l4@4a000000/cm1@4000/clocks/sys_32k_ck";
  3868. virt_12000000_ck = "/ocp/l4@4a000000/cm1@4000/clocks/virt_12000000_ck";
  3869. virt_13000000_ck = "/ocp/l4@4a000000/cm1@4000/clocks/virt_13000000_ck";
  3870. virt_16800000_ck = "/ocp/l4@4a000000/cm1@4000/clocks/virt_16800000_ck";
  3871. virt_19200000_ck = "/ocp/l4@4a000000/cm1@4000/clocks/virt_19200000_ck";
  3872. virt_26000000_ck = "/ocp/l4@4a000000/cm1@4000/clocks/virt_26000000_ck";
  3873. virt_27000000_ck = "/ocp/l4@4a000000/cm1@4000/clocks/virt_27000000_ck";
  3874. virt_38400000_ck = "/ocp/l4@4a000000/cm1@4000/clocks/virt_38400000_ck";
  3875. tie_low_clock_ck = "/ocp/l4@4a000000/cm1@4000/clocks/tie_low_clock_ck";
  3876. utmi_phy_clkout_ck = "/ocp/l4@4a000000/cm1@4000/clocks/utmi_phy_clkout_ck";
  3877. xclk60mhsp1_ck = "/ocp/l4@4a000000/cm1@4000/clocks/xclk60mhsp1_ck";
  3878. xclk60mhsp2_ck = "/ocp/l4@4a000000/cm1@4000/clocks/xclk60mhsp2_ck";
  3879. xclk60motg_ck = "/ocp/l4@4a000000/cm1@4000/clocks/xclk60motg_ck";
  3880. dpll_abe_ck = "/ocp/l4@4a000000/cm1@4000/clocks/dpll_abe_ck";
  3881. dpll_abe_x2_ck = "/ocp/l4@4a000000/cm1@4000/clocks/dpll_abe_x2_ck";
  3882. dpll_abe_m2x2_ck = "/ocp/l4@4a000000/cm1@4000/clocks/dpll_abe_m2x2_ck";
  3883. abe_24m_fclk = "/ocp/l4@4a000000/cm1@4000/clocks/abe_24m_fclk";
  3884. abe_clk = "/ocp/l4@4a000000/cm1@4000/clocks/abe_clk";
  3885. aess_fclk = "/ocp/l4@4a000000/cm1@4000/clocks/aess_fclk";
  3886. dpll_abe_m3x2_ck = "/ocp/l4@4a000000/cm1@4000/clocks/dpll_abe_m3x2_ck";
  3887. core_hsd_byp_clk_mux_ck = "/ocp/l4@4a000000/cm1@4000/clocks/core_hsd_byp_clk_mux_ck";
  3888. dpll_core_ck = "/ocp/l4@4a000000/cm1@4000/clocks/dpll_core_ck";
  3889. dpll_core_x2_ck = "/ocp/l4@4a000000/cm1@4000/clocks/dpll_core_x2_ck";
  3890. dpll_core_m6x2_ck = "/ocp/l4@4a000000/cm1@4000/clocks/dpll_core_m6x2_ck";
  3891. dpll_core_m2_ck = "/ocp/l4@4a000000/cm1@4000/clocks/dpll_core_m2_ck";
  3892. ddrphy_ck = "/ocp/l4@4a000000/cm1@4000/clocks/ddrphy_ck";
  3893. dpll_core_m5x2_ck = "/ocp/l4@4a000000/cm1@4000/clocks/dpll_core_m5x2_ck";
  3894. div_core_ck = "/ocp/l4@4a000000/cm1@4000/clocks/div_core_ck";
  3895. div_iva_hs_clk = "/ocp/l4@4a000000/cm1@4000/clocks/div_iva_hs_clk";
  3896. div_mpu_hs_clk = "/ocp/l4@4a000000/cm1@4000/clocks/div_mpu_hs_clk";
  3897. dpll_core_m4x2_ck = "/ocp/l4@4a000000/cm1@4000/clocks/dpll_core_m4x2_ck";
  3898. dll_clk_div_ck = "/ocp/l4@4a000000/cm1@4000/clocks/dll_clk_div_ck";
  3899. dpll_abe_m2_ck = "/ocp/l4@4a000000/cm1@4000/clocks/dpll_abe_m2_ck";
  3900. dpll_core_m3x2_gate_ck = "/ocp/l4@4a000000/cm1@4000/clocks/dpll_core_m3x2_gate_ck";
  3901. dpll_core_m3x2_div_ck = "/ocp/l4@4a000000/cm1@4000/clocks/dpll_core_m3x2_div_ck";
  3902. dpll_core_m3x2_ck = "/ocp/l4@4a000000/cm1@4000/clocks/dpll_core_m3x2_ck";
  3903. dpll_core_m7x2_ck = "/ocp/l4@4a000000/cm1@4000/clocks/dpll_core_m7x2_ck";
  3904. iva_hsd_byp_clk_mux_ck = "/ocp/l4@4a000000/cm1@4000/clocks/iva_hsd_byp_clk_mux_ck";
  3905. dpll_iva_ck = "/ocp/l4@4a000000/cm1@4000/clocks/dpll_iva_ck";
  3906. dpll_iva_x2_ck = "/ocp/l4@4a000000/cm1@4000/clocks/dpll_iva_x2_ck";
  3907. dpll_iva_m4x2_ck = "/ocp/l4@4a000000/cm1@4000/clocks/dpll_iva_m4x2_ck";
  3908. dpll_iva_m5x2_ck = "/ocp/l4@4a000000/cm1@4000/clocks/dpll_iva_m5x2_ck";
  3909. dpll_mpu_ck = "/ocp/l4@4a000000/cm1@4000/clocks/dpll_mpu_ck";
  3910. dpll_mpu_m2_ck = "/ocp/l4@4a000000/cm1@4000/clocks/dpll_mpu_m2_ck";
  3911. per_hs_clk_div_ck = "/ocp/l4@4a000000/cm1@4000/clocks/per_hs_clk_div_ck";
  3912. usb_hs_clk_div_ck = "/ocp/l4@4a000000/cm1@4000/clocks/usb_hs_clk_div_ck";
  3913. l3_div_ck = "/ocp/l4@4a000000/cm1@4000/clocks/l3_div_ck";
  3914. l4_div_ck = "/ocp/l4@4a000000/cm1@4000/clocks/l4_div_ck";
  3915. lp_clk_div_ck = "/ocp/l4@4a000000/cm1@4000/clocks/lp_clk_div_ck";
  3916. mpu_periphclk = "/ocp/l4@4a000000/cm1@4000/clocks/mpu_periphclk";
  3917. ocp_abe_iclk = "/ocp/l4@4a000000/cm1@4000/clocks/ocp_abe_iclk";
  3918. per_abe_24m_fclk = "/ocp/l4@4a000000/cm1@4000/clocks/per_abe_24m_fclk";
  3919. dmic_sync_mux_ck = "/ocp/l4@4a000000/cm1@4000/clocks/dmic_sync_mux_ck";
  3920. func_dmic_abe_gfclk = "/ocp/l4@4a000000/cm1@4000/clocks/func_dmic_abe_gfclk";
  3921. mcasp_sync_mux_ck = "/ocp/l4@4a000000/cm1@4000/clocks/mcasp_sync_mux_ck";
  3922. func_mcasp_abe_gfclk = "/ocp/l4@4a000000/cm1@4000/clocks/func_mcasp_abe_gfclk";
  3923. mcbsp1_sync_mux_ck = "/ocp/l4@4a000000/cm1@4000/clocks/mcbsp1_sync_mux_ck";
  3924. func_mcbsp1_gfclk = "/ocp/l4@4a000000/cm1@4000/clocks/func_mcbsp1_gfclk";
  3925. mcbsp2_sync_mux_ck = "/ocp/l4@4a000000/cm1@4000/clocks/mcbsp2_sync_mux_ck";
  3926. func_mcbsp2_gfclk = "/ocp/l4@4a000000/cm1@4000/clocks/func_mcbsp2_gfclk";
  3927. mcbsp3_sync_mux_ck = "/ocp/l4@4a000000/cm1@4000/clocks/mcbsp3_sync_mux_ck";
  3928. func_mcbsp3_gfclk = "/ocp/l4@4a000000/cm1@4000/clocks/func_mcbsp3_gfclk";
  3929. slimbus1_fclk_1 = "/ocp/l4@4a000000/cm1@4000/clocks/slimbus1_fclk_1";
  3930. slimbus1_fclk_0 = "/ocp/l4@4a000000/cm1@4000/clocks/slimbus1_fclk_0";
  3931. slimbus1_fclk_2 = "/ocp/l4@4a000000/cm1@4000/clocks/slimbus1_fclk_2";
  3932. slimbus1_slimbus_clk = "/ocp/l4@4a000000/cm1@4000/clocks/slimbus1_slimbus_clk";
  3933. timer5_sync_mux = "/ocp/l4@4a000000/cm1@4000/clocks/timer5_sync_mux";
  3934. timer6_sync_mux = "/ocp/l4@4a000000/cm1@4000/clocks/timer6_sync_mux";
  3935. timer7_sync_mux = "/ocp/l4@4a000000/cm1@4000/clocks/timer7_sync_mux";
  3936. timer8_sync_mux = "/ocp/l4@4a000000/cm1@4000/clocks/timer8_sync_mux";
  3937. dummy_ck = "/ocp/l4@4a000000/cm1@4000/clocks/dummy_ck";
  3938. cm1_clockdomains = "/ocp/l4@4a000000/cm1@4000/clockdomains";
  3939. cm2 = "/ocp/l4@4a000000/cm2@8000";
  3940. cm2_clocks = "/ocp/l4@4a000000/cm2@8000/clocks";
  3941. per_hsd_byp_clk_mux_ck = "/ocp/l4@4a000000/cm2@8000/clocks/per_hsd_byp_clk_mux_ck";
  3942. dpll_per_ck = "/ocp/l4@4a000000/cm2@8000/clocks/dpll_per_ck";
  3943. dpll_per_m2_ck = "/ocp/l4@4a000000/cm2@8000/clocks/dpll_per_m2_ck";
  3944. dpll_per_x2_ck = "/ocp/l4@4a000000/cm2@8000/clocks/dpll_per_x2_ck";
  3945. dpll_per_m2x2_ck = "/ocp/l4@4a000000/cm2@8000/clocks/dpll_per_m2x2_ck";
  3946. dpll_per_m3x2_gate_ck = "/ocp/l4@4a000000/cm2@8000/clocks/dpll_per_m3x2_gate_ck";
  3947. dpll_per_m3x2_div_ck = "/ocp/l4@4a000000/cm2@8000/clocks/dpll_per_m3x2_div_ck";
  3948. dpll_per_m3x2_ck = "/ocp/l4@4a000000/cm2@8000/clocks/dpll_per_m3x2_ck";
  3949. dpll_per_m4x2_ck = "/ocp/l4@4a000000/cm2@8000/clocks/dpll_per_m4x2_ck";
  3950. dpll_per_m5x2_ck = "/ocp/l4@4a000000/cm2@8000/clocks/dpll_per_m5x2_ck";
  3951. dpll_per_m6x2_ck = "/ocp/l4@4a000000/cm2@8000/clocks/dpll_per_m6x2_ck";
  3952. dpll_per_m7x2_ck = "/ocp/l4@4a000000/cm2@8000/clocks/dpll_per_m7x2_ck";
  3953. dpll_usb_ck = "/ocp/l4@4a000000/cm2@8000/clocks/dpll_usb_ck";
  3954. dpll_usb_clkdcoldo_ck = "/ocp/l4@4a000000/cm2@8000/clocks/dpll_usb_clkdcoldo_ck";
  3955. dpll_usb_m2_ck = "/ocp/l4@4a000000/cm2@8000/clocks/dpll_usb_m2_ck";
  3956. ducati_clk_mux_ck = "/ocp/l4@4a000000/cm2@8000/clocks/ducati_clk_mux_ck";
  3957. func_12m_fclk = "/ocp/l4@4a000000/cm2@8000/clocks/func_12m_fclk";
  3958. func_24m_clk = "/ocp/l4@4a000000/cm2@8000/clocks/func_24m_clk";
  3959. func_24mc_fclk = "/ocp/l4@4a000000/cm2@8000/clocks/func_24mc_fclk";
  3960. func_48m_fclk = "/ocp/l4@4a000000/cm2@8000/clocks/func_48m_fclk";
  3961. func_48mc_fclk = "/ocp/l4@4a000000/cm2@8000/clocks/func_48mc_fclk";
  3962. func_64m_fclk = "/ocp/l4@4a000000/cm2@8000/clocks/func_64m_fclk";
  3963. func_96m_fclk = "/ocp/l4@4a000000/cm2@8000/clocks/func_96m_fclk";
  3964. init_60m_fclk = "/ocp/l4@4a000000/cm2@8000/clocks/init_60m_fclk";
  3965. per_abe_nc_fclk = "/ocp/l4@4a000000/cm2@8000/clocks/per_abe_nc_fclk";
  3966. aes1_fck = "/ocp/l4@4a000000/cm2@8000/clocks/aes1_fck";
  3967. aes2_fck = "/ocp/l4@4a000000/cm2@8000/clocks/aes2_fck";
  3968. dss_sys_clk = "/ocp/l4@4a000000/cm2@8000/clocks/dss_sys_clk";
  3969. dss_tv_clk = "/ocp/l4@4a000000/cm2@8000/clocks/dss_tv_clk";
  3970. dss_dss_clk = "/ocp/l4@4a000000/cm2@8000/clocks/dss_dss_clk";
  3971. dss_48mhz_clk = "/ocp/l4@4a000000/cm2@8000/clocks/dss_48mhz_clk";
  3972. fdif_fck = "/ocp/l4@4a000000/cm2@8000/clocks/fdif_fck";
  3973. gpio2_dbclk = "/ocp/l4@4a000000/cm2@8000/clocks/gpio2_dbclk";
  3974. gpio3_dbclk = "/ocp/l4@4a000000/cm2@8000/clocks/gpio3_dbclk";
  3975. gpio4_dbclk = "/ocp/l4@4a000000/cm2@8000/clocks/gpio4_dbclk";
  3976. gpio5_dbclk = "/ocp/l4@4a000000/cm2@8000/clocks/gpio5_dbclk";
  3977. gpio6_dbclk = "/ocp/l4@4a000000/cm2@8000/clocks/gpio6_dbclk";
  3978. sgx_clk_mux = "/ocp/l4@4a000000/cm2@8000/clocks/sgx_clk_mux";
  3979. hsi_fck = "/ocp/l4@4a000000/cm2@8000/clocks/hsi_fck";
  3980. iss_ctrlclk = "/ocp/l4@4a000000/cm2@8000/clocks/iss_ctrlclk";
  3981. mcbsp4_sync_mux_ck = "/ocp/l4@4a000000/cm2@8000/clocks/mcbsp4_sync_mux_ck";
  3982. per_mcbsp4_gfclk = "/ocp/l4@4a000000/cm2@8000/clocks/per_mcbsp4_gfclk";
  3983. hsmmc1_fclk = "/ocp/l4@4a000000/cm2@8000/clocks/hsmmc1_fclk";
  3984. hsmmc2_fclk = "/ocp/l4@4a000000/cm2@8000/clocks/hsmmc2_fclk";
  3985. ocp2scp_usb_phy_phy_48m = "/ocp/l4@4a000000/cm2@8000/clocks/ocp2scp_usb_phy_phy_48m";
  3986. sha2md5_fck = "/ocp/l4@4a000000/cm2@8000/clocks/sha2md5_fck";
  3987. slimbus2_fclk_1 = "/ocp/l4@4a000000/cm2@8000/clocks/slimbus2_fclk_1";
  3988. slimbus2_fclk_0 = "/ocp/l4@4a000000/cm2@8000/clocks/slimbus2_fclk_0";
  3989. slimbus2_slimbus_clk = "/ocp/l4@4a000000/cm2@8000/clocks/slimbus2_slimbus_clk";
  3990. smartreflex_core_fck = "/ocp/l4@4a000000/cm2@8000/clocks/smartreflex_core_fck";
  3991. smartreflex_iva_fck = "/ocp/l4@4a000000/cm2@8000/clocks/smartreflex_iva_fck";
  3992. smartreflex_mpu_fck = "/ocp/l4@4a000000/cm2@8000/clocks/smartreflex_mpu_fck";
  3993. cm2_dm10_mux = "/ocp/l4@4a000000/cm2@8000/clocks/cm2_dm10_mux";
  3994. cm2_dm11_mux = "/ocp/l4@4a000000/cm2@8000/clocks/cm2_dm11_mux";
  3995. cm2_dm2_mux = "/ocp/l4@4a000000/cm2@8000/clocks/cm2_dm2_mux";
  3996. cm2_dm3_mux = "/ocp/l4@4a000000/cm2@8000/clocks/cm2_dm3_mux";
  3997. cm2_dm4_mux = "/ocp/l4@4a000000/cm2@8000/clocks/cm2_dm4_mux";
  3998. cm2_dm9_mux = "/ocp/l4@4a000000/cm2@8000/clocks/cm2_dm9_mux";
  3999. usb_host_fs_fck = "/ocp/l4@4a000000/cm2@8000/clocks/usb_host_fs_fck";
  4000. utmi_p1_gfclk = "/ocp/l4@4a000000/cm2@8000/clocks/utmi_p1_gfclk";
  4001. usb_host_hs_utmi_p1_clk = "/ocp/l4@4a000000/cm2@8000/clocks/usb_host_hs_utmi_p1_clk";
  4002. utmi_p2_gfclk = "/ocp/l4@4a000000/cm2@8000/clocks/utmi_p2_gfclk";
  4003. usb_host_hs_utmi_p2_clk = "/ocp/l4@4a000000/cm2@8000/clocks/usb_host_hs_utmi_p2_clk";
  4004. usb_host_hs_utmi_p3_clk = "/ocp/l4@4a000000/cm2@8000/clocks/usb_host_hs_utmi_p3_clk";
  4005. usb_host_hs_hsic480m_p1_clk = "/ocp/l4@4a000000/cm2@8000/clocks/usb_host_hs_hsic480m_p1_clk";
  4006. usb_host_hs_hsic60m_p1_clk = "/ocp/l4@4a000000/cm2@8000/clocks/usb_host_hs_hsic60m_p1_clk";
  4007. usb_host_hs_hsic60m_p2_clk = "/ocp/l4@4a000000/cm2@8000/clocks/usb_host_hs_hsic60m_p2_clk";
  4008. usb_host_hs_hsic480m_p2_clk = "/ocp/l4@4a000000/cm2@8000/clocks/usb_host_hs_hsic480m_p2_clk";
  4009. usb_host_hs_func48mclk = "/ocp/l4@4a000000/cm2@8000/clocks/usb_host_hs_func48mclk";
  4010. usb_host_hs_fck = "/ocp/l4@4a000000/cm2@8000/clocks/usb_host_hs_fck";
  4011. otg_60m_gfclk = "/ocp/l4@4a000000/cm2@8000/clocks/otg_60m_gfclk";
  4012. usb_otg_hs_xclk = "/ocp/l4@4a000000/cm2@8000/clocks/usb_otg_hs_xclk";
  4013. usb_otg_hs_ick = "/ocp/l4@4a000000/cm2@8000/clocks/usb_otg_hs_ick";
  4014. usb_phy_cm_clk32k = "/ocp/l4@4a000000/cm2@8000/clocks/usb_phy_cm_clk32k";
  4015. usb_tll_hs_usb_ch2_clk = "/ocp/l4@4a000000/cm2@8000/clocks/usb_tll_hs_usb_ch2_clk";
  4016. usb_tll_hs_usb_ch0_clk = "/ocp/l4@4a000000/cm2@8000/clocks/usb_tll_hs_usb_ch0_clk";
  4017. usb_tll_hs_usb_ch1_clk = "/ocp/l4@4a000000/cm2@8000/clocks/usb_tll_hs_usb_ch1_clk";
  4018. usb_tll_hs_ick = "/ocp/l4@4a000000/cm2@8000/clocks/usb_tll_hs_ick";
  4019. cm2_clockdomains = "/ocp/l4@4a000000/cm2@8000/clockdomains";
  4020. l3_init_clkdm = "/ocp/l4@4a000000/cm2@8000/clockdomains/l3_init_clkdm";
  4021. omap4_scm_core = "/ocp/l4@4a000000/scm@2000";
  4022. scm_conf = "/ocp/l4@4a000000/scm@2000/scm_conf@0";
  4023. omap4_padconf_core = "/ocp/l4@4a000000/scm@100000";
  4024. omap4_pmx_core = "/ocp/l4@4a000000/scm@100000/pinmux@40";
  4025. twl6040_pins = "/ocp/l4@4a000000/scm@100000/pinmux@40/pinmux_twl6040_pins";
  4026. mcpdm_pins = "/ocp/l4@4a000000/scm@100000/pinmux@40/pinmux_mcpdm_pins";
  4027. mcbsp1_pins = "/ocp/l4@4a000000/scm@100000/pinmux@40/pinmux_mcbsp1_pins";
  4028. dss_dpi_pins = "/ocp/l4@4a000000/scm@100000/pinmux@40/pinmux_dss_dpi_pins";
  4029. tfp410_pins = "/ocp/l4@4a000000/scm@100000/pinmux@40/pinmux_tfp410_pins";
  4030. dss_hdmi_pins = "/ocp/l4@4a000000/scm@100000/pinmux@40/pinmux_dss_hdmi_pins";
  4031. tpd12s015_pins = "/ocp/l4@4a000000/scm@100000/pinmux@40/pinmux_tpd12s015_pins";
  4032. hsusbb1_pins = "/ocp/l4@4a000000/scm@100000/pinmux@40/pinmux_hsusbb1_pins";
  4033. i2c1_pins = "/ocp/l4@4a000000/scm@100000/pinmux@40/pinmux_i2c1_pins";
  4034. i2c2_pins = "/ocp/l4@4a000000/scm@100000/pinmux@40/pinmux_i2c2_pins";
  4035. i2c3_pins = "/ocp/l4@4a000000/scm@100000/pinmux@40/pinmux_i2c3_pins";
  4036. i2c4_pins = "/ocp/l4@4a000000/scm@100000/pinmux@40/pinmux_i2c4_pins";
  4037. wl12xx_gpio = "/ocp/l4@4a000000/scm@100000/pinmux@40/pinmux_wl12xx_gpio";
  4038. wl12xx_pins = "/ocp/l4@4a000000/scm@100000/pinmux@40/pinmux_wl12xx_pins";
  4039. twl6030_pins = "/ocp/l4@4a000000/scm@100000/pinmux@40/pinmux_twl6030_pins";
  4040. uart4_pins = "/ocp/l4@4a000000/scm@100000/pinmux@40/pinmux_uart4_pins";
  4041. led_gpio_pins = "/ocp/l4@4a000000/scm@100000/pinmux@40/gpio_led_pmx";
  4042. omap4_padconf_global = "/ocp/l4@4a000000/scm@100000/omap4_padconf_global@5a0";
  4043. pbias_regulator = "/ocp/l4@4a000000/scm@100000/omap4_padconf_global@5a0/pbias_regulator";
  4044. pbias_mmc_reg = "/ocp/l4@4a000000/scm@100000/omap4_padconf_global@5a0/pbias_regulator/pbias_mmc_omap4";
  4045. l4_wkup = "/ocp/l4@4a000000/l4@300000";
  4046. counter32k = "/ocp/l4@4a000000/l4@300000/counter@4000";
  4047. prm = "/ocp/l4@4a000000/l4@300000/prm@6000";
  4048. prm_clocks = "/ocp/l4@4a000000/l4@300000/prm@6000/clocks";
  4049. sys_clkin_ck = "/ocp/l4@4a000000/l4@300000/prm@6000/clocks/sys_clkin_ck";
  4050. abe_dpll_bypass_clk_mux_ck = "/ocp/l4@4a000000/l4@300000/prm@6000/clocks/abe_dpll_bypass_clk_mux_ck";
  4051. abe_dpll_refclk_mux_ck = "/ocp/l4@4a000000/l4@300000/prm@6000/clocks/abe_dpll_refclk_mux_ck";
  4052. dbgclk_mux_ck = "/ocp/l4@4a000000/l4@300000/prm@6000/clocks/dbgclk_mux_ck";
  4053. l4_wkup_clk_mux_ck = "/ocp/l4@4a000000/l4@300000/prm@6000/clocks/l4_wkup_clk_mux_ck";
  4054. syc_clk_div_ck = "/ocp/l4@4a000000/l4@300000/prm@6000/clocks/syc_clk_div_ck";
  4055. gpio1_dbclk = "/ocp/l4@4a000000/l4@300000/prm@6000/clocks/gpio1_dbclk";
  4056. dmt1_clk_mux = "/ocp/l4@4a000000/l4@300000/prm@6000/clocks/dmt1_clk_mux";
  4057. usim_ck = "/ocp/l4@4a000000/l4@300000/prm@6000/clocks/usim_ck";
  4058. usim_fclk = "/ocp/l4@4a000000/l4@300000/prm@6000/clocks/usim_fclk";
  4059. pmd_stm_clock_mux_ck = "/ocp/l4@4a000000/l4@300000/prm@6000/clocks/pmd_stm_clock_mux_ck";
  4060. pmd_trace_clk_mux_ck = "/ocp/l4@4a000000/l4@300000/prm@6000/clocks/pmd_trace_clk_mux_ck";
  4061. stm_clk_div_ck = "/ocp/l4@4a000000/l4@300000/prm@6000/clocks/stm_clk_div_ck";
  4062. trace_clk_div_div_ck = "/ocp/l4@4a000000/l4@300000/prm@6000/clocks/trace_clk_div_div_ck";
  4063. trace_clk_div_ck = "/ocp/l4@4a000000/l4@300000/prm@6000/clocks/trace_clk_div_ck";
  4064. div_ts_ck = "/ocp/l4@4a000000/l4@300000/prm@6000/clocks/div_ts_ck";
  4065. bandgap_ts_fclk = "/ocp/l4@4a000000/l4@300000/prm@6000/clocks/bandgap_ts_fclk";
  4066. prm_clockdomains = "/ocp/l4@4a000000/l4@300000/prm@6000/clockdomains";
  4067. emu_sys_clkdm = "/ocp/l4@4a000000/l4@300000/prm@6000/clockdomains/emu_sys_clkdm";
  4068. scrm = "/ocp/l4@4a000000/l4@300000/scrm@a000";
  4069. scrm_clocks = "/ocp/l4@4a000000/l4@300000/scrm@a000/clocks";
  4070. auxclk0_src_gate_ck = "/ocp/l4@4a000000/l4@300000/scrm@a000/clocks/auxclk0_src_gate_ck";
  4071. auxclk0_src_mux_ck = "/ocp/l4@4a000000/l4@300000/scrm@a000/clocks/auxclk0_src_mux_ck";
  4072. auxclk0_src_ck = "/ocp/l4@4a000000/l4@300000/scrm@a000/clocks/auxclk0_src_ck";
  4073. auxclk0_ck = "/ocp/l4@4a000000/l4@300000/scrm@a000/clocks/auxclk0_ck";
  4074. auxclk1_src_gate_ck = "/ocp/l4@4a000000/l4@300000/scrm@a000/clocks/auxclk1_src_gate_ck";
  4075. auxclk1_src_mux_ck = "/ocp/l4@4a000000/l4@300000/scrm@a000/clocks/auxclk1_src_mux_ck";
  4076. auxclk1_src_ck = "/ocp/l4@4a000000/l4@300000/scrm@a000/clocks/auxclk1_src_ck";
  4077. auxclk1_ck = "/ocp/l4@4a000000/l4@300000/scrm@a000/clocks/auxclk1_ck";
  4078. auxclk2_src_gate_ck = "/ocp/l4@4a000000/l4@300000/scrm@a000/clocks/auxclk2_src_gate_ck";
  4079. auxclk2_src_mux_ck = "/ocp/l4@4a000000/l4@300000/scrm@a000/clocks/auxclk2_src_mux_ck";
  4080. auxclk2_src_ck = "/ocp/l4@4a000000/l4@300000/scrm@a000/clocks/auxclk2_src_ck";
  4081. auxclk2_ck = "/ocp/l4@4a000000/l4@300000/scrm@a000/clocks/auxclk2_ck";
  4082. auxclk3_src_gate_ck = "/ocp/l4@4a000000/l4@300000/scrm@a000/clocks/auxclk3_src_gate_ck";
  4083. auxclk3_src_mux_ck = "/ocp/l4@4a000000/l4@300000/scrm@a000/clocks/auxclk3_src_mux_ck";
  4084. auxclk3_src_ck = "/ocp/l4@4a000000/l4@300000/scrm@a000/clocks/auxclk3_src_ck";
  4085. auxclk3_ck = "/ocp/l4@4a000000/l4@300000/scrm@a000/clocks/auxclk3_ck";
  4086. auxclk4_src_gate_ck = "/ocp/l4@4a000000/l4@300000/scrm@a000/clocks/auxclk4_src_gate_ck";
  4087. auxclk4_src_mux_ck = "/ocp/l4@4a000000/l4@300000/scrm@a000/clocks/auxclk4_src_mux_ck";
  4088. auxclk4_src_ck = "/ocp/l4@4a000000/l4@300000/scrm@a000/clocks/auxclk4_src_ck";
  4089. auxclk4_ck = "/ocp/l4@4a000000/l4@300000/scrm@a000/clocks/auxclk4_ck";
  4090. auxclk5_src_gate_ck = "/ocp/l4@4a000000/l4@300000/scrm@a000/clocks/auxclk5_src_gate_ck";
  4091. auxclk5_src_mux_ck = "/ocp/l4@4a000000/l4@300000/scrm@a000/clocks/auxclk5_src_mux_ck";
  4092. auxclk5_src_ck = "/ocp/l4@4a000000/l4@300000/scrm@a000/clocks/auxclk5_src_ck";
  4093. auxclk5_ck = "/ocp/l4@4a000000/l4@300000/scrm@a000/clocks/auxclk5_ck";
  4094. auxclkreq0_ck = "/ocp/l4@4a000000/l4@300000/scrm@a000/clocks/auxclkreq0_ck";
  4095. auxclkreq1_ck = "/ocp/l4@4a000000/l4@300000/scrm@a000/clocks/auxclkreq1_ck";
  4096. auxclkreq2_ck = "/ocp/l4@4a000000/l4@300000/scrm@a000/clocks/auxclkreq2_ck";
  4097. auxclkreq3_ck = "/ocp/l4@4a000000/l4@300000/scrm@a000/clocks/auxclkreq3_ck";
  4098. auxclkreq4_ck = "/ocp/l4@4a000000/l4@300000/scrm@a000/clocks/auxclkreq4_ck";
  4099. auxclkreq5_ck = "/ocp/l4@4a000000/l4@300000/scrm@a000/clocks/auxclkreq5_ck";
  4100. scrm_clockdomains = "/ocp/l4@4a000000/l4@300000/scrm@a000/clockdomains";
  4101. omap4_pmx_wkup = "/ocp/l4@4a000000/l4@300000/pinmux@1e040";
  4102. led_wkgpio_pins = "/ocp/l4@4a000000/l4@300000/pinmux@1e040/pinmux_leds_wkpins";
  4103. twl6030_wkup_pins = "/ocp/l4@4a000000/l4@300000/pinmux@1e040/pinmux_twl6030_wkup_pins";
  4104. ocmcram = "/ocp/ocmcram@40304000";
  4105. sdma = "/ocp/dma-controller@4a056000";
  4106. gpio1 = "/ocp/gpio@4a310000";
  4107. gpio2 = "/ocp/gpio@48055000";
  4108. gpio3 = "/ocp/gpio@48057000";
  4109. gpio4 = "/ocp/gpio@48059000";
  4110. gpio5 = "/ocp/gpio@4805b000";
  4111. gpio6 = "/ocp/gpio@4805d000";
  4112. gpmc = "/ocp/gpmc@50000000";
  4113. uart1 = "/ocp/serial@4806a000";
  4114. uart2 = "/ocp/serial@4806c000";
  4115. uart3 = "/ocp/serial@48020000";
  4116. uart4 = "/ocp/serial@4806e000";
  4117. hwspinlock = "/ocp/spinlock@4a0f6000";
  4118. i2c1 = "/ocp/i2c@48070000";
  4119. twl = "/ocp/i2c@48070000/twl@48";
  4120. vaux1 = "/ocp/i2c@48070000/twl@48/regulator-vaux1";
  4121. vaux2 = "/ocp/i2c@48070000/twl@48/regulator-vaux2";
  4122. vaux3 = "/ocp/i2c@48070000/twl@48/regulator-vaux3";
  4123. vmmc = "/ocp/i2c@48070000/twl@48/regulator-vmmc";
  4124. vpp = "/ocp/i2c@48070000/twl@48/regulator-vpp";
  4125. vusim = "/ocp/i2c@48070000/twl@48/regulator-vusim";
  4126. vdac = "/ocp/i2c@48070000/twl@48/regulator-vdac";
  4127. vana = "/ocp/i2c@48070000/twl@48/regulator-vana";
  4128. vcxio = "/ocp/i2c@48070000/twl@48/regulator-vcxio";
  4129. vusb = "/ocp/i2c@48070000/twl@48/regulator-vusb";
  4130. v1v8 = "/ocp/i2c@48070000/twl@48/regulator-v1v8";
  4131. v2v1 = "/ocp/i2c@48070000/twl@48/regulator-v2v1";
  4132. twl_usb_comparator = "/ocp/i2c@48070000/twl@48/usb-comparator";
  4133. twl_pwm = "/ocp/i2c@48070000/twl@48/pwm";
  4134. twl_pwmled = "/ocp/i2c@48070000/twl@48/pwmled";
  4135. twl6040 = "/ocp/i2c@48070000/twl@4b";
  4136. i2c2 = "/ocp/i2c@48072000";
  4137. i2c3 = "/ocp/i2c@48060000";
  4138. i2c4 = "/ocp/i2c@48350000";
  4139. mcspi1 = "/ocp/spi@48098000";
  4140. mcspi2 = "/ocp/spi@4809a000";
  4141. mcspi3 = "/ocp/spi@480b8000";
  4142. mcspi4 = "/ocp/spi@480ba000";
  4143. mmc1 = "/ocp/mmc@4809c000";
  4144. mmc2 = "/ocp/mmc@480b4000";
  4145. mmc3 = "/ocp/mmc@480ad000";
  4146. mmc4 = "/ocp/mmc@480d1000";
  4147. mmc5 = "/ocp/mmc@480d5000";
  4148. wlcore = "/ocp/mmc@480d5000/wlcore@2";
  4149. mmu_dsp = "/ocp/mmu@4a066000";
  4150. mmu_ipu = "/ocp/mmu@55082000";
  4151. wdt2 = "/ocp/wdt@4a314000";
  4152. mcpdm = "/ocp/mcpdm@40132000";
  4153. dmic = "/ocp/dmic@4012e000";
  4154. mcbsp1 = "/ocp/mcbsp@40122000";
  4155. mcbsp2 = "/ocp/mcbsp@40124000";
  4156. mcbsp3 = "/ocp/mcbsp@40126000";
  4157. mcbsp4 = "/ocp/mcbsp@48096000";
  4158. keypad = "/ocp/keypad@4a31c000";
  4159. emif1 = "/ocp/emif@4c000000";
  4160. emif2 = "/ocp/emif@4d000000";
  4161. usb2_phy = "/ocp/ocp2scp@4a0ad000/usb2phy@4a0ad080";
  4162. mailbox = "/ocp/mailbox@4a0f4000";
  4163. mbox_ipu = "/ocp/mailbox@4a0f4000/mbox_ipu";
  4164. mbox_dsp = "/ocp/mailbox@4a0f4000/mbox_dsp";
  4165. timer1 = "/ocp/timer@4a318000";
  4166. timer2 = "/ocp/timer@48032000";
  4167. timer3 = "/ocp/timer@48034000";
  4168. timer4 = "/ocp/timer@48036000";
  4169. timer5 = "/ocp/timer@40138000";
  4170. timer6 = "/ocp/timer@4013a000";
  4171. timer7 = "/ocp/timer@4013c000";
  4172. timer8 = "/ocp/timer@4013e000";
  4173. timer9 = "/ocp/timer@4803e000";
  4174. timer10 = "/ocp/timer@48086000";
  4175. timer11 = "/ocp/timer@48088000";
  4176. usbhstll = "/ocp/usbhstll@4a062000";
  4177. usbhshost = "/ocp/usbhshost@4a064000";
  4178. usbhsohci = "/ocp/usbhshost@4a064000/ohci@4a064800";
  4179. usbhsehci = "/ocp/usbhshost@4a064000/ehci@4a064c00";
  4180. omap_control_usb2phy = "/ocp/control-phy@4a002300";
  4181. omap_control_usbotg = "/ocp/control-phy@4a00233c";
  4182. usb_otg_hs = "/ocp/usb_otg_hs@4a0ab000";
  4183. aes = "/ocp/aes@4b501000";
  4184. des = "/ocp/des@480a5000";
  4185. abb_mpu = "/ocp/regulator-abb-mpu";
  4186. abb_iva = "/ocp/regulator-abb-iva";
  4187. dss = "/ocp/dss@58000000";
  4188. rfbi = "/ocp/dss@58000000/encoder@58002000";
  4189. venc = "/ocp/dss@58000000/encoder@58003000";
  4190. dsi1 = "/ocp/dss@58000000/encoder@58004000";
  4191. dsi2 = "/ocp/dss@58000000/encoder@58005000";
  4192. hdmi = "/ocp/dss@58000000/encoder@58006000";
  4193. hdmi_out = "/ocp/dss@58000000/encoder@58006000/port/endpoint";
  4194. dpi_out = "/ocp/dss@58000000/port/endpoint";
  4195. bandgap = "/ocp/bandgap";
  4196. cpu_thermal = "/thermal-zones/cpu_thermal";
  4197. cpu_trips = "/thermal-zones/cpu_thermal/trips";
  4198. cpu_alert0 = "/thermal-zones/cpu_thermal/trips/cpu_alert";
  4199. cpu_crit = "/thermal-zones/cpu_thermal/trips/cpu_crit";
  4200. cpu_cooling_maps = "/thermal-zones/cpu_thermal/cooling-maps";
  4201. elpida_ECB240ABACN = "/lpddr2";
  4202. timings_elpida_ECB240ABACN_400mhz = "/lpddr2/lpddr2-timings@0";
  4203. timings_elpida_ECB240ABACN_200mhz = "/lpddr2/lpddr2-timings@1";
  4204. leds = "/leds";
  4205. sound = "/sound";
  4206. hsusb1_power = "/hsusb1_power_reg";
  4207. hsusb1_phy = "/hsusb1_phy";
  4208. wl12xx_vmmc = "/wl12xx_vmmc";
  4209. tfp410 = "/encoder@0";
  4210. tfp410_in = "/encoder@0/ports/port@0/endpoint@0";
  4211. tfp410_out = "/encoder@0/ports/port@1/endpoint@0";
  4212. dvi0 = "/connector@0";
  4213. dvi_connector_in = "/connector@0/port/endpoint";
  4214. tpd12s015 = "/encoder@1";
  4215. tpd12s015_in = "/encoder@1/ports/port@0/endpoint@0";
  4216. tpd12s015_out = "/encoder@1/ports/port@1/endpoint@0";
  4217. hdmi0 = "/connector@1";
  4218. hdmi_connector_in = "/connector@1/port/endpoint";
  4219. };
  4220.  
  4221. __local_fixups__ {
  4222. interrupt-parent = <0x0>;
  4223.  
  4224. cpus {
  4225.  
  4226. cpu@0 {
  4227. next-level-cache = <0x0>;
  4228. clocks = <0x0>;
  4229. };
  4230.  
  4231. cpu@1 {
  4232. next-level-cache = <0x0>;
  4233. };
  4234. };
  4235.  
  4236. interrupt-controller@48241000 {
  4237. interrupt-parent = <0x0>;
  4238. };
  4239.  
  4240. local-timer@48240600 {
  4241. clocks = <0x0>;
  4242. interrupt-parent = <0x0>;
  4243. };
  4244.  
  4245. interrupt-controller@48281000 {
  4246. interrupt-parent = <0x0>;
  4247. };
  4248.  
  4249. soc {
  4250.  
  4251. mpu {
  4252. sram = <0x0>;
  4253. };
  4254. };
  4255.  
  4256. ocp {
  4257.  
  4258. l4@4a000000 {
  4259.  
  4260. cm1@4000 {
  4261.  
  4262. clocks {
  4263.  
  4264. pad_clks_ck {
  4265. clocks = <0x0>;
  4266. };
  4267.  
  4268. slimbus_clk {
  4269. clocks = <0x0>;
  4270. };
  4271.  
  4272. dpll_abe_ck {
  4273. clocks = <0x0 0x4>;
  4274. };
  4275.  
  4276. dpll_abe_x2_ck {
  4277. clocks = <0x0>;
  4278. };
  4279.  
  4280. dpll_abe_m2x2_ck {
  4281. clocks = <0x0>;
  4282. };
  4283.  
  4284. abe_24m_fclk {
  4285. clocks = <0x0>;
  4286. };
  4287.  
  4288. abe_clk {
  4289. clocks = <0x0>;
  4290. };
  4291.  
  4292. aess_fclk {
  4293. clocks = <0x0>;
  4294. };
  4295.  
  4296. dpll_abe_m3x2_ck {
  4297. clocks = <0x0>;
  4298. };
  4299.  
  4300. core_hsd_byp_clk_mux_ck {
  4301. clocks = <0x0 0x4>;
  4302. };
  4303.  
  4304. dpll_core_ck {
  4305. clocks = <0x0 0x4>;
  4306. };
  4307.  
  4308. dpll_core_x2_ck {
  4309. clocks = <0x0>;
  4310. };
  4311.  
  4312. dpll_core_m6x2_ck {
  4313. clocks = <0x0>;
  4314. };
  4315.  
  4316. dpll_core_m2_ck {
  4317. clocks = <0x0>;
  4318. };
  4319.  
  4320. ddrphy_ck {
  4321. clocks = <0x0>;
  4322. };
  4323.  
  4324. dpll_core_m5x2_ck {
  4325. clocks = <0x0>;
  4326. };
  4327.  
  4328. div_core_ck {
  4329. clocks = <0x0>;
  4330. };
  4331.  
  4332. div_iva_hs_clk {
  4333. clocks = <0x0>;
  4334. };
  4335.  
  4336. div_mpu_hs_clk {
  4337. clocks = <0x0>;
  4338. };
  4339.  
  4340. dpll_core_m4x2_ck {
  4341. clocks = <0x0>;
  4342. };
  4343.  
  4344. dll_clk_div_ck {
  4345. clocks = <0x0>;
  4346. };
  4347.  
  4348. dpll_abe_m2_ck {
  4349. clocks = <0x0>;
  4350. };
  4351.  
  4352. dpll_core_m3x2_gate_ck {
  4353. clocks = <0x0>;
  4354. };
  4355.  
  4356. dpll_core_m3x2_div_ck {
  4357. clocks = <0x0>;
  4358. };
  4359.  
  4360. dpll_core_m3x2_ck {
  4361. clocks = <0x0 0x4>;
  4362. };
  4363.  
  4364. dpll_core_m7x2_ck {
  4365. clocks = <0x0>;
  4366. };
  4367.  
  4368. iva_hsd_byp_clk_mux_ck {
  4369. clocks = <0x0 0x4>;
  4370. };
  4371.  
  4372. dpll_iva_ck {
  4373. clocks = <0x0 0x4>;
  4374. };
  4375.  
  4376. dpll_iva_x2_ck {
  4377. clocks = <0x0>;
  4378. };
  4379.  
  4380. dpll_iva_m4x2_ck {
  4381. clocks = <0x0>;
  4382. };
  4383.  
  4384. dpll_iva_m5x2_ck {
  4385. clocks = <0x0>;
  4386. };
  4387.  
  4388. dpll_mpu_ck {
  4389. clocks = <0x0 0x4>;
  4390. };
  4391.  
  4392. dpll_mpu_m2_ck {
  4393. clocks = <0x0>;
  4394. };
  4395.  
  4396. per_hs_clk_div_ck {
  4397. clocks = <0x0>;
  4398. };
  4399.  
  4400. usb_hs_clk_div_ck {
  4401. clocks = <0x0>;
  4402. };
  4403.  
  4404. l3_div_ck {
  4405. clocks = <0x0>;
  4406. };
  4407.  
  4408. l4_div_ck {
  4409. clocks = <0x0>;
  4410. };
  4411.  
  4412. lp_clk_div_ck {
  4413. clocks = <0x0>;
  4414. };
  4415.  
  4416. mpu_periphclk {
  4417. clocks = <0x0>;
  4418. };
  4419.  
  4420. ocp_abe_iclk {
  4421. clocks = <0x0>;
  4422. };
  4423.  
  4424. per_abe_24m_fclk {
  4425. clocks = <0x0>;
  4426. };
  4427.  
  4428. dmic_sync_mux_ck {
  4429. clocks = <0x0 0x4 0x8>;
  4430. };
  4431.  
  4432. func_dmic_abe_gfclk {
  4433. clocks = <0x0 0x4 0x8>;
  4434. };
  4435.  
  4436. mcasp_sync_mux_ck {
  4437. clocks = <0x0 0x4 0x8>;
  4438. };
  4439.  
  4440. func_mcasp_abe_gfclk {
  4441. clocks = <0x0 0x4 0x8>;
  4442. };
  4443.  
  4444. mcbsp1_sync_mux_ck {
  4445. clocks = <0x0 0x4 0x8>;
  4446. };
  4447.  
  4448. func_mcbsp1_gfclk {
  4449. clocks = <0x0 0x4 0x8>;
  4450. };
  4451.  
  4452. mcbsp2_sync_mux_ck {
  4453. clocks = <0x0 0x4 0x8>;
  4454. };
  4455.  
  4456. func_mcbsp2_gfclk {
  4457. clocks = <0x0 0x4 0x8>;
  4458. };
  4459.  
  4460. mcbsp3_sync_mux_ck {
  4461. clocks = <0x0 0x4 0x8>;
  4462. };
  4463.  
  4464. func_mcbsp3_gfclk {
  4465. clocks = <0x0 0x4 0x8>;
  4466. };
  4467.  
  4468. slimbus1_fclk_1 {
  4469. clocks = <0x0>;
  4470. };
  4471.  
  4472. slimbus1_fclk_0 {
  4473. clocks = <0x0>;
  4474. };
  4475.  
  4476. slimbus1_fclk_2 {
  4477. clocks = <0x0>;
  4478. };
  4479.  
  4480. slimbus1_slimbus_clk {
  4481. clocks = <0x0>;
  4482. };
  4483.  
  4484. timer5_sync_mux {
  4485. clocks = <0x0 0x4>;
  4486. };
  4487.  
  4488. timer6_sync_mux {
  4489. clocks = <0x0 0x4>;
  4490. };
  4491.  
  4492. timer7_sync_mux {
  4493. clocks = <0x0 0x4>;
  4494. };
  4495.  
  4496. timer8_sync_mux {
  4497. clocks = <0x0 0x4>;
  4498. };
  4499. };
  4500. };
  4501.  
  4502. cm2@8000 {
  4503.  
  4504. clocks {
  4505.  
  4506. per_hsd_byp_clk_mux_ck {
  4507. clocks = <0x0 0x4>;
  4508. };
  4509.  
  4510. dpll_per_ck {
  4511. clocks = <0x0 0x4>;
  4512. };
  4513.  
  4514. dpll_per_m2_ck {
  4515. clocks = <0x0>;
  4516. };
  4517.  
  4518. dpll_per_x2_ck {
  4519. clocks = <0x0>;
  4520. };
  4521.  
  4522. dpll_per_m2x2_ck {
  4523. clocks = <0x0>;
  4524. };
  4525.  
  4526. dpll_per_m3x2_gate_ck {
  4527. clocks = <0x0>;
  4528. };
  4529.  
  4530. dpll_per_m3x2_div_ck {
  4531. clocks = <0x0>;
  4532. };
  4533.  
  4534. dpll_per_m3x2_ck {
  4535. clocks = <0x0 0x4>;
  4536. };
  4537.  
  4538. dpll_per_m4x2_ck {
  4539. clocks = <0x0>;
  4540. };
  4541.  
  4542. dpll_per_m5x2_ck {
  4543. clocks = <0x0>;
  4544. };
  4545.  
  4546. dpll_per_m6x2_ck {
  4547. clocks = <0x0>;
  4548. };
  4549.  
  4550. dpll_per_m7x2_ck {
  4551. clocks = <0x0>;
  4552. };
  4553.  
  4554. dpll_usb_ck {
  4555. clocks = <0x0 0x4>;
  4556. };
  4557.  
  4558. dpll_usb_clkdcoldo_ck {
  4559. clocks = <0x0>;
  4560. };
  4561.  
  4562. dpll_usb_m2_ck {
  4563. clocks = <0x0>;
  4564. };
  4565.  
  4566. ducati_clk_mux_ck {
  4567. clocks = <0x0 0x4>;
  4568. };
  4569.  
  4570. func_12m_fclk {
  4571. clocks = <0x0>;
  4572. };
  4573.  
  4574. func_24m_clk {
  4575. clocks = <0x0>;
  4576. };
  4577.  
  4578. func_24mc_fclk {
  4579. clocks = <0x0>;
  4580. };
  4581.  
  4582. func_48m_fclk {
  4583. clocks = <0x0>;
  4584. };
  4585.  
  4586. func_48mc_fclk {
  4587. clocks = <0x0>;
  4588. };
  4589.  
  4590. func_64m_fclk {
  4591. clocks = <0x0>;
  4592. };
  4593.  
  4594. func_96m_fclk {
  4595. clocks = <0x0>;
  4596. };
  4597.  
  4598. init_60m_fclk {
  4599. clocks = <0x0>;
  4600. };
  4601.  
  4602. per_abe_nc_fclk {
  4603. clocks = <0x0>;
  4604. };
  4605.  
  4606. aes1_fck {
  4607. clocks = <0x0>;
  4608. };
  4609.  
  4610. aes2_fck {
  4611. clocks = <0x0>;
  4612. };
  4613.  
  4614. dss_sys_clk {
  4615. clocks = <0x0>;
  4616. };
  4617.  
  4618. dss_tv_clk {
  4619. clocks = <0x0>;
  4620. };
  4621.  
  4622. dss_dss_clk {
  4623. clocks = <0x0>;
  4624. };
  4625.  
  4626. dss_48mhz_clk {
  4627. clocks = <0x0>;
  4628. };
  4629.  
  4630. fdif_fck {
  4631. clocks = <0x0>;
  4632. };
  4633.  
  4634. gpio2_dbclk {
  4635. clocks = <0x0>;
  4636. };
  4637.  
  4638. gpio3_dbclk {
  4639. clocks = <0x0>;
  4640. };
  4641.  
  4642. gpio4_dbclk {
  4643. clocks = <0x0>;
  4644. };
  4645.  
  4646. gpio5_dbclk {
  4647. clocks = <0x0>;
  4648. };
  4649.  
  4650. gpio6_dbclk {
  4651. clocks = <0x0>;
  4652. };
  4653.  
  4654. sgx_clk_mux {
  4655. clocks = <0x0 0x4>;
  4656. };
  4657.  
  4658. hsi_fck {
  4659. clocks = <0x0>;
  4660. };
  4661.  
  4662. iss_ctrlclk {
  4663. clocks = <0x0>;
  4664. };
  4665.  
  4666. mcbsp4_sync_mux_ck {
  4667. clocks = <0x0 0x4>;
  4668. };
  4669.  
  4670. per_mcbsp4_gfclk {
  4671. clocks = <0x0 0x4>;
  4672. };
  4673.  
  4674. hsmmc1_fclk {
  4675. clocks = <0x0 0x4>;
  4676. };
  4677.  
  4678. hsmmc2_fclk {
  4679. clocks = <0x0 0x4>;
  4680. };
  4681.  
  4682. ocp2scp_usb_phy_phy_48m {
  4683. clocks = <0x0>;
  4684. };
  4685.  
  4686. sha2md5_fck {
  4687. clocks = <0x0>;
  4688. };
  4689.  
  4690. slimbus2_fclk_1 {
  4691. clocks = <0x0>;
  4692. };
  4693.  
  4694. slimbus2_fclk_0 {
  4695. clocks = <0x0>;
  4696. };
  4697.  
  4698. slimbus2_slimbus_clk {
  4699. clocks = <0x0>;
  4700. };
  4701.  
  4702. smartreflex_core_fck {
  4703. clocks = <0x0>;
  4704. };
  4705.  
  4706. smartreflex_iva_fck {
  4707. clocks = <0x0>;
  4708. };
  4709.  
  4710. smartreflex_mpu_fck {
  4711. clocks = <0x0>;
  4712. };
  4713.  
  4714. cm2_dm10_mux {
  4715. clocks = <0x0 0x4>;
  4716. };
  4717.  
  4718. cm2_dm11_mux {
  4719. clocks = <0x0 0x4>;
  4720. };
  4721.  
  4722. cm2_dm2_mux {
  4723. clocks = <0x0 0x4>;
  4724. };
  4725.  
  4726. cm2_dm3_mux {
  4727. clocks = <0x0 0x4>;
  4728. };
  4729.  
  4730. cm2_dm4_mux {
  4731. clocks = <0x0 0x4>;
  4732. };
  4733.  
  4734. cm2_dm9_mux {
  4735. clocks = <0x0 0x4>;
  4736. };
  4737.  
  4738. usb_host_fs_fck {
  4739. clocks = <0x0>;
  4740. };
  4741.  
  4742. utmi_p1_gfclk {
  4743. clocks = <0x0 0x4>;
  4744. };
  4745.  
  4746. usb_host_hs_utmi_p1_clk {
  4747. clocks = <0x0>;
  4748. };
  4749.  
  4750. utmi_p2_gfclk {
  4751. clocks = <0x0 0x4>;
  4752. };
  4753.  
  4754. usb_host_hs_utmi_p2_clk {
  4755. clocks = <0x0>;
  4756. };
  4757.  
  4758. usb_host_hs_utmi_p3_clk {
  4759. clocks = <0x0>;
  4760. };
  4761.  
  4762. usb_host_hs_hsic480m_p1_clk {
  4763. clocks = <0x0>;
  4764. };
  4765.  
  4766. usb_host_hs_hsic60m_p1_clk {
  4767. clocks = <0x0>;
  4768. };
  4769.  
  4770. usb_host_hs_hsic60m_p2_clk {
  4771. clocks = <0x0>;
  4772. };
  4773.  
  4774. usb_host_hs_hsic480m_p2_clk {
  4775. clocks = <0x0>;
  4776. };
  4777.  
  4778. usb_host_hs_func48mclk {
  4779. clocks = <0x0>;
  4780. };
  4781.  
  4782. usb_host_hs_fck {
  4783. clocks = <0x0>;
  4784. };
  4785.  
  4786. otg_60m_gfclk {
  4787. clocks = <0x0 0x4>;
  4788. };
  4789.  
  4790. usb_otg_hs_xclk {
  4791. clocks = <0x0>;
  4792. };
  4793.  
  4794. usb_otg_hs_ick {
  4795. clocks = <0x0>;
  4796. };
  4797.  
  4798. usb_phy_cm_clk32k {
  4799. clocks = <0x0>;
  4800. };
  4801.  
  4802. usb_tll_hs_usb_ch2_clk {
  4803. clocks = <0x0>;
  4804. };
  4805.  
  4806. usb_tll_hs_usb_ch0_clk {
  4807. clocks = <0x0>;
  4808. };
  4809.  
  4810. usb_tll_hs_usb_ch1_clk {
  4811. clocks = <0x0>;
  4812. };
  4813.  
  4814. usb_tll_hs_ick {
  4815. clocks = <0x0>;
  4816. };
  4817. };
  4818.  
  4819. clockdomains {
  4820.  
  4821. l3_init_clkdm {
  4822. clocks = <0x0 0x4>;
  4823. };
  4824. };
  4825. };
  4826.  
  4827. scm@100000 {
  4828.  
  4829. pinmux@40 {
  4830. pinctrl-0 = <0x0 0x4 0x8 0xc 0x10>;
  4831. };
  4832.  
  4833. omap4_padconf_global@5a0 {
  4834.  
  4835. pbias_regulator {
  4836. syscon = <0x0>;
  4837. };
  4838. };
  4839. };
  4840.  
  4841. l4@300000 {
  4842.  
  4843. prm@6000 {
  4844.  
  4845. clocks {
  4846.  
  4847. sys_clkin_ck {
  4848. clocks = <0x0 0x4 0x8 0xc 0x10 0x14 0x18>;
  4849. };
  4850.  
  4851. abe_dpll_bypass_clk_mux_ck {
  4852. clocks = <0x0 0x4>;
  4853. };
  4854.  
  4855. abe_dpll_refclk_mux_ck {
  4856. clocks = <0x0 0x4>;
  4857. };
  4858.  
  4859. dbgclk_mux_ck {
  4860. clocks = <0x0>;
  4861. };
  4862.  
  4863. l4_wkup_clk_mux_ck {
  4864. clocks = <0x0 0x4>;
  4865. };
  4866.  
  4867. syc_clk_div_ck {
  4868. clocks = <0x0>;
  4869. };
  4870.  
  4871. gpio1_dbclk {
  4872. clocks = <0x0>;
  4873. };
  4874.  
  4875. dmt1_clk_mux {
  4876. clocks = <0x0 0x4>;
  4877. };
  4878.  
  4879. usim_ck {
  4880. clocks = <0x0>;
  4881. };
  4882.  
  4883. usim_fclk {
  4884. clocks = <0x0>;
  4885. };
  4886.  
  4887. pmd_stm_clock_mux_ck {
  4888. clocks = <0x0 0x4 0x8>;
  4889. };
  4890.  
  4891. pmd_trace_clk_mux_ck {
  4892. clocks = <0x0 0x4 0x8>;
  4893. };
  4894.  
  4895. stm_clk_div_ck {
  4896. clocks = <0x0>;
  4897. };
  4898.  
  4899. trace_clk_div_div_ck {
  4900. clocks = <0x0>;
  4901. };
  4902.  
  4903. trace_clk_div_ck {
  4904. clocks = <0x0>;
  4905. };
  4906.  
  4907. div_ts_ck {
  4908. clocks = <0x0>;
  4909. };
  4910.  
  4911. bandgap_ts_fclk {
  4912. clocks = <0x0>;
  4913. };
  4914. };
  4915.  
  4916. clockdomains {
  4917.  
  4918. emu_sys_clkdm {
  4919. clocks = <0x0>;
  4920. };
  4921. };
  4922. };
  4923.  
  4924. scrm@a000 {
  4925.  
  4926. clocks {
  4927.  
  4928. auxclk0_src_gate_ck {
  4929. clocks = <0x0>;
  4930. };
  4931.  
  4932. auxclk0_src_mux_ck {
  4933. clocks = <0x0 0x4 0x8>;
  4934. };
  4935.  
  4936. auxclk0_src_ck {
  4937. clocks = <0x0 0x4>;
  4938. };
  4939.  
  4940. auxclk0_ck {
  4941. clocks = <0x0>;
  4942. };
  4943.  
  4944. auxclk1_src_gate_ck {
  4945. clocks = <0x0>;
  4946. };
  4947.  
  4948. auxclk1_src_mux_ck {
  4949. clocks = <0x0 0x4 0x8>;
  4950. };
  4951.  
  4952. auxclk1_src_ck {
  4953. clocks = <0x0 0x4>;
  4954. };
  4955.  
  4956. auxclk1_ck {
  4957. clocks = <0x0>;
  4958. };
  4959.  
  4960. auxclk2_src_gate_ck {
  4961. clocks = <0x0>;
  4962. };
  4963.  
  4964. auxclk2_src_mux_ck {
  4965. clocks = <0x0 0x4 0x8>;
  4966. };
  4967.  
  4968. auxclk2_src_ck {
  4969. clocks = <0x0 0x4>;
  4970. };
  4971.  
  4972. auxclk2_ck {
  4973. clocks = <0x0>;
  4974. };
  4975.  
  4976. auxclk3_src_gate_ck {
  4977. clocks = <0x0>;
  4978. };
  4979.  
  4980. auxclk3_src_mux_ck {
  4981. clocks = <0x0 0x4 0x8>;
  4982. };
  4983.  
  4984. auxclk3_src_ck {
  4985. clocks = <0x0 0x4>;
  4986. };
  4987.  
  4988. auxclk3_ck {
  4989. clocks = <0x0>;
  4990. };
  4991.  
  4992. auxclk4_src_gate_ck {
  4993. clocks = <0x0>;
  4994. };
  4995.  
  4996. auxclk4_src_mux_ck {
  4997. clocks = <0x0 0x4 0x8>;
  4998. };
  4999.  
  5000. auxclk4_src_ck {
  5001. clocks = <0x0 0x4>;
  5002. };
  5003.  
  5004. auxclk4_ck {
  5005. clocks = <0x0>;
  5006. };
  5007.  
  5008. auxclk5_src_gate_ck {
  5009. clocks = <0x0>;
  5010. };
  5011.  
  5012. auxclk5_src_mux_ck {
  5013. clocks = <0x0 0x4 0x8>;
  5014. };
  5015.  
  5016. auxclk5_src_ck {
  5017. clocks = <0x0 0x4>;
  5018. };
  5019.  
  5020. auxclk5_ck {
  5021. clocks = <0x0>;
  5022. };
  5023.  
  5024. auxclkreq0_ck {
  5025. clocks = <0x0 0x4 0x8 0xc 0x10 0x14>;
  5026. };
  5027.  
  5028. auxclkreq1_ck {
  5029. clocks = <0x0 0x4 0x8 0xc 0x10 0x14>;
  5030. };
  5031.  
  5032. auxclkreq2_ck {
  5033. clocks = <0x0 0x4 0x8 0xc 0x10 0x14>;
  5034. };
  5035.  
  5036. auxclkreq3_ck {
  5037. clocks = <0x0 0x4 0x8 0xc 0x10 0x14>;
  5038. };
  5039.  
  5040. auxclkreq4_ck {
  5041. clocks = <0x0 0x4 0x8 0xc 0x10 0x14>;
  5042. };
  5043.  
  5044. auxclkreq5_ck {
  5045. clocks = <0x0 0x4 0x8 0xc 0x10 0x14>;
  5046. };
  5047. };
  5048. };
  5049. };
  5050. };
  5051.  
  5052. gpmc@50000000 {
  5053. clocks = <0x0>;
  5054. };
  5055.  
  5056. serial@4806c000 {
  5057. interrupts-extended = <0x0 0x10>;
  5058. };
  5059.  
  5060. serial@48020000 {
  5061. interrupts-extended = <0x0 0x10>;
  5062. };
  5063.  
  5064. serial@4806e000 {
  5065. interrupts-extended = <0x0 0x10>;
  5066. };
  5067.  
  5068. i2c@48070000 {
  5069. pinctrl-0 = <0x0>;
  5070.  
  5071. twl@48 {
  5072. pinctrl-0 = <0x0 0x4>;
  5073.  
  5074. usb-comparator {
  5075. usb-supply = <0x0>;
  5076. };
  5077. };
  5078.  
  5079. twl@4b {
  5080. pinctrl-0 = <0x0>;
  5081. ti,audpwron-gpio = <0x0>;
  5082. vio-supply = <0x0>;
  5083. v2v1-supply = <0x0>;
  5084. };
  5085. };
  5086.  
  5087. i2c@48072000 {
  5088. pinctrl-0 = <0x0>;
  5089. };
  5090.  
  5091. i2c@48060000 {
  5092. pinctrl-0 = <0x0>;
  5093. };
  5094.  
  5095. i2c@48350000 {
  5096. pinctrl-0 = <0x0>;
  5097. };
  5098.  
  5099. spi@48098000 {
  5100. dmas = <0x0 0x8 0x10 0x18 0x20 0x28 0x30 0x38>;
  5101. };
  5102.  
  5103. spi@4809a000 {
  5104. dmas = <0x0 0x8 0x10 0x18>;
  5105. };
  5106.  
  5107. spi@480b8000 {
  5108. dmas = <0x0 0x8>;
  5109. };
  5110.  
  5111. spi@480ba000 {
  5112. dmas = <0x0 0x8>;
  5113. };
  5114.  
  5115. mmc@4809c000 {
  5116. dmas = <0x0 0x8>;
  5117. pbias-supply = <0x0>;
  5118. vmmc-supply = <0x0>;
  5119. };
  5120.  
  5121. mmc@480b4000 {
  5122. dmas = <0x0 0x8>;
  5123. };
  5124.  
  5125. mmc@480ad000 {
  5126. dmas = <0x0 0x8>;
  5127. };
  5128.  
  5129. mmc@480d1000 {
  5130. dmas = <0x0 0x8>;
  5131. };
  5132.  
  5133. mmc@480d5000 {
  5134. dmas = <0x0 0x8>;
  5135. pinctrl-0 = <0x0>;
  5136. vmmc-supply = <0x0>;
  5137.  
  5138. wlcore@2 {
  5139. interrupt-parent = <0x0>;
  5140. };
  5141. };
  5142.  
  5143. mcpdm@40132000 {
  5144. dmas = <0x0 0x8>;
  5145. pinctrl-0 = <0x0>;
  5146. };
  5147.  
  5148. dmic@4012e000 {
  5149. dmas = <0x0>;
  5150. };
  5151.  
  5152. mcbsp@40122000 {
  5153. dmas = <0x0 0x8>;
  5154. pinctrl-0 = <0x0>;
  5155. };
  5156.  
  5157. mcbsp@40124000 {
  5158. dmas = <0x0 0x8>;
  5159. };
  5160.  
  5161. mcbsp@40126000 {
  5162. dmas = <0x0 0x8>;
  5163. };
  5164.  
  5165. mcbsp@48096000 {
  5166. dmas = <0x0 0x8>;
  5167. };
  5168.  
  5169. emif@4c000000 {
  5170. device-handle = <0x0>;
  5171. };
  5172.  
  5173. emif@4d000000 {
  5174. device-handle = <0x0>;
  5175. };
  5176.  
  5177. ocp2scp@4a0ad000 {
  5178.  
  5179. usb2phy@4a0ad080 {
  5180. ctrl-module = <0x0>;
  5181. clocks = <0x0>;
  5182. };
  5183. };
  5184.  
  5185. usbhshost@4a064000 {
  5186. clocks = <0x0 0x4 0x8>;
  5187.  
  5188. ohci@4a064800 {
  5189. interrupt-parent = <0x0>;
  5190. };
  5191.  
  5192. ehci@4a064c00 {
  5193. interrupt-parent = <0x0>;
  5194. phys = <0x0>;
  5195. };
  5196. };
  5197.  
  5198. usb_otg_hs@4a0ab000 {
  5199. usb-phy = <0x0>;
  5200. phys = <0x0>;
  5201. ctrl-module = <0x0>;
  5202. };
  5203.  
  5204. aes@4b501000 {
  5205. dmas = <0x0 0x8>;
  5206. };
  5207.  
  5208. des@480a5000 {
  5209. dmas = <0x0 0x8>;
  5210. };
  5211.  
  5212. regulator-abb-mpu {
  5213. clocks = <0x0>;
  5214. };
  5215.  
  5216. regulator-abb-iva {
  5217. clocks = <0x0>;
  5218. };
  5219.  
  5220. dss@58000000 {
  5221. clocks = <0x0>;
  5222.  
  5223. dispc@58001000 {
  5224. clocks = <0x0>;
  5225. };
  5226.  
  5227. encoder@58002000 {
  5228. clocks = <0x0 0x4>;
  5229. };
  5230.  
  5231. encoder@58003000 {
  5232. clocks = <0x0>;
  5233. };
  5234.  
  5235. encoder@58004000 {
  5236. clocks = <0x0 0x4>;
  5237. };
  5238.  
  5239. encoder@58005000 {
  5240. clocks = <0x0 0x4>;
  5241. vdd-supply = <0x0>;
  5242. };
  5243.  
  5244. encoder@58006000 {
  5245. clocks = <0x0 0x4>;
  5246. dmas = <0x0>;
  5247. vdda-supply = <0x0>;
  5248.  
  5249. port {
  5250.  
  5251. endpoint {
  5252. remote-endpoint = <0x0>;
  5253. };
  5254. };
  5255. };
  5256.  
  5257. port {
  5258.  
  5259. endpoint {
  5260. remote-endpoint = <0x0>;
  5261. };
  5262. };
  5263. };
  5264.  
  5265. bandgap {
  5266. gpios = <0x0>;
  5267. };
  5268. };
  5269.  
  5270. thermal-zones {
  5271.  
  5272. cpu_thermal {
  5273. thermal-sensors = <0x0>;
  5274.  
  5275. cooling-maps {
  5276.  
  5277. map0 {
  5278. trip = <0x0>;
  5279. cooling-device = <0x0>;
  5280. };
  5281. };
  5282. };
  5283. };
  5284.  
  5285. leds {
  5286. pinctrl-0 = <0x0 0x4>;
  5287.  
  5288. heartbeat {
  5289. gpios = <0x0>;
  5290. };
  5291.  
  5292. mmc {
  5293. gpios = <0x0>;
  5294. };
  5295. };
  5296.  
  5297. sound {
  5298. ti,mcpdm = <0x0>;
  5299. ti,twl6040 = <0x0>;
  5300. };
  5301.  
  5302. hsusb1_power_reg {
  5303. gpio = <0x0>;
  5304. };
  5305.  
  5306. hsusb1_phy {
  5307. reset-gpios = <0x0>;
  5308. vcc-supply = <0x0>;
  5309. clocks = <0x0>;
  5310. };
  5311.  
  5312. wl12xx_vmmc {
  5313. pinctrl-0 = <0x0>;
  5314. gpio = <0x0>;
  5315. };
  5316.  
  5317. encoder@0 {
  5318. powerdown-gpios = <0x0>;
  5319.  
  5320. ports {
  5321.  
  5322. port@0 {
  5323.  
  5324. endpoint@0 {
  5325. remote-endpoint = <0x0>;
  5326. };
  5327. };
  5328.  
  5329. port@1 {
  5330.  
  5331. endpoint@0 {
  5332. remote-endpoint = <0x0>;
  5333. };
  5334. };
  5335. };
  5336. };
  5337.  
  5338. connector@0 {
  5339. ddc-i2c-bus = <0x0>;
  5340.  
  5341. port {
  5342.  
  5343. endpoint {
  5344. remote-endpoint = <0x0>;
  5345. };
  5346. };
  5347. };
  5348.  
  5349. encoder@1 {
  5350. gpios = <0x0 0xc 0x18>;
  5351.  
  5352. ports {
  5353.  
  5354. port@0 {
  5355.  
  5356. endpoint@0 {
  5357. remote-endpoint = <0x0>;
  5358. };
  5359. };
  5360.  
  5361. port@1 {
  5362.  
  5363. endpoint@0 {
  5364. remote-endpoint = <0x0>;
  5365. };
  5366. };
  5367. };
  5368. };
  5369.  
  5370. connector@1 {
  5371.  
  5372. port {
  5373.  
  5374. endpoint {
  5375. remote-endpoint = <0x0>;
  5376. };
  5377. };
  5378. };
  5379. };
  5380. };
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