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  1. --------------------------------------------------------------------------------
  2. Release 14.7 Trace (lin64)
  3. Copyright (c) 1995-2013 Xilinx, Inc. All rights reserved.
  4.  
  5. /opt/Xilinx/14.7/ISE_DS/ISE/bin/lin64/unwrapped/trce -intstyle ise -v 3 -s 2 -n
  6. 3 -fastpaths -xml orpsoc_top.twx orpsoc_top.ncd -o orpsoc_top.twr
  7. orpsoc_top.pcf
  8.  
  9. Design file: orpsoc_top.ncd
  10. Physical constraint file: orpsoc_top.pcf
  11. Device,package,speed: xc7a100t,csg324,C,-2 (PRODUCTION 1.10 2013-10-13)
  12. Report level: verbose report
  13.  
  14. Environment Variable Effect
  15. -------------------- ------
  16. NONE No environment variables were set
  17. --------------------------------------------------------------------------------
  18.  
  19. INFO:Timing:3412 - To improve timing, see the Timing Closure User Guide (UG612).
  20. INFO:Timing:2752 - To get complete path coverage, use the unconstrained paths
  21. option. All paths that are not constrained will be reported in the
  22. unconstrained paths section(s) of the report.
  23. INFO:Timing:3339 - The clock-to-out numbers in this timing report are based on
  24. a 50 Ohm transmission line loading model. For the details of this model,
  25. and for more information on accounting for different loading conditions,
  26. please see the device datasheet.
  27.  
  28. ================================================================================
  29. Timing constraint: TS_sys_clk_pin = PERIOD TIMEGRP "sys_clk_pin" 100 MHz HIGH
  30. 50%;
  31. For more information, see Period Analysis in the Timing Closure User Guide (UG612).
  32.  
  33. 0 paths analyzed, 0 endpoints analyzed, 0 failing endpoints
  34. 0 timing errors detected. (0 component switching limit errors)
  35. Minimum period is 4.000ns.
  36. --------------------------------------------------------------------------------
  37.  
  38. Component Switching Limit Checks: TS_sys_clk_pin = PERIOD TIMEGRP "sys_clk_pin" 100 MHz HIGH 50%;
  39. --------------------------------------------------------------------------------
  40. Slack: 6.000ns (period - (min low pulse limit / (low pulse / period)))
  41. Period: 10.000ns
  42. Low pulse: 5.000ns
  43. Low pulse limit: 2.000ns (Tmmcmpw_CLKIN1_100_150)
  44. Physical resource: clkgen0/mmcm_adv_inst/CLKIN1
  45. Logical resource: clkgen0/mmcm_adv_inst/CLKIN1
  46. Location pin: MMCME2_ADV_X1Y2.CLKIN1
  47. Clock network: clkgen0/clkin1
  48. --------------------------------------------------------------------------------
  49. Slack: 6.000ns (period - (min high pulse limit / (high pulse / period)))
  50. Period: 10.000ns
  51. High pulse: 5.000ns
  52. High pulse limit: 2.000ns (Tmmcmpw_CLKIN1_100_150)
  53. Physical resource: clkgen0/mmcm_adv_inst/CLKIN1
  54. Logical resource: clkgen0/mmcm_adv_inst/CLKIN1
  55. Location pin: MMCME2_ADV_X1Y2.CLKIN1
  56. Clock network: clkgen0/clkin1
  57. --------------------------------------------------------------------------------
  58. Slack: 8.751ns (period - min period limit)
  59. Period: 10.000ns
  60. Min period limit: 1.249ns (800.641MHz) (Tmmcmper_CLKIN(Finmax))
  61. Physical resource: clkgen0/mmcm_adv_inst/CLKIN1
  62. Logical resource: clkgen0/mmcm_adv_inst/CLKIN1
  63. Location pin: MMCME2_ADV_X1Y2.CLKIN1
  64. Clock network: clkgen0/clkin1
  65. --------------------------------------------------------------------------------
  66.  
  67. ================================================================================
  68. Timing constraint: TS_clkgen0_clkout0 = PERIOD TIMEGRP "clkgen0_clkout0"
  69. TS_sys_clk_pin * 0.5 HIGH 50%;
  70. For more information, see Period Analysis in the Timing Closure User Guide (UG612).
  71.  
  72. 4202623 paths analyzed, 14100 endpoints analyzed, 0 failing endpoints
  73. 0 timing errors detected. (0 setup errors, 0 hold errors, 0 component switching limit errors)
  74. Minimum period is 13.466ns.
  75. --------------------------------------------------------------------------------
  76.  
  77. Paths for end point mor1kx0/mor1kx_cpu/cappuccino.mor1kx_cpu/mor1kx_fetch_cappuccino/icache_gen.mor1kx_icache/way_memories[1].way_data_ram/Mram_mem1 (RAMB36_X3Y17.ADDRBWRADDRL13), 3863 paths
  78. --------------------------------------------------------------------------------
  79. Slack (setup path): 6.534ns (requirement - (data path - clock path skew + uncertainty))
  80. Source: mor1kx0/mor1kx_cpu/cappuccino.mor1kx_cpu/mor1kx_lsu_cappuccino/dmmu_gen.mor1kx_dmmu/dtlb_match_regs/Mram_mem (RAM)
  81. Destination: mor1kx0/mor1kx_cpu/cappuccino.mor1kx_cpu/mor1kx_fetch_cappuccino/icache_gen.mor1kx_icache/way_memories[1].way_data_ram/Mram_mem1 (RAM)
  82. Requirement: 20.000ns
  83. Data Path Delay: 13.351ns (Levels of Logic = 9)
  84. Clock Path Skew: -0.033ns (0.757 - 0.790)
  85. Source Clock: wb_clk rising at 0.000ns
  86. Destination Clock: wb_clk rising at 20.000ns
  87. Clock Uncertainty: 0.082ns
  88.  
  89. Clock Uncertainty: 0.082ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE
  90. Total System Jitter (TSJ): 0.070ns
  91. Discrete Jitter (DJ): 0.147ns
  92. Phase Error (PE): 0.000ns
  93.  
  94. Maximum Data Path at Slow Process Corner: mor1kx0/mor1kx_cpu/cappuccino.mor1kx_cpu/mor1kx_lsu_cappuccino/dmmu_gen.mor1kx_dmmu/dtlb_match_regs/Mram_mem to mor1kx0/mor1kx_cpu/cappuccino.mor1kx_cpu/mor1kx_fetch_cappuccino/icache_gen.mor1kx_icache/way_memories[1].way_data_ram/Mram_mem1
  95. Location Delay type Delay(ns) Physical Resource
  96. Logical Resource(s)
  97. -------------------------------------------------------- -------------------
  98. RAMB36_X3Y14.DOBDO0 Trcko_DOB 2.125 mor1kx0/mor1kx_cpu/cappuccino.mor1kx_cpu/mor1kx_lsu_cappuccino/dmmu_gen.mor1kx_dmmu/dtlb_match_regs/Mram_mem
  99. mor1kx0/mor1kx_cpu/cappuccino.mor1kx_cpu/mor1kx_lsu_cappuccino/dmmu_gen.mor1kx_dmmu/dtlb_match_regs/Mram_mem
  100. SLICE_X76Y76.C1 net (fanout=46) 1.200 mor1kx0/mor1kx_cpu/cappuccino.mor1kx_cpu/mor1kx_lsu_cappuccino/dmmu_gen.mor1kx_dmmu/dtlb_match_huge_dout<0>
  101. SLICE_X76Y76.C Tilo 0.105 mor1kx0/mor1kx_cpu/cappuccino.mor1kx_cpu/mor1kx_lsu_cappuccino/dmmu_gen.mor1kx_dmmu/tlb_huge
  102. mor1kx0/mor1kx_cpu/cappuccino.mor1kx_cpu/mor1kx_lsu_cappuccino/dmmu_gen.mor1kx_dmmu/out1
  103. SLICE_X77Y76.A3 net (fanout=2) 0.520 mor1kx0/mor1kx_cpu/cappuccino.mor1kx_cpu/mor1kx_lsu_cappuccino/dmmu_gen.mor1kx_dmmu/tlb_huge
  104. SLICE_X77Y76.A Tilo 0.105 mor1kx0/mor1kx_cpu/cappuccino.mor1kx_cpu/mor1kx_ctrl_cappuccino/mfspr_dat_o<26>5
  105. mor1kx0/mor1kx_cpu/cappuccino.mor1kx_cpu/mor1kx_lsu_cappuccino/dmmu_gen.mor1kx_dmmu/Mmux_pagefault_o12
  106. SLICE_X68Y75.C2 net (fanout=2) 0.884 mor1kx0/mor1kx_cpu/cappuccino.mor1kx_cpu/mor1kx_lsu_cappuccino/dmmu_gen.mor1kx_dmmu/Mmux_pagefault_o11
  107. SLICE_X68Y75.C Tilo 0.105 mor1kx0/mor1kx_cpu/cappuccino.mor1kx_cpu/mor1kx_lsu_cappuccino/pagefault
  108. mor1kx0/mor1kx_cpu/cappuccino.mor1kx_cpu/mor1kx_lsu_cappuccino/dmmu_gen.mor1kx_dmmu/Mmux_pagefault_o13
  109. SLICE_X66Y75.D2 net (fanout=8) 0.724 mor1kx0/mor1kx_cpu/cappuccino.mor1kx_cpu/mor1kx_lsu_cappuccino/pagefault
  110. SLICE_X66Y75.CMUX Topdc 0.443 mor1kx0/mor1kx_cpu/cappuccino.mor1kx_cpu/mor1kx_lsu_cappuccino/atomic_gen.atomic_flag_set
  111. mor1kx0/mor1kx_cpu/cappuccino.mor1kx_cpu/mor1kx_lsu_cappuccino/dmmu_gen.mor1kx_dmmu/tlb_miss_o8_SW0_F
  112. mor1kx0/mor1kx_cpu/cappuccino.mor1kx_cpu/mor1kx_lsu_cappuccino/dmmu_gen.mor1kx_dmmu/tlb_miss_o8_SW0
  113. SLICE_X62Y71.B1 net (fanout=1) 0.853 N1402
  114. SLICE_X62Y71.B Tilo 0.105 mor1kx0/mor1kx_cpu/cappuccino.mor1kx_cpu/decode_branch_o
  115. mor1kx0/mor1kx_cpu/cappuccino.mor1kx_cpu/mor1kx_lsu_cappuccino/Mmux_lsu_ack11
  116. SLICE_X64Y68.A2 net (fanout=8) 0.859 mor1kx0/mor1kx_cpu/cappuccino.mor1kx_cpu/mor1kx_lsu_cappuccino/Mmux_lsu_ack1
  117. SLICE_X64Y68.A Tilo 0.105 N1400
  118. mor1kx0/mor1kx_cpu/cappuccino.mor1kx_cpu/mor1kx_lsu_cappuccino/lsu_valid_o1_SW5
  119. SLICE_X64Y65.A4 net (fanout=1) 0.586 N1400
  120. SLICE_X64Y65.A Tilo 0.105 mor1kx0/mor1kx_cpu/cappuccino.mor1kx_cpu/mor1kx_fetch_cappuccino/addr_valid
  121. mor1kx0/mor1kx_cpu/cappuccino.mor1kx_cpu/mor1kx_ctrl_cappuccino/padv_fetch_o1
  122. SLICE_X64Y65.B5 net (fanout=33) 0.275 mor1kx0/mor1kx_cpu/cappuccino.mor1kx_cpu/padv_fetch_o
  123. SLICE_X64Y65.B Tilo 0.105 mor1kx0/mor1kx_cpu/cappuccino.mor1kx_cpu/mor1kx_fetch_cappuccino/addr_valid
  124. mor1kx0/mor1kx_cpu/cappuccino.mor1kx_cpu/mor1kx_fetch_cappuccino/addr_valid3
  125. SLICE_X60Y59.D1 net (fanout=32) 1.106 mor1kx0/mor1kx_cpu/cappuccino.mor1kx_cpu/mor1kx_fetch_cappuccino/addr_valid
  126. SLICE_X60Y59.D Tilo 0.105 mor1kx0/mor1kx_cpu/cappuccino.mor1kx_cpu/mor1kx_fetch_cappuccino/pc_fetch<11>
  127. mor1kx0/mor1kx_cpu/cappuccino.mor1kx_cpu/mor1kx_fetch_cappuccino/Mmux_ic_addr65
  128. RAMB36_X3Y17.ADDRBWRADDRL13 net (fanout=10) 2.446 mor1kx0/mor1kx_cpu/cappuccino.mor1kx_cpu/mor1kx_fetch_cappuccino/ic_addr<11>
  129. RAMB36_X3Y17.CLKBWRCLKL Trcck_ADDRB 0.490 mor1kx0/mor1kx_cpu/cappuccino.mor1kx_cpu/mor1kx_fetch_cappuccino/icache_gen.mor1kx_icache/way_memories[1].way_data_ram/Mram_mem1
  130. mor1kx0/mor1kx_cpu/cappuccino.mor1kx_cpu/mor1kx_fetch_cappuccino/icache_gen.mor1kx_icache/way_memories[1].way_data_ram/Mram_mem1
  131. -------------------------------------------------------- ---------------------------
  132. Total 13.351ns (3.898ns logic, 9.453ns route)
  133. (29.2% logic, 70.8% route)
  134.  
  135. --------------------------------------------------------------------------------
  136. Slack (setup path): 6.534ns (requirement - (data path - clock path skew + uncertainty))
  137. Source: mor1kx0/mor1kx_cpu/cappuccino.mor1kx_cpu/mor1kx_lsu_cappuccino/dmmu_gen.mor1kx_dmmu/dtlb_match_regs/Mram_mem (RAM)
  138. Destination: mor1kx0/mor1kx_cpu/cappuccino.mor1kx_cpu/mor1kx_fetch_cappuccino/icache_gen.mor1kx_icache/way_memories[1].way_data_ram/Mram_mem1 (RAM)
  139. Requirement: 20.000ns
  140. Data Path Delay: 13.351ns (Levels of Logic = 9)
  141. Clock Path Skew: -0.033ns (0.757 - 0.790)
  142. Source Clock: wb_clk rising at 0.000ns
  143. Destination Clock: wb_clk rising at 20.000ns
  144. Clock Uncertainty: 0.082ns
  145.  
  146. Clock Uncertainty: 0.082ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE
  147. Total System Jitter (TSJ): 0.070ns
  148. Discrete Jitter (DJ): 0.147ns
  149. Phase Error (PE): 0.000ns
  150.  
  151. Maximum Data Path at Slow Process Corner: mor1kx0/mor1kx_cpu/cappuccino.mor1kx_cpu/mor1kx_lsu_cappuccino/dmmu_gen.mor1kx_dmmu/dtlb_match_regs/Mram_mem to mor1kx0/mor1kx_cpu/cappuccino.mor1kx_cpu/mor1kx_fetch_cappuccino/icache_gen.mor1kx_icache/way_memories[1].way_data_ram/Mram_mem1
  152. Location Delay type Delay(ns) Physical Resource
  153. Logical Resource(s)
  154. -------------------------------------------------------- -------------------
  155. RAMB36_X3Y14.DOBDO0 Trcko_DOB 2.125 mor1kx0/mor1kx_cpu/cappuccino.mor1kx_cpu/mor1kx_lsu_cappuccino/dmmu_gen.mor1kx_dmmu/dtlb_match_regs/Mram_mem
  156. mor1kx0/mor1kx_cpu/cappuccino.mor1kx_cpu/mor1kx_lsu_cappuccino/dmmu_gen.mor1kx_dmmu/dtlb_match_regs/Mram_mem
  157. SLICE_X76Y76.C1 net (fanout=46) 1.200 mor1kx0/mor1kx_cpu/cappuccino.mor1kx_cpu/mor1kx_lsu_cappuccino/dmmu_gen.mor1kx_dmmu/dtlb_match_huge_dout<0>
  158. SLICE_X76Y76.C Tilo 0.105 mor1kx0/mor1kx_cpu/cappuccino.mor1kx_cpu/mor1kx_lsu_cappuccino/dmmu_gen.mor1kx_dmmu/tlb_huge
  159. mor1kx0/mor1kx_cpu/cappuccino.mor1kx_cpu/mor1kx_lsu_cappuccino/dmmu_gen.mor1kx_dmmu/out1
  160. SLICE_X77Y76.A3 net (fanout=2) 0.520 mor1kx0/mor1kx_cpu/cappuccino.mor1kx_cpu/mor1kx_lsu_cappuccino/dmmu_gen.mor1kx_dmmu/tlb_huge
  161. SLICE_X77Y76.A Tilo 0.105 mor1kx0/mor1kx_cpu/cappuccino.mor1kx_cpu/mor1kx_ctrl_cappuccino/mfspr_dat_o<26>5
  162. mor1kx0/mor1kx_cpu/cappuccino.mor1kx_cpu/mor1kx_lsu_cappuccino/dmmu_gen.mor1kx_dmmu/Mmux_pagefault_o12
  163. SLICE_X68Y75.C2 net (fanout=2) 0.884 mor1kx0/mor1kx_cpu/cappuccino.mor1kx_cpu/mor1kx_lsu_cappuccino/dmmu_gen.mor1kx_dmmu/Mmux_pagefault_o11
  164. SLICE_X68Y75.C Tilo 0.105 mor1kx0/mor1kx_cpu/cappuccino.mor1kx_cpu/mor1kx_lsu_cappuccino/pagefault
  165. mor1kx0/mor1kx_cpu/cappuccino.mor1kx_cpu/mor1kx_lsu_cappuccino/dmmu_gen.mor1kx_dmmu/Mmux_pagefault_o13
  166. SLICE_X66Y75.D2 net (fanout=8) 0.724 mor1kx0/mor1kx_cpu/cappuccino.mor1kx_cpu/mor1kx_lsu_cappuccino/pagefault
  167. SLICE_X66Y75.CMUX Topdc 0.443 mor1kx0/mor1kx_cpu/cappuccino.mor1kx_cpu/mor1kx_lsu_cappuccino/atomic_gen.atomic_flag_set
  168. mor1kx0/mor1kx_cpu/cappuccino.mor1kx_cpu/mor1kx_lsu_cappuccino/dmmu_gen.mor1kx_dmmu/tlb_miss_o8_SW0_F
  169. mor1kx0/mor1kx_cpu/cappuccino.mor1kx_cpu/mor1kx_lsu_cappuccino/dmmu_gen.mor1kx_dmmu/tlb_miss_o8_SW0
  170. SLICE_X62Y71.B1 net (fanout=1) 0.853 N1402
  171. SLICE_X62Y71.B Tilo 0.105 mor1kx0/mor1kx_cpu/cappuccino.mor1kx_cpu/decode_branch_o
  172. mor1kx0/mor1kx_cpu/cappuccino.mor1kx_cpu/mor1kx_lsu_cappuccino/Mmux_lsu_ack11
  173. SLICE_X64Y68.A2 net (fanout=8) 0.859 mor1kx0/mor1kx_cpu/cappuccino.mor1kx_cpu/mor1kx_lsu_cappuccino/Mmux_lsu_ack1
  174. SLICE_X64Y68.A Tilo 0.105 N1400
  175. mor1kx0/mor1kx_cpu/cappuccino.mor1kx_cpu/mor1kx_lsu_cappuccino/lsu_valid_o1_SW5
  176. SLICE_X64Y65.A4 net (fanout=1) 0.586 N1400
  177. SLICE_X64Y65.A Tilo 0.105 mor1kx0/mor1kx_cpu/cappuccino.mor1kx_cpu/mor1kx_fetch_cappuccino/addr_valid
  178. mor1kx0/mor1kx_cpu/cappuccino.mor1kx_cpu/mor1kx_ctrl_cappuccino/padv_fetch_o1
  179. SLICE_X64Y65.B5 net (fanout=33) 0.275 mor1kx0/mor1kx_cpu/cappuccino.mor1kx_cpu/padv_fetch_o
  180. SLICE_X64Y65.B Tilo 0.105 mor1kx0/mor1kx_cpu/cappuccino.mor1kx_cpu/mor1kx_fetch_cappuccino/addr_valid
  181. mor1kx0/mor1kx_cpu/cappuccino.mor1kx_cpu/mor1kx_fetch_cappuccino/addr_valid3
  182. SLICE_X60Y59.D1 net (fanout=32) 1.106 mor1kx0/mor1kx_cpu/cappuccino.mor1kx_cpu/mor1kx_fetch_cappuccino/addr_valid
  183. SLICE_X60Y59.D Tilo 0.105 mor1kx0/mor1kx_cpu/cappuccino.mor1kx_cpu/mor1kx_fetch_cappuccino/pc_fetch<11>
  184. mor1kx0/mor1kx_cpu/cappuccino.mor1kx_cpu/mor1kx_fetch_cappuccino/Mmux_ic_addr65
  185. RAMB36_X3Y17.ADDRBWRADDRL13 net (fanout=10) 2.446 mor1kx0/mor1kx_cpu/cappuccino.mor1kx_cpu/mor1kx_fetch_cappuccino/ic_addr<11>
  186. RAMB36_X3Y17.CLKBWRCLKL Trcck_ADDRB 0.490 mor1kx0/mor1kx_cpu/cappuccino.mor1kx_cpu/mor1kx_fetch_cappuccino/icache_gen.mor1kx_icache/way_memories[1].way_data_ram/Mram_mem1
  187. mor1kx0/mor1kx_cpu/cappuccino.mor1kx_cpu/mor1kx_fetch_cappuccino/icache_gen.mor1kx_icache/way_memories[1].way_data_ram/Mram_mem1
  188. -------------------------------------------------------- ---------------------------
  189. Total 13.351ns (3.898ns logic, 9.453ns route)
  190. (29.2% logic, 70.8% route)
  191.  
  192. --------------------------------------------------------------------------------
  193. Slack (setup path): 6.540ns (requirement - (data path - clock path skew + uncertainty))
  194. Source: mor1kx0/mor1kx_cpu/cappuccino.mor1kx_cpu/mor1kx_lsu_cappuccino/dmmu_gen.mor1kx_dmmu/dtlb_match_regs/Mram_mem (RAM)
  195. Destination: mor1kx0/mor1kx_cpu/cappuccino.mor1kx_cpu/mor1kx_fetch_cappuccino/icache_gen.mor1kx_icache/way_memories[1].way_data_ram/Mram_mem1 (RAM)
  196. Requirement: 20.000ns
  197. Data Path Delay: 13.345ns (Levels of Logic = 9)
  198. Clock Path Skew: -0.033ns (0.757 - 0.790)
  199. Source Clock: wb_clk rising at 0.000ns
  200. Destination Clock: wb_clk rising at 20.000ns
  201. Clock Uncertainty: 0.082ns
  202.  
  203. Clock Uncertainty: 0.082ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE
  204. Total System Jitter (TSJ): 0.070ns
  205. Discrete Jitter (DJ): 0.147ns
  206. Phase Error (PE): 0.000ns
  207.  
  208. Maximum Data Path at Slow Process Corner: mor1kx0/mor1kx_cpu/cappuccino.mor1kx_cpu/mor1kx_lsu_cappuccino/dmmu_gen.mor1kx_dmmu/dtlb_match_regs/Mram_mem to mor1kx0/mor1kx_cpu/cappuccino.mor1kx_cpu/mor1kx_fetch_cappuccino/icache_gen.mor1kx_icache/way_memories[1].way_data_ram/Mram_mem1
  209. Location Delay type Delay(ns) Physical Resource
  210. Logical Resource(s)
  211. -------------------------------------------------------- -------------------
  212. RAMB36_X3Y14.DOBDO0 Trcko_DOB 2.125 mor1kx0/mor1kx_cpu/cappuccino.mor1kx_cpu/mor1kx_lsu_cappuccino/dmmu_gen.mor1kx_dmmu/dtlb_match_regs/Mram_mem
  213. mor1kx0/mor1kx_cpu/cappuccino.mor1kx_cpu/mor1kx_lsu_cappuccino/dmmu_gen.mor1kx_dmmu/dtlb_match_regs/Mram_mem
  214. SLICE_X76Y76.C1 net (fanout=46) 1.200 mor1kx0/mor1kx_cpu/cappuccino.mor1kx_cpu/mor1kx_lsu_cappuccino/dmmu_gen.mor1kx_dmmu/dtlb_match_huge_dout<0>
  215. SLICE_X76Y76.C Tilo 0.105 mor1kx0/mor1kx_cpu/cappuccino.mor1kx_cpu/mor1kx_lsu_cappuccino/dmmu_gen.mor1kx_dmmu/tlb_huge
  216. mor1kx0/mor1kx_cpu/cappuccino.mor1kx_cpu/mor1kx_lsu_cappuccino/dmmu_gen.mor1kx_dmmu/out1
  217. SLICE_X77Y76.A3 net (fanout=2) 0.520 mor1kx0/mor1kx_cpu/cappuccino.mor1kx_cpu/mor1kx_lsu_cappuccino/dmmu_gen.mor1kx_dmmu/tlb_huge
  218. SLICE_X77Y76.A Tilo 0.105 mor1kx0/mor1kx_cpu/cappuccino.mor1kx_cpu/mor1kx_ctrl_cappuccino/mfspr_dat_o<26>5
  219. mor1kx0/mor1kx_cpu/cappuccino.mor1kx_cpu/mor1kx_lsu_cappuccino/dmmu_gen.mor1kx_dmmu/Mmux_pagefault_o12
  220. SLICE_X68Y75.C2 net (fanout=2) 0.884 mor1kx0/mor1kx_cpu/cappuccino.mor1kx_cpu/mor1kx_lsu_cappuccino/dmmu_gen.mor1kx_dmmu/Mmux_pagefault_o11
  221. SLICE_X68Y75.C Tilo 0.105 mor1kx0/mor1kx_cpu/cappuccino.mor1kx_cpu/mor1kx_lsu_cappuccino/pagefault
  222. mor1kx0/mor1kx_cpu/cappuccino.mor1kx_cpu/mor1kx_lsu_cappuccino/dmmu_gen.mor1kx_dmmu/Mmux_pagefault_o13
  223. SLICE_X66Y75.C2 net (fanout=8) 0.713 mor1kx0/mor1kx_cpu/cappuccino.mor1kx_cpu/mor1kx_lsu_cappuccino/pagefault
  224. SLICE_X66Y75.CMUX Tilo 0.448 mor1kx0/mor1kx_cpu/cappuccino.mor1kx_cpu/mor1kx_lsu_cappuccino/atomic_gen.atomic_flag_set
  225. mor1kx0/mor1kx_cpu/cappuccino.mor1kx_cpu/mor1kx_lsu_cappuccino/dmmu_gen.mor1kx_dmmu/tlb_miss_o8_SW0_G
  226. mor1kx0/mor1kx_cpu/cappuccino.mor1kx_cpu/mor1kx_lsu_cappuccino/dmmu_gen.mor1kx_dmmu/tlb_miss_o8_SW0
  227. SLICE_X62Y71.B1 net (fanout=1) 0.853 N1402
  228. SLICE_X62Y71.B Tilo 0.105 mor1kx0/mor1kx_cpu/cappuccino.mor1kx_cpu/decode_branch_o
  229. mor1kx0/mor1kx_cpu/cappuccino.mor1kx_cpu/mor1kx_lsu_cappuccino/Mmux_lsu_ack11
  230. SLICE_X64Y68.A2 net (fanout=8) 0.859 mor1kx0/mor1kx_cpu/cappuccino.mor1kx_cpu/mor1kx_lsu_cappuccino/Mmux_lsu_ack1
  231. SLICE_X64Y68.A Tilo 0.105 N1400
  232. mor1kx0/mor1kx_cpu/cappuccino.mor1kx_cpu/mor1kx_lsu_cappuccino/lsu_valid_o1_SW5
  233. SLICE_X64Y65.A4 net (fanout=1) 0.586 N1400
  234. SLICE_X64Y65.A Tilo 0.105 mor1kx0/mor1kx_cpu/cappuccino.mor1kx_cpu/mor1kx_fetch_cappuccino/addr_valid
  235. mor1kx0/mor1kx_cpu/cappuccino.mor1kx_cpu/mor1kx_ctrl_cappuccino/padv_fetch_o1
  236. SLICE_X64Y65.B5 net (fanout=33) 0.275 mor1kx0/mor1kx_cpu/cappuccino.mor1kx_cpu/padv_fetch_o
  237. SLICE_X64Y65.B Tilo 0.105 mor1kx0/mor1kx_cpu/cappuccino.mor1kx_cpu/mor1kx_fetch_cappuccino/addr_valid
  238. mor1kx0/mor1kx_cpu/cappuccino.mor1kx_cpu/mor1kx_fetch_cappuccino/addr_valid3
  239. SLICE_X60Y59.D1 net (fanout=32) 1.106 mor1kx0/mor1kx_cpu/cappuccino.mor1kx_cpu/mor1kx_fetch_cappuccino/addr_valid
  240. SLICE_X60Y59.D Tilo 0.105 mor1kx0/mor1kx_cpu/cappuccino.mor1kx_cpu/mor1kx_fetch_cappuccino/pc_fetch<11>
  241. mor1kx0/mor1kx_cpu/cappuccino.mor1kx_cpu/mor1kx_fetch_cappuccino/Mmux_ic_addr65
  242. RAMB36_X3Y17.ADDRBWRADDRL13 net (fanout=10) 2.446 mor1kx0/mor1kx_cpu/cappuccino.mor1kx_cpu/mor1kx_fetch_cappuccino/ic_addr<11>
  243. RAMB36_X3Y17.CLKBWRCLKL Trcck_ADDRB 0.490 mor1kx0/mor1kx_cpu/cappuccino.mor1kx_cpu/mor1kx_fetch_cappuccino/icache_gen.mor1kx_icache/way_memories[1].way_data_ram/Mram_mem1
  244. mor1kx0/mor1kx_cpu/cappuccino.mor1kx_cpu/mor1kx_fetch_cappuccino/icache_gen.mor1kx_icache/way_memories[1].way_data_ram/Mram_mem1
  245. -------------------------------------------------------- ---------------------------
  246. Total 13.345ns (3.903ns logic, 9.442ns route)
  247. (29.2% logic, 70.8% route)
  248.  
  249. --------------------------------------------------------------------------------
  250.  
  251. Paths for end point mor1kx0/mor1kx_cpu/cappuccino.mor1kx_cpu/mor1kx_fetch_cappuccino/icache_gen.mor1kx_icache/way_memories[1].way_data_ram/Mram_mem1 (RAMB36_X3Y17.ADDRBWRADDRU13), 3863 paths
  252. --------------------------------------------------------------------------------
  253. Slack (setup path): 6.534ns (requirement - (data path - clock path skew + uncertainty))
  254. Source: mor1kx0/mor1kx_cpu/cappuccino.mor1kx_cpu/mor1kx_lsu_cappuccino/dmmu_gen.mor1kx_dmmu/dtlb_match_regs/Mram_mem (RAM)
  255. Destination: mor1kx0/mor1kx_cpu/cappuccino.mor1kx_cpu/mor1kx_fetch_cappuccino/icache_gen.mor1kx_icache/way_memories[1].way_data_ram/Mram_mem1 (RAM)
  256. Requirement: 20.000ns
  257. Data Path Delay: 13.351ns (Levels of Logic = 9)
  258. Clock Path Skew: -0.033ns (0.757 - 0.790)
  259. Source Clock: wb_clk rising at 0.000ns
  260. Destination Clock: wb_clk rising at 20.000ns
  261. Clock Uncertainty: 0.082ns
  262.  
  263. Clock Uncertainty: 0.082ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE
  264. Total System Jitter (TSJ): 0.070ns
  265. Discrete Jitter (DJ): 0.147ns
  266. Phase Error (PE): 0.000ns
  267.  
  268. Maximum Data Path at Slow Process Corner: mor1kx0/mor1kx_cpu/cappuccino.mor1kx_cpu/mor1kx_lsu_cappuccino/dmmu_gen.mor1kx_dmmu/dtlb_match_regs/Mram_mem to mor1kx0/mor1kx_cpu/cappuccino.mor1kx_cpu/mor1kx_fetch_cappuccino/icache_gen.mor1kx_icache/way_memories[1].way_data_ram/Mram_mem1
  269. Location Delay type Delay(ns) Physical Resource
  270. Logical Resource(s)
  271. -------------------------------------------------------- -------------------
  272. RAMB36_X3Y14.DOBDO0 Trcko_DOB 2.125 mor1kx0/mor1kx_cpu/cappuccino.mor1kx_cpu/mor1kx_lsu_cappuccino/dmmu_gen.mor1kx_dmmu/dtlb_match_regs/Mram_mem
  273. mor1kx0/mor1kx_cpu/cappuccino.mor1kx_cpu/mor1kx_lsu_cappuccino/dmmu_gen.mor1kx_dmmu/dtlb_match_regs/Mram_mem
  274. SLICE_X76Y76.C1 net (fanout=46) 1.200 mor1kx0/mor1kx_cpu/cappuccino.mor1kx_cpu/mor1kx_lsu_cappuccino/dmmu_gen.mor1kx_dmmu/dtlb_match_huge_dout<0>
  275. SLICE_X76Y76.C Tilo 0.105 mor1kx0/mor1kx_cpu/cappuccino.mor1kx_cpu/mor1kx_lsu_cappuccino/dmmu_gen.mor1kx_dmmu/tlb_huge
  276. mor1kx0/mor1kx_cpu/cappuccino.mor1kx_cpu/mor1kx_lsu_cappuccino/dmmu_gen.mor1kx_dmmu/out1
  277. SLICE_X77Y76.A3 net (fanout=2) 0.520 mor1kx0/mor1kx_cpu/cappuccino.mor1kx_cpu/mor1kx_lsu_cappuccino/dmmu_gen.mor1kx_dmmu/tlb_huge
  278. SLICE_X77Y76.A Tilo 0.105 mor1kx0/mor1kx_cpu/cappuccino.mor1kx_cpu/mor1kx_ctrl_cappuccino/mfspr_dat_o<26>5
  279. mor1kx0/mor1kx_cpu/cappuccino.mor1kx_cpu/mor1kx_lsu_cappuccino/dmmu_gen.mor1kx_dmmu/Mmux_pagefault_o12
  280. SLICE_X68Y75.C2 net (fanout=2) 0.884 mor1kx0/mor1kx_cpu/cappuccino.mor1kx_cpu/mor1kx_lsu_cappuccino/dmmu_gen.mor1kx_dmmu/Mmux_pagefault_o11
  281. SLICE_X68Y75.C Tilo 0.105 mor1kx0/mor1kx_cpu/cappuccino.mor1kx_cpu/mor1kx_lsu_cappuccino/pagefault
  282. mor1kx0/mor1kx_cpu/cappuccino.mor1kx_cpu/mor1kx_lsu_cappuccino/dmmu_gen.mor1kx_dmmu/Mmux_pagefault_o13
  283. SLICE_X66Y75.D2 net (fanout=8) 0.724 mor1kx0/mor1kx_cpu/cappuccino.mor1kx_cpu/mor1kx_lsu_cappuccino/pagefault
  284. SLICE_X66Y75.CMUX Topdc 0.443 mor1kx0/mor1kx_cpu/cappuccino.mor1kx_cpu/mor1kx_lsu_cappuccino/atomic_gen.atomic_flag_set
  285. mor1kx0/mor1kx_cpu/cappuccino.mor1kx_cpu/mor1kx_lsu_cappuccino/dmmu_gen.mor1kx_dmmu/tlb_miss_o8_SW0_F
  286. mor1kx0/mor1kx_cpu/cappuccino.mor1kx_cpu/mor1kx_lsu_cappuccino/dmmu_gen.mor1kx_dmmu/tlb_miss_o8_SW0
  287. SLICE_X62Y71.B1 net (fanout=1) 0.853 N1402
  288. SLICE_X62Y71.B Tilo 0.105 mor1kx0/mor1kx_cpu/cappuccino.mor1kx_cpu/decode_branch_o
  289. mor1kx0/mor1kx_cpu/cappuccino.mor1kx_cpu/mor1kx_lsu_cappuccino/Mmux_lsu_ack11
  290. SLICE_X64Y68.A2 net (fanout=8) 0.859 mor1kx0/mor1kx_cpu/cappuccino.mor1kx_cpu/mor1kx_lsu_cappuccino/Mmux_lsu_ack1
  291. SLICE_X64Y68.A Tilo 0.105 N1400
  292. mor1kx0/mor1kx_cpu/cappuccino.mor1kx_cpu/mor1kx_lsu_cappuccino/lsu_valid_o1_SW5
  293. SLICE_X64Y65.A4 net (fanout=1) 0.586 N1400
  294. SLICE_X64Y65.A Tilo 0.105 mor1kx0/mor1kx_cpu/cappuccino.mor1kx_cpu/mor1kx_fetch_cappuccino/addr_valid
  295. mor1kx0/mor1kx_cpu/cappuccino.mor1kx_cpu/mor1kx_ctrl_cappuccino/padv_fetch_o1
  296. SLICE_X64Y65.B5 net (fanout=33) 0.275 mor1kx0/mor1kx_cpu/cappuccino.mor1kx_cpu/padv_fetch_o
  297. SLICE_X64Y65.B Tilo 0.105 mor1kx0/mor1kx_cpu/cappuccino.mor1kx_cpu/mor1kx_fetch_cappuccino/addr_valid
  298. mor1kx0/mor1kx_cpu/cappuccino.mor1kx_cpu/mor1kx_fetch_cappuccino/addr_valid3
  299. SLICE_X60Y59.D1 net (fanout=32) 1.106 mor1kx0/mor1kx_cpu/cappuccino.mor1kx_cpu/mor1kx_fetch_cappuccino/addr_valid
  300. SLICE_X60Y59.D Tilo 0.105 mor1kx0/mor1kx_cpu/cappuccino.mor1kx_cpu/mor1kx_fetch_cappuccino/pc_fetch<11>
  301. mor1kx0/mor1kx_cpu/cappuccino.mor1kx_cpu/mor1kx_fetch_cappuccino/Mmux_ic_addr65
  302. RAMB36_X3Y17.ADDRBWRADDRU13 net (fanout=10) 2.446 mor1kx0/mor1kx_cpu/cappuccino.mor1kx_cpu/mor1kx_fetch_cappuccino/ic_addr<11>
  303. RAMB36_X3Y17.CLKBWRCLKU Trcck_ADDRB 0.490 mor1kx0/mor1kx_cpu/cappuccino.mor1kx_cpu/mor1kx_fetch_cappuccino/icache_gen.mor1kx_icache/way_memories[1].way_data_ram/Mram_mem1
  304. mor1kx0/mor1kx_cpu/cappuccino.mor1kx_cpu/mor1kx_fetch_cappuccino/icache_gen.mor1kx_icache/way_memories[1].way_data_ram/Mram_mem1
  305. -------------------------------------------------------- ---------------------------
  306. Total 13.351ns (3.898ns logic, 9.453ns route)
  307. (29.2% logic, 70.8% route)
  308.  
  309. --------------------------------------------------------------------------------
  310. Slack (setup path): 6.534ns (requirement - (data path - clock path skew + uncertainty))
  311. Source: mor1kx0/mor1kx_cpu/cappuccino.mor1kx_cpu/mor1kx_lsu_cappuccino/dmmu_gen.mor1kx_dmmu/dtlb_match_regs/Mram_mem (RAM)
  312. Destination: mor1kx0/mor1kx_cpu/cappuccino.mor1kx_cpu/mor1kx_fetch_cappuccino/icache_gen.mor1kx_icache/way_memories[1].way_data_ram/Mram_mem1 (RAM)
  313. Requirement: 20.000ns
  314. Data Path Delay: 13.351ns (Levels of Logic = 9)
  315. Clock Path Skew: -0.033ns (0.757 - 0.790)
  316. Source Clock: wb_clk rising at 0.000ns
  317. Destination Clock: wb_clk rising at 20.000ns
  318. Clock Uncertainty: 0.082ns
  319.  
  320. Clock Uncertainty: 0.082ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE
  321. Total System Jitter (TSJ): 0.070ns
  322. Discrete Jitter (DJ): 0.147ns
  323. Phase Error (PE): 0.000ns
  324.  
  325. Maximum Data Path at Slow Process Corner: mor1kx0/mor1kx_cpu/cappuccino.mor1kx_cpu/mor1kx_lsu_cappuccino/dmmu_gen.mor1kx_dmmu/dtlb_match_regs/Mram_mem to mor1kx0/mor1kx_cpu/cappuccino.mor1kx_cpu/mor1kx_fetch_cappuccino/icache_gen.mor1kx_icache/way_memories[1].way_data_ram/Mram_mem1
  326. Location Delay type Delay(ns) Physical Resource
  327. Logical Resource(s)
  328. -------------------------------------------------------- -------------------
  329. RAMB36_X3Y14.DOBDO0 Trcko_DOB 2.125 mor1kx0/mor1kx_cpu/cappuccino.mor1kx_cpu/mor1kx_lsu_cappuccino/dmmu_gen.mor1kx_dmmu/dtlb_match_regs/Mram_mem
  330. mor1kx0/mor1kx_cpu/cappuccino.mor1kx_cpu/mor1kx_lsu_cappuccino/dmmu_gen.mor1kx_dmmu/dtlb_match_regs/Mram_mem
  331. SLICE_X76Y76.C1 net (fanout=46) 1.200 mor1kx0/mor1kx_cpu/cappuccino.mor1kx_cpu/mor1kx_lsu_cappuccino/dmmu_gen.mor1kx_dmmu/dtlb_match_huge_dout<0>
  332. SLICE_X76Y76.C Tilo 0.105 mor1kx0/mor1kx_cpu/cappuccino.mor1kx_cpu/mor1kx_lsu_cappuccino/dmmu_gen.mor1kx_dmmu/tlb_huge
  333. mor1kx0/mor1kx_cpu/cappuccino.mor1kx_cpu/mor1kx_lsu_cappuccino/dmmu_gen.mor1kx_dmmu/out1
  334. SLICE_X77Y76.A3 net (fanout=2) 0.520 mor1kx0/mor1kx_cpu/cappuccino.mor1kx_cpu/mor1kx_lsu_cappuccino/dmmu_gen.mor1kx_dmmu/tlb_huge
  335. SLICE_X77Y76.A Tilo 0.105 mor1kx0/mor1kx_cpu/cappuccino.mor1kx_cpu/mor1kx_ctrl_cappuccino/mfspr_dat_o<26>5
  336. mor1kx0/mor1kx_cpu/cappuccino.mor1kx_cpu/mor1kx_lsu_cappuccino/dmmu_gen.mor1kx_dmmu/Mmux_pagefault_o12
  337. SLICE_X68Y75.C2 net (fanout=2) 0.884 mor1kx0/mor1kx_cpu/cappuccino.mor1kx_cpu/mor1kx_lsu_cappuccino/dmmu_gen.mor1kx_dmmu/Mmux_pagefault_o11
  338. SLICE_X68Y75.C Tilo 0.105 mor1kx0/mor1kx_cpu/cappuccino.mor1kx_cpu/mor1kx_lsu_cappuccino/pagefault
  339. mor1kx0/mor1kx_cpu/cappuccino.mor1kx_cpu/mor1kx_lsu_cappuccino/dmmu_gen.mor1kx_dmmu/Mmux_pagefault_o13
  340. SLICE_X66Y75.D2 net (fanout=8) 0.724 mor1kx0/mor1kx_cpu/cappuccino.mor1kx_cpu/mor1kx_lsu_cappuccino/pagefault
  341. SLICE_X66Y75.CMUX Topdc 0.443 mor1kx0/mor1kx_cpu/cappuccino.mor1kx_cpu/mor1kx_lsu_cappuccino/atomic_gen.atomic_flag_set
  342. mor1kx0/mor1kx_cpu/cappuccino.mor1kx_cpu/mor1kx_lsu_cappuccino/dmmu_gen.mor1kx_dmmu/tlb_miss_o8_SW0_F
  343. mor1kx0/mor1kx_cpu/cappuccino.mor1kx_cpu/mor1kx_lsu_cappuccino/dmmu_gen.mor1kx_dmmu/tlb_miss_o8_SW0
  344. SLICE_X62Y71.B1 net (fanout=1) 0.853 N1402
  345. SLICE_X62Y71.B Tilo 0.105 mor1kx0/mor1kx_cpu/cappuccino.mor1kx_cpu/decode_branch_o
  346. mor1kx0/mor1kx_cpu/cappuccino.mor1kx_cpu/mor1kx_lsu_cappuccino/Mmux_lsu_ack11
  347. SLICE_X64Y68.A2 net (fanout=8) 0.859 mor1kx0/mor1kx_cpu/cappuccino.mor1kx_cpu/mor1kx_lsu_cappuccino/Mmux_lsu_ack1
  348. SLICE_X64Y68.A Tilo 0.105 N1400
  349. mor1kx0/mor1kx_cpu/cappuccino.mor1kx_cpu/mor1kx_lsu_cappuccino/lsu_valid_o1_SW5
  350. SLICE_X64Y65.A4 net (fanout=1) 0.586 N1400
  351. SLICE_X64Y65.A Tilo 0.105 mor1kx0/mor1kx_cpu/cappuccino.mor1kx_cpu/mor1kx_fetch_cappuccino/addr_valid
  352. mor1kx0/mor1kx_cpu/cappuccino.mor1kx_cpu/mor1kx_ctrl_cappuccino/padv_fetch_o1
  353. SLICE_X64Y65.B5 net (fanout=33) 0.275 mor1kx0/mor1kx_cpu/cappuccino.mor1kx_cpu/padv_fetch_o
  354. SLICE_X64Y65.B Tilo 0.105 mor1kx0/mor1kx_cpu/cappuccino.mor1kx_cpu/mor1kx_fetch_cappuccino/addr_valid
  355. mor1kx0/mor1kx_cpu/cappuccino.mor1kx_cpu/mor1kx_fetch_cappuccino/addr_valid3
  356. SLICE_X60Y59.D1 net (fanout=32) 1.106 mor1kx0/mor1kx_cpu/cappuccino.mor1kx_cpu/mor1kx_fetch_cappuccino/addr_valid
  357. SLICE_X60Y59.D Tilo 0.105 mor1kx0/mor1kx_cpu/cappuccino.mor1kx_cpu/mor1kx_fetch_cappuccino/pc_fetch<11>
  358. mor1kx0/mor1kx_cpu/cappuccino.mor1kx_cpu/mor1kx_fetch_cappuccino/Mmux_ic_addr65
  359. RAMB36_X3Y17.ADDRBWRADDRU13 net (fanout=10) 2.446 mor1kx0/mor1kx_cpu/cappuccino.mor1kx_cpu/mor1kx_fetch_cappuccino/ic_addr<11>
  360. RAMB36_X3Y17.CLKBWRCLKU Trcck_ADDRB 0.490 mor1kx0/mor1kx_cpu/cappuccino.mor1kx_cpu/mor1kx_fetch_cappuccino/icache_gen.mor1kx_icache/way_memories[1].way_data_ram/Mram_mem1
  361. mor1kx0/mor1kx_cpu/cappuccino.mor1kx_cpu/mor1kx_fetch_cappuccino/icache_gen.mor1kx_icache/way_memories[1].way_data_ram/Mram_mem1
  362. -------------------------------------------------------- ---------------------------
  363. Total 13.351ns (3.898ns logic, 9.453ns route)
  364. (29.2% logic, 70.8% route)
  365.  
  366. --------------------------------------------------------------------------------
  367. Slack (setup path): 6.540ns (requirement - (data path - clock path skew + uncertainty))
  368. Source: mor1kx0/mor1kx_cpu/cappuccino.mor1kx_cpu/mor1kx_lsu_cappuccino/dmmu_gen.mor1kx_dmmu/dtlb_match_regs/Mram_mem (RAM)
  369. Destination: mor1kx0/mor1kx_cpu/cappuccino.mor1kx_cpu/mor1kx_fetch_cappuccino/icache_gen.mor1kx_icache/way_memories[1].way_data_ram/Mram_mem1 (RAM)
  370. Requirement: 20.000ns
  371. Data Path Delay: 13.345ns (Levels of Logic = 9)
  372. Clock Path Skew: -0.033ns (0.757 - 0.790)
  373. Source Clock: wb_clk rising at 0.000ns
  374. Destination Clock: wb_clk rising at 20.000ns
  375. Clock Uncertainty: 0.082ns
  376.  
  377. Clock Uncertainty: 0.082ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE
  378. Total System Jitter (TSJ): 0.070ns
  379. Discrete Jitter (DJ): 0.147ns
  380. Phase Error (PE): 0.000ns
  381.  
  382. Maximum Data Path at Slow Process Corner: mor1kx0/mor1kx_cpu/cappuccino.mor1kx_cpu/mor1kx_lsu_cappuccino/dmmu_gen.mor1kx_dmmu/dtlb_match_regs/Mram_mem to mor1kx0/mor1kx_cpu/cappuccino.mor1kx_cpu/mor1kx_fetch_cappuccino/icache_gen.mor1kx_icache/way_memories[1].way_data_ram/Mram_mem1
  383. Location Delay type Delay(ns) Physical Resource
  384. Logical Resource(s)
  385. -------------------------------------------------------- -------------------
  386. RAMB36_X3Y14.DOBDO0 Trcko_DOB 2.125 mor1kx0/mor1kx_cpu/cappuccino.mor1kx_cpu/mor1kx_lsu_cappuccino/dmmu_gen.mor1kx_dmmu/dtlb_match_regs/Mram_mem
  387. mor1kx0/mor1kx_cpu/cappuccino.mor1kx_cpu/mor1kx_lsu_cappuccino/dmmu_gen.mor1kx_dmmu/dtlb_match_regs/Mram_mem
  388. SLICE_X76Y76.C1 net (fanout=46) 1.200 mor1kx0/mor1kx_cpu/cappuccino.mor1kx_cpu/mor1kx_lsu_cappuccino/dmmu_gen.mor1kx_dmmu/dtlb_match_huge_dout<0>
  389. SLICE_X76Y76.C Tilo 0.105 mor1kx0/mor1kx_cpu/cappuccino.mor1kx_cpu/mor1kx_lsu_cappuccino/dmmu_gen.mor1kx_dmmu/tlb_huge
  390. mor1kx0/mor1kx_cpu/cappuccino.mor1kx_cpu/mor1kx_lsu_cappuccino/dmmu_gen.mor1kx_dmmu/out1
  391. SLICE_X77Y76.A3 net (fanout=2) 0.520 mor1kx0/mor1kx_cpu/cappuccino.mor1kx_cpu/mor1kx_lsu_cappuccino/dmmu_gen.mor1kx_dmmu/tlb_huge
  392. SLICE_X77Y76.A Tilo 0.105 mor1kx0/mor1kx_cpu/cappuccino.mor1kx_cpu/mor1kx_ctrl_cappuccino/mfspr_dat_o<26>5
  393. mor1kx0/mor1kx_cpu/cappuccino.mor1kx_cpu/mor1kx_lsu_cappuccino/dmmu_gen.mor1kx_dmmu/Mmux_pagefault_o12
  394. SLICE_X68Y75.C2 net (fanout=2) 0.884 mor1kx0/mor1kx_cpu/cappuccino.mor1kx_cpu/mor1kx_lsu_cappuccino/dmmu_gen.mor1kx_dmmu/Mmux_pagefault_o11
  395. SLICE_X68Y75.C Tilo 0.105 mor1kx0/mor1kx_cpu/cappuccino.mor1kx_cpu/mor1kx_lsu_cappuccino/pagefault
  396. mor1kx0/mor1kx_cpu/cappuccino.mor1kx_cpu/mor1kx_lsu_cappuccino/dmmu_gen.mor1kx_dmmu/Mmux_pagefault_o13
  397. SLICE_X66Y75.C2 net (fanout=8) 0.713 mor1kx0/mor1kx_cpu/cappuccino.mor1kx_cpu/mor1kx_lsu_cappuccino/pagefault
  398. SLICE_X66Y75.CMUX Tilo 0.448 mor1kx0/mor1kx_cpu/cappuccino.mor1kx_cpu/mor1kx_lsu_cappuccino/atomic_gen.atomic_flag_set
  399. mor1kx0/mor1kx_cpu/cappuccino.mor1kx_cpu/mor1kx_lsu_cappuccino/dmmu_gen.mor1kx_dmmu/tlb_miss_o8_SW0_G
  400. mor1kx0/mor1kx_cpu/cappuccino.mor1kx_cpu/mor1kx_lsu_cappuccino/dmmu_gen.mor1kx_dmmu/tlb_miss_o8_SW0
  401. SLICE_X62Y71.B1 net (fanout=1) 0.853 N1402
  402. SLICE_X62Y71.B Tilo 0.105 mor1kx0/mor1kx_cpu/cappuccino.mor1kx_cpu/decode_branch_o
  403. mor1kx0/mor1kx_cpu/cappuccino.mor1kx_cpu/mor1kx_lsu_cappuccino/Mmux_lsu_ack11
  404. SLICE_X64Y68.A2 net (fanout=8) 0.859 mor1kx0/mor1kx_cpu/cappuccino.mor1kx_cpu/mor1kx_lsu_cappuccino/Mmux_lsu_ack1
  405. SLICE_X64Y68.A Tilo 0.105 N1400
  406. mor1kx0/mor1kx_cpu/cappuccino.mor1kx_cpu/mor1kx_lsu_cappuccino/lsu_valid_o1_SW5
  407. SLICE_X64Y65.A4 net (fanout=1) 0.586 N1400
  408. SLICE_X64Y65.A Tilo 0.105 mor1kx0/mor1kx_cpu/cappuccino.mor1kx_cpu/mor1kx_fetch_cappuccino/addr_valid
  409. mor1kx0/mor1kx_cpu/cappuccino.mor1kx_cpu/mor1kx_ctrl_cappuccino/padv_fetch_o1
  410. SLICE_X64Y65.B5 net (fanout=33) 0.275 mor1kx0/mor1kx_cpu/cappuccino.mor1kx_cpu/padv_fetch_o
  411. SLICE_X64Y65.B Tilo 0.105 mor1kx0/mor1kx_cpu/cappuccino.mor1kx_cpu/mor1kx_fetch_cappuccino/addr_valid
  412. mor1kx0/mor1kx_cpu/cappuccino.mor1kx_cpu/mor1kx_fetch_cappuccino/addr_valid3
  413. SLICE_X60Y59.D1 net (fanout=32) 1.106 mor1kx0/mor1kx_cpu/cappuccino.mor1kx_cpu/mor1kx_fetch_cappuccino/addr_valid
  414. SLICE_X60Y59.D Tilo 0.105 mor1kx0/mor1kx_cpu/cappuccino.mor1kx_cpu/mor1kx_fetch_cappuccino/pc_fetch<11>
  415. mor1kx0/mor1kx_cpu/cappuccino.mor1kx_cpu/mor1kx_fetch_cappuccino/Mmux_ic_addr65
  416. RAMB36_X3Y17.ADDRBWRADDRU13 net (fanout=10) 2.446 mor1kx0/mor1kx_cpu/cappuccino.mor1kx_cpu/mor1kx_fetch_cappuccino/ic_addr<11>
  417. RAMB36_X3Y17.CLKBWRCLKU Trcck_ADDRB 0.490 mor1kx0/mor1kx_cpu/cappuccino.mor1kx_cpu/mor1kx_fetch_cappuccino/icache_gen.mor1kx_icache/way_memories[1].way_data_ram/Mram_mem1
  418. mor1kx0/mor1kx_cpu/cappuccino.mor1kx_cpu/mor1kx_fetch_cappuccino/icache_gen.mor1kx_icache/way_memories[1].way_data_ram/Mram_mem1
  419. -------------------------------------------------------- ---------------------------
  420. Total 13.345ns (3.903ns logic, 9.442ns route)
  421. (29.2% logic, 70.8% route)
  422.  
  423. --------------------------------------------------------------------------------
  424.  
  425. Paths for end point mor1kx0/mor1kx_cpu/cappuccino.mor1kx_cpu/mor1kx_fetch_cappuccino/icache_gen.mor1kx_icache/way_memories[1].way_data_ram/Mram_mem1 (RAMB36_X3Y17.ADDRBWRADDRL12), 3859 paths
  426. --------------------------------------------------------------------------------
  427. Slack (setup path): 6.665ns (requirement - (data path - clock path skew + uncertainty))
  428. Source: mor1kx0/mor1kx_cpu/cappuccino.mor1kx_cpu/mor1kx_lsu_cappuccino/dmmu_gen.mor1kx_dmmu/dtlb_match_regs/Mram_mem (RAM)
  429. Destination: mor1kx0/mor1kx_cpu/cappuccino.mor1kx_cpu/mor1kx_fetch_cappuccino/icache_gen.mor1kx_icache/way_memories[1].way_data_ram/Mram_mem1 (RAM)
  430. Requirement: 20.000ns
  431. Data Path Delay: 13.220ns (Levels of Logic = 9)
  432. Clock Path Skew: -0.033ns (0.757 - 0.790)
  433. Source Clock: wb_clk rising at 0.000ns
  434. Destination Clock: wb_clk rising at 20.000ns
  435. Clock Uncertainty: 0.082ns
  436.  
  437. Clock Uncertainty: 0.082ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE
  438. Total System Jitter (TSJ): 0.070ns
  439. Discrete Jitter (DJ): 0.147ns
  440. Phase Error (PE): 0.000ns
  441.  
  442. Maximum Data Path at Slow Process Corner: mor1kx0/mor1kx_cpu/cappuccino.mor1kx_cpu/mor1kx_lsu_cappuccino/dmmu_gen.mor1kx_dmmu/dtlb_match_regs/Mram_mem to mor1kx0/mor1kx_cpu/cappuccino.mor1kx_cpu/mor1kx_fetch_cappuccino/icache_gen.mor1kx_icache/way_memories[1].way_data_ram/Mram_mem1
  443. Location Delay type Delay(ns) Physical Resource
  444. Logical Resource(s)
  445. -------------------------------------------------------- -------------------
  446. RAMB36_X3Y14.DOBDO0 Trcko_DOB 2.125 mor1kx0/mor1kx_cpu/cappuccino.mor1kx_cpu/mor1kx_lsu_cappuccino/dmmu_gen.mor1kx_dmmu/dtlb_match_regs/Mram_mem
  447. mor1kx0/mor1kx_cpu/cappuccino.mor1kx_cpu/mor1kx_lsu_cappuccino/dmmu_gen.mor1kx_dmmu/dtlb_match_regs/Mram_mem
  448. SLICE_X76Y76.C1 net (fanout=46) 1.200 mor1kx0/mor1kx_cpu/cappuccino.mor1kx_cpu/mor1kx_lsu_cappuccino/dmmu_gen.mor1kx_dmmu/dtlb_match_huge_dout<0>
  449. SLICE_X76Y76.C Tilo 0.105 mor1kx0/mor1kx_cpu/cappuccino.mor1kx_cpu/mor1kx_lsu_cappuccino/dmmu_gen.mor1kx_dmmu/tlb_huge
  450. mor1kx0/mor1kx_cpu/cappuccino.mor1kx_cpu/mor1kx_lsu_cappuccino/dmmu_gen.mor1kx_dmmu/out1
  451. SLICE_X77Y76.A3 net (fanout=2) 0.520 mor1kx0/mor1kx_cpu/cappuccino.mor1kx_cpu/mor1kx_lsu_cappuccino/dmmu_gen.mor1kx_dmmu/tlb_huge
  452. SLICE_X77Y76.A Tilo 0.105 mor1kx0/mor1kx_cpu/cappuccino.mor1kx_cpu/mor1kx_ctrl_cappuccino/mfspr_dat_o<26>5
  453. mor1kx0/mor1kx_cpu/cappuccino.mor1kx_cpu/mor1kx_lsu_cappuccino/dmmu_gen.mor1kx_dmmu/Mmux_pagefault_o12
  454. SLICE_X68Y75.C2 net (fanout=2) 0.884 mor1kx0/mor1kx_cpu/cappuccino.mor1kx_cpu/mor1kx_lsu_cappuccino/dmmu_gen.mor1kx_dmmu/Mmux_pagefault_o11
  455. SLICE_X68Y75.C Tilo 0.105 mor1kx0/mor1kx_cpu/cappuccino.mor1kx_cpu/mor1kx_lsu_cappuccino/pagefault
  456. mor1kx0/mor1kx_cpu/cappuccino.mor1kx_cpu/mor1kx_lsu_cappuccino/dmmu_gen.mor1kx_dmmu/Mmux_pagefault_o13
  457. SLICE_X66Y75.D2 net (fanout=8) 0.724 mor1kx0/mor1kx_cpu/cappuccino.mor1kx_cpu/mor1kx_lsu_cappuccino/pagefault
  458. SLICE_X66Y75.CMUX Topdc 0.443 mor1kx0/mor1kx_cpu/cappuccino.mor1kx_cpu/mor1kx_lsu_cappuccino/atomic_gen.atomic_flag_set
  459. mor1kx0/mor1kx_cpu/cappuccino.mor1kx_cpu/mor1kx_lsu_cappuccino/dmmu_gen.mor1kx_dmmu/tlb_miss_o8_SW0_F
  460. mor1kx0/mor1kx_cpu/cappuccino.mor1kx_cpu/mor1kx_lsu_cappuccino/dmmu_gen.mor1kx_dmmu/tlb_miss_o8_SW0
  461. SLICE_X62Y71.B1 net (fanout=1) 0.853 N1402
  462. SLICE_X62Y71.B Tilo 0.105 mor1kx0/mor1kx_cpu/cappuccino.mor1kx_cpu/decode_branch_o
  463. mor1kx0/mor1kx_cpu/cappuccino.mor1kx_cpu/mor1kx_lsu_cappuccino/Mmux_lsu_ack11
  464. SLICE_X64Y68.A2 net (fanout=8) 0.859 mor1kx0/mor1kx_cpu/cappuccino.mor1kx_cpu/mor1kx_lsu_cappuccino/Mmux_lsu_ack1
  465. SLICE_X64Y68.A Tilo 0.105 N1400
  466. mor1kx0/mor1kx_cpu/cappuccino.mor1kx_cpu/mor1kx_lsu_cappuccino/lsu_valid_o1_SW5
  467. SLICE_X64Y65.A4 net (fanout=1) 0.586 N1400
  468. SLICE_X64Y65.A Tilo 0.105 mor1kx0/mor1kx_cpu/cappuccino.mor1kx_cpu/mor1kx_fetch_cappuccino/addr_valid
  469. mor1kx0/mor1kx_cpu/cappuccino.mor1kx_cpu/mor1kx_ctrl_cappuccino/padv_fetch_o1
  470. SLICE_X64Y65.B5 net (fanout=33) 0.275 mor1kx0/mor1kx_cpu/cappuccino.mor1kx_cpu/padv_fetch_o
  471. SLICE_X64Y65.B Tilo 0.105 mor1kx0/mor1kx_cpu/cappuccino.mor1kx_cpu/mor1kx_fetch_cappuccino/addr_valid
  472. mor1kx0/mor1kx_cpu/cappuccino.mor1kx_cpu/mor1kx_fetch_cappuccino/addr_valid3
  473. SLICE_X60Y59.C1 net (fanout=32) 1.092 mor1kx0/mor1kx_cpu/cappuccino.mor1kx_cpu/mor1kx_fetch_cappuccino/addr_valid
  474. SLICE_X60Y59.C Tilo 0.105 mor1kx0/mor1kx_cpu/cappuccino.mor1kx_cpu/mor1kx_fetch_cappuccino/pc_fetch<11>
  475. mor1kx0/mor1kx_cpu/cappuccino.mor1kx_cpu/mor1kx_fetch_cappuccino/Mmux_ic_addr46
  476. RAMB36_X3Y17.ADDRBWRADDRL12 net (fanout=10) 2.329 mor1kx0/mor1kx_cpu/cappuccino.mor1kx_cpu/mor1kx_fetch_cappuccino/ic_addr<10>
  477. RAMB36_X3Y17.CLKBWRCLKL Trcck_ADDRB 0.490 mor1kx0/mor1kx_cpu/cappuccino.mor1kx_cpu/mor1kx_fetch_cappuccino/icache_gen.mor1kx_icache/way_memories[1].way_data_ram/Mram_mem1
  478. mor1kx0/mor1kx_cpu/cappuccino.mor1kx_cpu/mor1kx_fetch_cappuccino/icache_gen.mor1kx_icache/way_memories[1].way_data_ram/Mram_mem1
  479. -------------------------------------------------------- ---------------------------
  480. Total 13.220ns (3.898ns logic, 9.322ns route)
  481. (29.5% logic, 70.5% route)
  482.  
  483. --------------------------------------------------------------------------------
  484. Slack (setup path): 6.665ns (requirement - (data path - clock path skew + uncertainty))
  485. Source: mor1kx0/mor1kx_cpu/cappuccino.mor1kx_cpu/mor1kx_lsu_cappuccino/dmmu_gen.mor1kx_dmmu/dtlb_match_regs/Mram_mem (RAM)
  486. Destination: mor1kx0/mor1kx_cpu/cappuccino.mor1kx_cpu/mor1kx_fetch_cappuccino/icache_gen.mor1kx_icache/way_memories[1].way_data_ram/Mram_mem1 (RAM)
  487. Requirement: 20.000ns
  488. Data Path Delay: 13.220ns (Levels of Logic = 9)
  489. Clock Path Skew: -0.033ns (0.757 - 0.790)
  490. Source Clock: wb_clk rising at 0.000ns
  491. Destination Clock: wb_clk rising at 20.000ns
  492. Clock Uncertainty: 0.082ns
  493.  
  494. Clock Uncertainty: 0.082ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE
  495. Total System Jitter (TSJ): 0.070ns
  496. Discrete Jitter (DJ): 0.147ns
  497. Phase Error (PE): 0.000ns
  498.  
  499. Maximum Data Path at Slow Process Corner: mor1kx0/mor1kx_cpu/cappuccino.mor1kx_cpu/mor1kx_lsu_cappuccino/dmmu_gen.mor1kx_dmmu/dtlb_match_regs/Mram_mem to mor1kx0/mor1kx_cpu/cappuccino.mor1kx_cpu/mor1kx_fetch_cappuccino/icache_gen.mor1kx_icache/way_memories[1].way_data_ram/Mram_mem1
  500. Location Delay type Delay(ns) Physical Resource
  501. Logical Resource(s)
  502. -------------------------------------------------------- -------------------
  503. RAMB36_X3Y14.DOBDO0 Trcko_DOB 2.125 mor1kx0/mor1kx_cpu/cappuccino.mor1kx_cpu/mor1kx_lsu_cappuccino/dmmu_gen.mor1kx_dmmu/dtlb_match_regs/Mram_mem
  504. mor1kx0/mor1kx_cpu/cappuccino.mor1kx_cpu/mor1kx_lsu_cappuccino/dmmu_gen.mor1kx_dmmu/dtlb_match_regs/Mram_mem
  505. SLICE_X76Y76.C1 net (fanout=46) 1.200 mor1kx0/mor1kx_cpu/cappuccino.mor1kx_cpu/mor1kx_lsu_cappuccino/dmmu_gen.mor1kx_dmmu/dtlb_match_huge_dout<0>
  506. SLICE_X76Y76.C Tilo 0.105 mor1kx0/mor1kx_cpu/cappuccino.mor1kx_cpu/mor1kx_lsu_cappuccino/dmmu_gen.mor1kx_dmmu/tlb_huge
  507. mor1kx0/mor1kx_cpu/cappuccino.mor1kx_cpu/mor1kx_lsu_cappuccino/dmmu_gen.mor1kx_dmmu/out1
  508. SLICE_X77Y76.A3 net (fanout=2) 0.520 mor1kx0/mor1kx_cpu/cappuccino.mor1kx_cpu/mor1kx_lsu_cappuccino/dmmu_gen.mor1kx_dmmu/tlb_huge
  509. SLICE_X77Y76.A Tilo 0.105 mor1kx0/mor1kx_cpu/cappuccino.mor1kx_cpu/mor1kx_ctrl_cappuccino/mfspr_dat_o<26>5
  510. mor1kx0/mor1kx_cpu/cappuccino.mor1kx_cpu/mor1kx_lsu_cappuccino/dmmu_gen.mor1kx_dmmu/Mmux_pagefault_o12
  511. SLICE_X68Y75.C2 net (fanout=2) 0.884 mor1kx0/mor1kx_cpu/cappuccino.mor1kx_cpu/mor1kx_lsu_cappuccino/dmmu_gen.mor1kx_dmmu/Mmux_pagefault_o11
  512. SLICE_X68Y75.C Tilo 0.105 mor1kx0/mor1kx_cpu/cappuccino.mor1kx_cpu/mor1kx_lsu_cappuccino/pagefault
  513. mor1kx0/mor1kx_cpu/cappuccino.mor1kx_cpu/mor1kx_lsu_cappuccino/dmmu_gen.mor1kx_dmmu/Mmux_pagefault_o13
  514. SLICE_X66Y75.D2 net (fanout=8) 0.724 mor1kx0/mor1kx_cpu/cappuccino.mor1kx_cpu/mor1kx_lsu_cappuccino/pagefault
  515. SLICE_X66Y75.CMUX Topdc 0.443 mor1kx0/mor1kx_cpu/cappuccino.mor1kx_cpu/mor1kx_lsu_cappuccino/atomic_gen.atomic_flag_set
  516. mor1kx0/mor1kx_cpu/cappuccino.mor1kx_cpu/mor1kx_lsu_cappuccino/dmmu_gen.mor1kx_dmmu/tlb_miss_o8_SW0_F
  517. mor1kx0/mor1kx_cpu/cappuccino.mor1kx_cpu/mor1kx_lsu_cappuccino/dmmu_gen.mor1kx_dmmu/tlb_miss_o8_SW0
  518. SLICE_X62Y71.B1 net (fanout=1) 0.853 N1402
  519. SLICE_X62Y71.B Tilo 0.105 mor1kx0/mor1kx_cpu/cappuccino.mor1kx_cpu/decode_branch_o
  520. mor1kx0/mor1kx_cpu/cappuccino.mor1kx_cpu/mor1kx_lsu_cappuccino/Mmux_lsu_ack11
  521. SLICE_X64Y68.A2 net (fanout=8) 0.859 mor1kx0/mor1kx_cpu/cappuccino.mor1kx_cpu/mor1kx_lsu_cappuccino/Mmux_lsu_ack1
  522. SLICE_X64Y68.A Tilo 0.105 N1400
  523. mor1kx0/mor1kx_cpu/cappuccino.mor1kx_cpu/mor1kx_lsu_cappuccino/lsu_valid_o1_SW5
  524. SLICE_X64Y65.A4 net (fanout=1) 0.586 N1400
  525. SLICE_X64Y65.A Tilo 0.105 mor1kx0/mor1kx_cpu/cappuccino.mor1kx_cpu/mor1kx_fetch_cappuccino/addr_valid
  526. mor1kx0/mor1kx_cpu/cappuccino.mor1kx_cpu/mor1kx_ctrl_cappuccino/padv_fetch_o1
  527. SLICE_X64Y65.B5 net (fanout=33) 0.275 mor1kx0/mor1kx_cpu/cappuccino.mor1kx_cpu/padv_fetch_o
  528. SLICE_X64Y65.B Tilo 0.105 mor1kx0/mor1kx_cpu/cappuccino.mor1kx_cpu/mor1kx_fetch_cappuccino/addr_valid
  529. mor1kx0/mor1kx_cpu/cappuccino.mor1kx_cpu/mor1kx_fetch_cappuccino/addr_valid3
  530. SLICE_X60Y59.C1 net (fanout=32) 1.092 mor1kx0/mor1kx_cpu/cappuccino.mor1kx_cpu/mor1kx_fetch_cappuccino/addr_valid
  531. SLICE_X60Y59.C Tilo 0.105 mor1kx0/mor1kx_cpu/cappuccino.mor1kx_cpu/mor1kx_fetch_cappuccino/pc_fetch<11>
  532. mor1kx0/mor1kx_cpu/cappuccino.mor1kx_cpu/mor1kx_fetch_cappuccino/Mmux_ic_addr46
  533. RAMB36_X3Y17.ADDRBWRADDRL12 net (fanout=10) 2.329 mor1kx0/mor1kx_cpu/cappuccino.mor1kx_cpu/mor1kx_fetch_cappuccino/ic_addr<10>
  534. RAMB36_X3Y17.CLKBWRCLKL Trcck_ADDRB 0.490 mor1kx0/mor1kx_cpu/cappuccino.mor1kx_cpu/mor1kx_fetch_cappuccino/icache_gen.mor1kx_icache/way_memories[1].way_data_ram/Mram_mem1
  535. mor1kx0/mor1kx_cpu/cappuccino.mor1kx_cpu/mor1kx_fetch_cappuccino/icache_gen.mor1kx_icache/way_memories[1].way_data_ram/Mram_mem1
  536. -------------------------------------------------------- ---------------------------
  537. Total 13.220ns (3.898ns logic, 9.322ns route)
  538. (29.5% logic, 70.5% route)
  539.  
  540. --------------------------------------------------------------------------------
  541. Slack (setup path): 6.671ns (requirement - (data path - clock path skew + uncertainty))
  542. Source: mor1kx0/mor1kx_cpu/cappuccino.mor1kx_cpu/mor1kx_lsu_cappuccino/dmmu_gen.mor1kx_dmmu/dtlb_match_regs/Mram_mem (RAM)
  543. Destination: mor1kx0/mor1kx_cpu/cappuccino.mor1kx_cpu/mor1kx_fetch_cappuccino/icache_gen.mor1kx_icache/way_memories[1].way_data_ram/Mram_mem1 (RAM)
  544. Requirement: 20.000ns
  545. Data Path Delay: 13.214ns (Levels of Logic = 9)
  546. Clock Path Skew: -0.033ns (0.757 - 0.790)
  547. Source Clock: wb_clk rising at 0.000ns
  548. Destination Clock: wb_clk rising at 20.000ns
  549. Clock Uncertainty: 0.082ns
  550.  
  551. Clock Uncertainty: 0.082ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE
  552. Total System Jitter (TSJ): 0.070ns
  553. Discrete Jitter (DJ): 0.147ns
  554. Phase Error (PE): 0.000ns
  555.  
  556. Maximum Data Path at Slow Process Corner: mor1kx0/mor1kx_cpu/cappuccino.mor1kx_cpu/mor1kx_lsu_cappuccino/dmmu_gen.mor1kx_dmmu/dtlb_match_regs/Mram_mem to mor1kx0/mor1kx_cpu/cappuccino.mor1kx_cpu/mor1kx_fetch_cappuccino/icache_gen.mor1kx_icache/way_memories[1].way_data_ram/Mram_mem1
  557. Location Delay type Delay(ns) Physical Resource
  558. Logical Resource(s)
  559. -------------------------------------------------------- -------------------
  560. RAMB36_X3Y14.DOBDO0 Trcko_DOB 2.125 mor1kx0/mor1kx_cpu/cappuccino.mor1kx_cpu/mor1kx_lsu_cappuccino/dmmu_gen.mor1kx_dmmu/dtlb_match_regs/Mram_mem
  561. mor1kx0/mor1kx_cpu/cappuccino.mor1kx_cpu/mor1kx_lsu_cappuccino/dmmu_gen.mor1kx_dmmu/dtlb_match_regs/Mram_mem
  562. SLICE_X76Y76.C1 net (fanout=46) 1.200 mor1kx0/mor1kx_cpu/cappuccino.mor1kx_cpu/mor1kx_lsu_cappuccino/dmmu_gen.mor1kx_dmmu/dtlb_match_huge_dout<0>
  563. SLICE_X76Y76.C Tilo 0.105 mor1kx0/mor1kx_cpu/cappuccino.mor1kx_cpu/mor1kx_lsu_cappuccino/dmmu_gen.mor1kx_dmmu/tlb_huge
  564. mor1kx0/mor1kx_cpu/cappuccino.mor1kx_cpu/mor1kx_lsu_cappuccino/dmmu_gen.mor1kx_dmmu/out1
  565. SLICE_X77Y76.A3 net (fanout=2) 0.520 mor1kx0/mor1kx_cpu/cappuccino.mor1kx_cpu/mor1kx_lsu_cappuccino/dmmu_gen.mor1kx_dmmu/tlb_huge
  566. SLICE_X77Y76.A Tilo 0.105 mor1kx0/mor1kx_cpu/cappuccino.mor1kx_cpu/mor1kx_ctrl_cappuccino/mfspr_dat_o<26>5
  567. mor1kx0/mor1kx_cpu/cappuccino.mor1kx_cpu/mor1kx_lsu_cappuccino/dmmu_gen.mor1kx_dmmu/Mmux_pagefault_o12
  568. SLICE_X68Y75.C2 net (fanout=2) 0.884 mor1kx0/mor1kx_cpu/cappuccino.mor1kx_cpu/mor1kx_lsu_cappuccino/dmmu_gen.mor1kx_dmmu/Mmux_pagefault_o11
  569. SLICE_X68Y75.C Tilo 0.105 mor1kx0/mor1kx_cpu/cappuccino.mor1kx_cpu/mor1kx_lsu_cappuccino/pagefault
  570. mor1kx0/mor1kx_cpu/cappuccino.mor1kx_cpu/mor1kx_lsu_cappuccino/dmmu_gen.mor1kx_dmmu/Mmux_pagefault_o13
  571. SLICE_X66Y75.C2 net (fanout=8) 0.713 mor1kx0/mor1kx_cpu/cappuccino.mor1kx_cpu/mor1kx_lsu_cappuccino/pagefault
  572. SLICE_X66Y75.CMUX Tilo 0.448 mor1kx0/mor1kx_cpu/cappuccino.mor1kx_cpu/mor1kx_lsu_cappuccino/atomic_gen.atomic_flag_set
  573. mor1kx0/mor1kx_cpu/cappuccino.mor1kx_cpu/mor1kx_lsu_cappuccino/dmmu_gen.mor1kx_dmmu/tlb_miss_o8_SW0_G
  574. mor1kx0/mor1kx_cpu/cappuccino.mor1kx_cpu/mor1kx_lsu_cappuccino/dmmu_gen.mor1kx_dmmu/tlb_miss_o8_SW0
  575. SLICE_X62Y71.B1 net (fanout=1) 0.853 N1402
  576. SLICE_X62Y71.B Tilo 0.105 mor1kx0/mor1kx_cpu/cappuccino.mor1kx_cpu/decode_branch_o
  577. mor1kx0/mor1kx_cpu/cappuccino.mor1kx_cpu/mor1kx_lsu_cappuccino/Mmux_lsu_ack11
  578. SLICE_X64Y68.A2 net (fanout=8) 0.859 mor1kx0/mor1kx_cpu/cappuccino.mor1kx_cpu/mor1kx_lsu_cappuccino/Mmux_lsu_ack1
  579. SLICE_X64Y68.A Tilo 0.105 N1400
  580. mor1kx0/mor1kx_cpu/cappuccino.mor1kx_cpu/mor1kx_lsu_cappuccino/lsu_valid_o1_SW5
  581. SLICE_X64Y65.A4 net (fanout=1) 0.586 N1400
  582. SLICE_X64Y65.A Tilo 0.105 mor1kx0/mor1kx_cpu/cappuccino.mor1kx_cpu/mor1kx_fetch_cappuccino/addr_valid
  583. mor1kx0/mor1kx_cpu/cappuccino.mor1kx_cpu/mor1kx_ctrl_cappuccino/padv_fetch_o1
  584. SLICE_X64Y65.B5 net (fanout=33) 0.275 mor1kx0/mor1kx_cpu/cappuccino.mor1kx_cpu/padv_fetch_o
  585. SLICE_X64Y65.B Tilo 0.105 mor1kx0/mor1kx_cpu/cappuccino.mor1kx_cpu/mor1kx_fetch_cappuccino/addr_valid
  586. mor1kx0/mor1kx_cpu/cappuccino.mor1kx_cpu/mor1kx_fetch_cappuccino/addr_valid3
  587. SLICE_X60Y59.C1 net (fanout=32) 1.092 mor1kx0/mor1kx_cpu/cappuccino.mor1kx_cpu/mor1kx_fetch_cappuccino/addr_valid
  588. SLICE_X60Y59.C Tilo 0.105 mor1kx0/mor1kx_cpu/cappuccino.mor1kx_cpu/mor1kx_fetch_cappuccino/pc_fetch<11>
  589. mor1kx0/mor1kx_cpu/cappuccino.mor1kx_cpu/mor1kx_fetch_cappuccino/Mmux_ic_addr46
  590. RAMB36_X3Y17.ADDRBWRADDRL12 net (fanout=10) 2.329 mor1kx0/mor1kx_cpu/cappuccino.mor1kx_cpu/mor1kx_fetch_cappuccino/ic_addr<10>
  591. RAMB36_X3Y17.CLKBWRCLKL Trcck_ADDRB 0.490 mor1kx0/mor1kx_cpu/cappuccino.mor1kx_cpu/mor1kx_fetch_cappuccino/icache_gen.mor1kx_icache/way_memories[1].way_data_ram/Mram_mem1
  592. mor1kx0/mor1kx_cpu/cappuccino.mor1kx_cpu/mor1kx_fetch_cappuccino/icache_gen.mor1kx_icache/way_memories[1].way_data_ram/Mram_mem1
  593. -------------------------------------------------------- ---------------------------
  594. Total 13.214ns (3.903ns logic, 9.311ns route)
  595. (29.5% logic, 70.5% route)
  596.  
  597. --------------------------------------------------------------------------------
  598.  
  599. Hold Paths: TS_clkgen0_clkout0 = PERIOD TIMEGRP "clkgen0_clkout0" TS_sys_clk_pin * 0.5
  600. HIGH 50%;
  601. --------------------------------------------------------------------------------
  602.  
  603. Paths for end point mor1kx0/mor1kx_cpu/cappuccino.mor1kx_cpu/mor1kx_decode_execute_cappuccino/execute_except_ipagefault_o (SLICE_X63Y49.AX), 1 path
  604. --------------------------------------------------------------------------------
  605. Slack (hold path): 0.030ns (requirement - (clock path skew + uncertainty - data path))
  606. Source: mor1kx0/mor1kx_cpu/cappuccino.mor1kx_cpu/mor1kx_fetch_cappuccino/decode_except_ipagefault_o (FF)
  607. Destination: mor1kx0/mor1kx_cpu/cappuccino.mor1kx_cpu/mor1kx_decode_execute_cappuccino/execute_except_ipagefault_o (FF)
  608. Requirement: 0.000ns
  609. Data Path Delay: 0.366ns (Levels of Logic = 0)
  610. Clock Path Skew: 0.336ns (0.853 - 0.517)
  611. Source Clock: wb_clk rising at 20.000ns
  612. Destination Clock: wb_clk rising at 20.000ns
  613. Clock Uncertainty: 0.000ns
  614.  
  615. Minimum Data Path at Fast Process Corner: mor1kx0/mor1kx_cpu/cappuccino.mor1kx_cpu/mor1kx_fetch_cappuccino/decode_except_ipagefault_o to mor1kx0/mor1kx_cpu/cappuccino.mor1kx_cpu/mor1kx_decode_execute_cappuccino/execute_except_ipagefault_o
  616. Location Delay type Delay(ns) Physical Resource
  617. Logical Resource(s)
  618. ------------------------------------------------- -------------------
  619. SLICE_X62Y50.BQ Tcko 0.164 mor1kx0/mor1kx_cpu/cappuccino.mor1kx_cpu/mor1kx_fetch_cappuccino/decode_except_ipagefault_o
  620. mor1kx0/mor1kx_cpu/cappuccino.mor1kx_cpu/mor1kx_fetch_cappuccino/decode_except_ipagefault_o
  621. SLICE_X63Y49.AX net (fanout=5) 0.272 mor1kx0/mor1kx_cpu/cappuccino.mor1kx_cpu/mor1kx_fetch_cappuccino/decode_except_ipagefault_o
  622. SLICE_X63Y49.CLK Tckdi (-Th) 0.070 mor1kx0/mor1kx_cpu/cappuccino.mor1kx_cpu/mor1kx_decode_execute_cappuccino/execute_except_ipagefault_o
  623. mor1kx0/mor1kx_cpu/cappuccino.mor1kx_cpu/mor1kx_decode_execute_cappuccino/execute_except_ipagefault_o
  624. ------------------------------------------------- ---------------------------
  625. Total 0.366ns (0.094ns logic, 0.272ns route)
  626. (25.7% logic, 74.3% route)
  627.  
  628. --------------------------------------------------------------------------------
  629.  
  630. Paths for end point mor1kx0/mor1kx_cpu/cappuccino.mor1kx_cpu/mor1kx_execute_ctrl_cappuccino/ctrl_except_itlb_miss_o (SLICE_X58Y49.A3), 1 path
  631. --------------------------------------------------------------------------------
  632. Slack (hold path): 0.031ns (requirement - (clock path skew + uncertainty - data path))
  633. Source: mor1kx0/mor1kx_cpu/cappuccino.mor1kx_cpu/mor1kx_decode_execute_cappuccino/execute_except_itlb_miss_o (FF)
  634. Destination: mor1kx0/mor1kx_cpu/cappuccino.mor1kx_cpu/mor1kx_execute_ctrl_cappuccino/ctrl_except_itlb_miss_o (FF)
  635. Requirement: 0.000ns
  636. Data Path Delay: 0.367ns (Levels of Logic = 1)
  637. Clock Path Skew: 0.336ns (0.851 - 0.515)
  638. Source Clock: wb_clk rising at 20.000ns
  639. Destination Clock: wb_clk rising at 20.000ns
  640. Clock Uncertainty: 0.000ns
  641.  
  642. Minimum Data Path at Fast Process Corner: mor1kx0/mor1kx_cpu/cappuccino.mor1kx_cpu/mor1kx_decode_execute_cappuccino/execute_except_itlb_miss_o to mor1kx0/mor1kx_cpu/cappuccino.mor1kx_cpu/mor1kx_execute_ctrl_cappuccino/ctrl_except_itlb_miss_o
  643. Location Delay type Delay(ns) Physical Resource
  644. Logical Resource(s)
  645. ------------------------------------------------- -------------------
  646. SLICE_X58Y50.AQ Tcko 0.164 mor1kx0/mor1kx_cpu/cappuccino.mor1kx_cpu/mor1kx_decode_execute_cappuccino/execute_except_itlb_miss_o
  647. mor1kx0/mor1kx_cpu/cappuccino.mor1kx_cpu/mor1kx_decode_execute_cappuccino/execute_except_itlb_miss_o
  648. SLICE_X58Y49.A3 net (fanout=1) 0.278 mor1kx0/mor1kx_cpu/cappuccino.mor1kx_cpu/mor1kx_decode_execute_cappuccino/execute_except_itlb_miss_o
  649. SLICE_X58Y49.CLK Tah (-Th) 0.075 mor1kx0/mor1kx_cpu/cappuccino.mor1kx_cpu/mor1kx_execute_ctrl_cappuccino/ctrl_except_itlb_miss_o
  650. mor1kx0/mor1kx_cpu/cappuccino.mor1kx_cpu/mor1kx_execute_ctrl_cappuccino/Mmux_ctrl_except_itlb_miss_o_GND_45_o_MUX_3461_o11
  651. mor1kx0/mor1kx_cpu/cappuccino.mor1kx_cpu/mor1kx_execute_ctrl_cappuccino/ctrl_except_itlb_miss_o
  652. ------------------------------------------------- ---------------------------
  653. Total 0.367ns (0.089ns logic, 0.278ns route)
  654. (24.3% logic, 75.7% route)
  655.  
  656. --------------------------------------------------------------------------------
  657.  
  658. Paths for end point mor1kx0/mor1kx_cpu/cappuccino.mor1kx_cpu/mor1kx_ctrl_cappuccino/last_branch_insn_pc_23 (SLICE_X50Y62.DX), 1 path
  659. --------------------------------------------------------------------------------
  660. Slack (hold path): 0.037ns (requirement - (clock path skew + uncertainty - data path))
  661. Source: mor1kx0/mor1kx_cpu/cappuccino.mor1kx_cpu/mor1kx_decode_execute_cappuccino/pc_execute_o_23 (FF)
  662. Destination: mor1kx0/mor1kx_cpu/cappuccino.mor1kx_cpu/mor1kx_ctrl_cappuccino/last_branch_insn_pc_23 (FF)
  663. Requirement: 0.000ns
  664. Data Path Delay: 0.302ns (Levels of Logic = 0)
  665. Clock Path Skew: 0.265ns (0.774 - 0.509)
  666. Source Clock: wb_clk rising at 20.000ns
  667. Destination Clock: wb_clk rising at 20.000ns
  668. Clock Uncertainty: 0.000ns
  669.  
  670. Minimum Data Path at Fast Process Corner: mor1kx0/mor1kx_cpu/cappuccino.mor1kx_cpu/mor1kx_decode_execute_cappuccino/pc_execute_o_23 to mor1kx0/mor1kx_cpu/cappuccino.mor1kx_cpu/mor1kx_ctrl_cappuccino/last_branch_insn_pc_23
  671. Location Delay type Delay(ns) Physical Resource
  672. Logical Resource(s)
  673. ------------------------------------------------- -------------------
  674. SLICE_X53Y62.DQ Tcko 0.141 mor1kx0/mor1kx_cpu/cappuccino.mor1kx_cpu/mor1kx_decode_execute_cappuccino/pc_execute_o<23>
  675. mor1kx0/mor1kx_cpu/cappuccino.mor1kx_cpu/mor1kx_decode_execute_cappuccino/pc_execute_o_23
  676. SLICE_X50Y62.DX net (fanout=3) 0.224 mor1kx0/mor1kx_cpu/cappuccino.mor1kx_cpu/mor1kx_decode_execute_cappuccino/pc_execute_o<23>
  677. SLICE_X50Y62.CLK Tckdi (-Th) 0.063 mor1kx0/mor1kx_cpu/cappuccino.mor1kx_cpu/mor1kx_ctrl_cappuccino/last_branch_insn_pc<23>
  678. mor1kx0/mor1kx_cpu/cappuccino.mor1kx_cpu/mor1kx_ctrl_cappuccino/last_branch_insn_pc_23
  679. ------------------------------------------------- ---------------------------
  680. Total 0.302ns (0.078ns logic, 0.224ns route)
  681. (25.8% logic, 74.2% route)
  682.  
  683. --------------------------------------------------------------------------------
  684.  
  685. Component Switching Limit Checks: TS_clkgen0_clkout0 = PERIOD TIMEGRP "clkgen0_clkout0" TS_sys_clk_pin * 0.5
  686. HIGH 50%;
  687. --------------------------------------------------------------------------------
  688. Slack: 17.528ns (period - min period limit)
  689. Period: 20.000ns
  690. Min period limit: 2.472ns (404.531MHz) (Trper_CLKA)
  691. Physical resource: mor1kx0/mor1kx_cpu/cappuccino.mor1kx_cpu/mor1kx_rf_cappuccino/rfa/Mram_mem/CLKARDCLK
  692. Logical resource: mor1kx0/mor1kx_cpu/cappuccino.mor1kx_cpu/mor1kx_rf_cappuccino/rfa/Mram_mem/CLKARDCLK
  693. Location pin: RAMB18_X3Y25.CLKARDCLK
  694. Clock network: wb_clk
  695. --------------------------------------------------------------------------------
  696. Slack: 17.528ns (period - min period limit)
  697. Period: 20.000ns
  698. Min period limit: 2.472ns (404.531MHz) (Trper_CLKB)
  699. Physical resource: mor1kx0/mor1kx_cpu/cappuccino.mor1kx_cpu/mor1kx_rf_cappuccino/rfa/Mram_mem/CLKBWRCLK
  700. Logical resource: mor1kx0/mor1kx_cpu/cappuccino.mor1kx_cpu/mor1kx_rf_cappuccino/rfa/Mram_mem/CLKBWRCLK
  701. Location pin: RAMB18_X3Y25.CLKBWRCLK
  702. Clock network: wb_clk
  703. --------------------------------------------------------------------------------
  704. Slack: 17.528ns (period - min period limit)
  705. Period: 20.000ns
  706. Min period limit: 2.472ns (404.531MHz) (Trper_CLKA)
  707. Physical resource: mor1kx0/mor1kx_cpu/cappuccino.mor1kx_cpu/mor1kx_fetch_cappuccino/icache_gen.mor1kx_icache/way_memories[1].way_data_ram/Mram_mem1/CLKARDCLKL
  708. Logical resource: mor1kx0/mor1kx_cpu/cappuccino.mor1kx_cpu/mor1kx_fetch_cappuccino/icache_gen.mor1kx_icache/way_memories[1].way_data_ram/Mram_mem1/CLKARDCLKL
  709. Location pin: RAMB36_X3Y17.CLKARDCLKL
  710. Clock network: wb_clk
  711. --------------------------------------------------------------------------------
  712.  
  713.  
  714. Derived Constraint Report
  715. Derived Constraints for TS_sys_clk_pin
  716. +-------------------------------+-------------+-------------+-------------+-------------+-------------+-------------+-------------+
  717. | | Period | Actual Period | Timing Errors | Paths Analyzed |
  718. | Constraint | Requirement |-------------+-------------|-------------+-------------|-------------+-------------|
  719. | | | Direct | Derivative | Direct | Derivative | Direct | Derivative |
  720. +-------------------------------+-------------+-------------+-------------+-------------+-------------+-------------+-------------+
  721. |TS_sys_clk_pin | 10.000ns| 4.000ns| 6.733ns| 0| 0| 0| 4202623|
  722. | TS_clkgen0_clkout0 | 20.000ns| 13.466ns| N/A| 0| 0| 4202623| 0|
  723. +-------------------------------+-------------+-------------+-------------+-------------+-------------+-------------+-------------+
  724.  
  725. All constraints were met.
  726.  
  727.  
  728. Data Sheet report:
  729. -----------------
  730. All values displayed in nanoseconds (ns)
  731.  
  732. Clock to Setup on destination clock sys_clk_pad_i
  733. ---------------+---------+---------+---------+---------+
  734. | Src:Rise| Src:Fall| Src:Rise| Src:Fall|
  735. Source Clock |Dest:Rise|Dest:Rise|Dest:Fall|Dest:Fall|
  736. ---------------+---------+---------+---------+---------+
  737. sys_clk_pad_i | 13.466| | | |
  738. ---------------+---------+---------+---------+---------+
  739.  
  740.  
  741. Timing summary:
  742. ---------------
  743.  
  744. Timing errors: 0 Score: 0 (Setup/Max: 0, Hold: 0)
  745.  
  746. Constraints cover 4202623 paths, 0 nets, and 28946 connections
  747.  
  748. Design statistics:
  749. Minimum period: 13.466ns{1} (Maximum frequency: 74.261MHz)
  750.  
  751.  
  752. ------------------------------------Footnotes-----------------------------------
  753. 1) The minimum period statistic assumes all single cycle delays.
  754.  
  755. Analysis completed Thu Nov 20 23:53:26 2014
  756. --------------------------------------------------------------------------------
  757.  
  758. Trace Settings:
  759. -------------------------
  760. Trace Settings
  761.  
  762. Peak Memory Usage: 865 MB
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