<6>ParseEDID
<6>DDC_Init
<6>EDID ready
<6>DDC_Read
<6>Sink : EDID bank 0:
<6> 0   1   2   3   4   5   6   7   8   9   A   B   C   D   E   F
<6> ===============================================================================================
<6> 00  ff  ff  ff  ff  ff  ff  00  1e  6d  7a  58  92  4a  01  00
<6> 06  16  01  03  80  33  1d  78  ea  5e  a5  a2  55  4d  a0  26
<6> 11  50  54  a7  6b  80  b3  00  81  80  81  40  71  4f  01  01
<6> 01  01  01  01  01  01  02  3a  80  18  71  38  2d  40  58  2c
<6> 45  00  fe  22  11  00  00  1e  00  00  00  fd  00  38  4b  1e
<6> 53  0f  00  0a  20  20  20  20  20  20  00  00  00  fc  00  49
<6> 50  53  32  32  35  0a  20  20  20  20  20  20  00  00  00  ff
<6> 00  32  30  36  52  41  44  43  32  47  36  32  36  0a  00  00
<6> ===============================================================================================
<4>disp_clk: Could not find a matching pll-freq for 108003000 pclk
<4>disp_clk: Could not find a matching pll-freq for 108003000 pclk
<4>disp_clk: Could not find a matching pll-freq for 108003000 pclk
<4>disp_clk: Could not find a matching pll-freq for 108003000 pclk
<4>disp_clk: Could not find a matching pll-freq for 108003000 pclk
<4>disp_clk: Could not find a matching pll-freq for 108003000 pclk
<4>disp_clk: Could not find a matching pll-freq for 108003000 pclk
<4>disp_clk: Could not find a matching pll-freq for 108003000 pclk
<6>EDID version: 1.3
<6>PCLK=148500000 X 1920 2008 2052 2200 Y 1080 1084 1089 1125 fr 60 PP
<6>Using above mode as preferred EDID mode