library ieee;
use ieee.std_logic_1164.all;

entity par_reg is
    generic(
            n: integer := 1
            );
   port(
         clk  : in  std_logic;
            en  : in std_logic;
         pin   : in  std_logic_vector(n downto 0);
         pout   : out std_logic_vector(n downto 0)
        );
end par_reg;

architecture arch of par_reg is
begin
   process (clk, en)
   begin
        if(en = '1') then
       if (Clk'event and Clk='1') then
           pout <= pin;
       end if;
        end if;
   end process;
end arch;