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  1. diff --git a/arch/arm/boot/dts/Makefile b/arch/arm/boot/dts/Makefile
  2. index b8c5cd3..3dd7c79 100644
  3. --- a/arch/arm/boot/dts/Makefile
  4. +++ b/arch/arm/boot/dts/Makefile
  5. @@ -460,7 +460,8 @@ dtb-$(CONFIG_ARCH_VT8500) += vt8500-bv07.dtb \
  6. wm8505-ref.dtb \
  7. wm8650-mid.dtb \
  8. wm8750-apc8750.dtb \
  9. - wm8850-w70v2.dtb
  10. + wm8850-w70v2.dtb \
  11. + wm8950-vab600.dtb
  12. dtb-$(CONFIG_ARCH_ZYNQ) += \
  13. zynq-parallella.dtb \
  14. zynq-zc702.dtb \
  15. diff --git a/arch/arm/boot/dts/wm8850.dtsi b/arch/arm/boot/dts/wm8850.dtsi
  16. index 8fbccfbe..4398ad2 100644
  17. --- a/arch/arm/boot/dts/wm8850.dtsi
  18. +++ b/arch/arm/boot/dts/wm8850.dtsi
  19. @@ -27,6 +27,10 @@
  20. serial1 = &uart1;
  21. serial2 = &uart2;
  22. serial3 = &uart3;
  23. + i2c0 = &i2c_0;
  24. + i2c1 = &i2c_1;
  25. + i2c2 = &i2c_2;
  26. + i2c3 = &i2c_3;
  27. };
  28.  
  29. soc {
  30. @@ -53,7 +57,7 @@
  31. };
  32.  
  33. pinctrl: pinctrl@d8110000 {
  34. - compatible = "wm,wm8850-pinctrl";
  35. + compatible = "wm,wm8850-pinctrl","wm,prizm-pinctrl";
  36. reg = <0xd8110000 0x10000>;
  37. interrupt-controller;
  38. #interrupt-cells = <2>;
  39. @@ -69,12 +73,6 @@
  40. #address-cells = <1>;
  41. #size-cells = <0>;
  42.  
  43. - ref25: ref25M {
  44. - #clock-cells = <0>;
  45. - compatible = "fixed-clock";
  46. - clock-frequency = <25000000>;
  47. - };
  48. -
  49. ref24: ref24M {
  50. #clock-cells = <0>;
  51. compatible = "fixed-clock";
  52. @@ -208,6 +206,51 @@
  53. enable-reg = <0x250>;
  54. enable-bit = <0>;
  55. };
  56. +
  57. + clksf: sf {
  58. + #clock-cells = <0>;
  59. + compatible = "via,vt8500-device-clock";
  60. + clocks = <&pllb>;
  61. + divisor-reg = <0x314>;
  62. + enable-reg = <0x254>;
  63. + enable-bit = <23>;
  64. + };
  65. +
  66. + clki2c0: i2c0clk {
  67. + #clock-cells = <0>;
  68. + compatible = "via,vt8500-device-clock";
  69. + clocks = <&pllb>;
  70. + divisor-reg = <0x3A0>;
  71. + enable-reg = <0x250>;
  72. + enable-bit = <8>;
  73. + };
  74. +
  75. + clki2c1: i2c1clk {
  76. + #clock-cells = <0>;
  77. + compatible = "via,vt8500-device-clock";
  78. + clocks = <&pllb>;
  79. + divisor-reg = <0x3A4>;
  80. + enable-reg = <0x250>;
  81. + enable-bit = <9>;
  82. + };
  83. +
  84. + clki2c2: i2c2clk {
  85. + #clock-cells = <0>;
  86. + compatible = "via,vt8500-device-clock";
  87. + clocks = <&pllb>;
  88. + divisor-reg = <0x3A8>;
  89. + enable-reg = <0x250>;
  90. + enable-bit = <10>;
  91. + };
  92. +
  93. + clki2c3: i2c3clk {
  94. + #clock-cells = <0>;
  95. + compatible = "via,vt8500-device-clock";
  96. + clocks = <&pllb>;
  97. + divisor-reg = <0x3AC>;
  98. + enable-reg = <0x250>;
  99. + enable-bit = <11>;
  100. + };
  101. };
  102. };
  103.  
  104. @@ -221,6 +264,12 @@
  105. reg = <0xd8050400 0x100>;
  106. };
  107.  
  108. + sf@d8002000 {
  109. + compatible = "wm,wm8505-sf";
  110. + reg = <0xd8002000 0x400>;
  111. + clocks = <&clksf>;
  112. + };
  113. +
  114. pwm: pwm@d8220000 {
  115. #pwm-cells = <3>;
  116. compatible = "via,vt8500-pwm";
  117. @@ -299,10 +348,36 @@
  118. sdon-inverted;
  119. };
  120.  
  121. - ethernet@d8004000 {
  122. - compatible = "via,vt8500-rhine";
  123. - reg = <0xd8004000 0x100>;
  124. - interrupts = <10>;
  125. - };
  126. + i2c_0: i2c@d8280000 {
  127. + compatible = "wm,wm8505-i2c";
  128. + reg = <0xd8280000 0x1000>;
  129. + interrupts = <19>;
  130. + clocks = <&clki2c0>;
  131. + clock-frequency = <400000>;
  132. + };
  133. +
  134. + i2c_1: i2c@d8320000 {
  135. + compatible = "wm,wm8505-i2c";
  136. + reg = <0xd8320000 0x1000>;
  137. + interrupts = <18>;
  138. + clocks = <&clki2c1>;
  139. + clock-frequency = <400000>;
  140. + };
  141. +
  142. + i2c_2: i2c@d83a0000 {
  143. + compatible = "wm,wm8505-i2c";
  144. + reg = <0xd83A0000 0x1000>;
  145. + interrupts = <7>;
  146. + clocks = <&clki2c2>;
  147. + clock-frequency = <400000>;
  148. + };
  149. +
  150. + i2c_3: i2c@d83b0000 {
  151. + compatible = "wm,wm8505-i2c";
  152. + reg = <0xd83B0000 0x1000>;
  153. + interrupts = <15>;
  154. + clocks = <&clki2c3>;
  155. + clock-frequency = <400000>;
  156. + };
  157. };
  158. };
  159. diff --git a/arch/arm/boot/dts/wm8950-vab600.dts b/arch/arm/boot/dts/wm8950-vab600.dts
  160. new file mode 100644
  161. index 0000000..d7fc614
  162. --- /dev/null
  163. +++ b/arch/arm/boot/dts/wm8950-vab600.dts
  164. @@ -0,0 +1,29 @@
  165. +/*
  166. + * wm8950-vab600.dts
  167. + * - Device tree file for VIA VAB-600 Springboard
  168. + *
  169. + * Copyright (C) 2012 Tony Prisk <linux@prisktech.co.nz>
  170. + *
  171. + * Licensed under GPLv2 or later
  172. + */
  173. +
  174. +/dts-v1/;
  175. +/include/ "wm8950.dtsi"
  176. +
  177. +/ {
  178. + model = "VIA VAB-600 Springboard";
  179. + compatible = "via,vab600", "wm,wm8950";
  180. +
  181. + framebuffer {
  182. + compatible = "simple-framebuffer";
  183. + reg = <0x35200000 (1280 * 1024 * 2)>; /* Register is at top of memtotal, here 850Mb (850 << 20) */
  184. + width = <1280>;
  185. + height = <1024>;
  186. + stride = <(1280 * 2)>;
  187. + format = "r5g6b5";
  188. + };
  189. +};
  190. +
  191. +&uart0 {
  192. + status = "okay";
  193. +};
  194. diff --git a/arch/arm/boot/dts/wm8950.dtsi b/arch/arm/boot/dts/wm8950.dtsi
  195. new file mode 100644
  196. index 0000000..c3f53c0
  197. --- /dev/null
  198. +++ b/arch/arm/boot/dts/wm8950.dtsi
  199. @@ -0,0 +1,389 @@
  200. +/*
  201. + * wm8950.dtsi - Device tree file for Wondermedia WM8950 SoC
  202. + *
  203. + * Copyright (C) 2012 Tony Prisk <linux@prisktech.co.nz>
  204. + *
  205. + * Licensed under GPLv2 or later
  206. + */
  207. +
  208. +/include/ "skeleton.dtsi"
  209. +
  210. +/ {
  211. + compatible = "wm,wm8950";
  212. +
  213. + cpus {
  214. + #address-cells = <1>;
  215. + #size-cells = <0>;
  216. +
  217. + cpu@0 {
  218. + device_type = "cpu";
  219. + compatible = "arm,cortex-a9";
  220. + reg = <0x0>;
  221. + };
  222. + };
  223. +
  224. + aliases {
  225. + serial0 = &uart0;
  226. + serial1 = &uart1;
  227. + serial2 = &uart2;
  228. + serial3 = &uart3;
  229. + i2c0 = &i2c_0;
  230. + i2c1 = &i2c_1;
  231. + i2c2 = &i2c_2;
  232. + i2c3 = &i2c_3;
  233. + };
  234. +
  235. + soc {
  236. + #address-cells = <1>;
  237. + #size-cells = <1>;
  238. + compatible = "simple-bus";
  239. + ranges;
  240. + interrupt-parent = <&intc0>;
  241. +
  242. + intc0: interrupt-controller@d8140000 {
  243. + compatible = "via,vt8500-intc";
  244. + interrupt-controller;
  245. + reg = <0xd8140000 0x10000>;
  246. + #interrupt-cells = <1>;
  247. + };
  248. +
  249. + /* Secondary IC cascaded to intc0 */
  250. + intc1: interrupt-controller@d8150000 {
  251. + compatible = "via,vt8500-intc";
  252. + interrupt-controller;
  253. + #interrupt-cells = <1>;
  254. + reg = <0xD8150000 0x10000>;
  255. + interrupts = <56 57 58 59 60 61 62 63>;
  256. + };
  257. +
  258. + pinctrl: pinctrl@d8110000 {
  259. + compatible = "wm,wm8850-pinctrl","wm,prizm-pinctrl";
  260. + reg = <0xd8110000 0x10000>;
  261. + interrupt-controller;
  262. + #interrupt-cells = <2>;
  263. + gpio-controller;
  264. + #gpio-cells = <2>;
  265. + };
  266. +
  267. + pmc@d8130000 {
  268. + compatible = "via,vt8500-pmc";
  269. + reg = <0xd8130000 0x1000>;
  270. +
  271. + clocks {
  272. + #address-cells = <1>;
  273. + #size-cells = <0>;
  274. +
  275. + ref24: ref24M {
  276. + #clock-cells = <0>;
  277. + compatible = "fixed-clock";
  278. + clock-frequency = <24000000>;
  279. + };
  280. +
  281. + plla: plla {
  282. + #clock-cells = <0>;
  283. + compatible = "wm,wm8850-pll-clock";
  284. + clocks = <&ref24>;
  285. + reg = <0x200>;
  286. + };
  287. +
  288. + pllb: pllb {
  289. + #clock-cells = <0>;
  290. + compatible = "wm,wm8850-pll-clock";
  291. + clocks = <&ref24>;
  292. + reg = <0x204>;
  293. + };
  294. +
  295. + pllc: pllc {
  296. + #clock-cells = <0>;
  297. + compatible = "wm,wm8850-pll-clock";
  298. + clocks = <&ref24>;
  299. + reg = <0x208>;
  300. + };
  301. +
  302. + plld: plld {
  303. + #clock-cells = <0>;
  304. + compatible = "wm,wm8850-pll-clock";
  305. + clocks = <&ref24>;
  306. + reg = <0x20c>;
  307. + };
  308. +
  309. + plle: plle {
  310. + #clock-cells = <0>;
  311. + compatible = "wm,wm8850-pll-clock";
  312. + clocks = <&ref24>;
  313. + reg = <0x210>;
  314. + };
  315. +
  316. + pllf: pllf {
  317. + #clock-cells = <0>;
  318. + compatible = "wm,wm8850-pll-clock";
  319. + clocks = <&ref24>;
  320. + reg = <0x214>;
  321. + };
  322. +
  323. + pllg: pllg {
  324. + #clock-cells = <0>;
  325. + compatible = "wm,wm8850-pll-clock";
  326. + clocks = <&ref24>;
  327. + reg = <0x218>;
  328. + };
  329. +
  330. + clkarm: arm {
  331. + #clock-cells = <0>;
  332. + compatible = "via,vt8500-device-clock";
  333. + clocks = <&plla>;
  334. + divisor-reg = <0x300>;
  335. + };
  336. +
  337. + clkahb: ahb {
  338. + #clock-cells = <0>;
  339. + compatible = "via,vt8500-device-clock";
  340. + clocks = <&pllb>;
  341. + divisor-reg = <0x304>;
  342. + };
  343. +
  344. + clkapb: apb {
  345. + #clock-cells = <0>;
  346. + compatible = "via,vt8500-device-clock";
  347. + clocks = <&pllb>;
  348. + divisor-reg = <0x320>;
  349. + };
  350. +
  351. + clkddr: ddr {
  352. + #clock-cells = <0>;
  353. + compatible = "via,vt8500-device-clock";
  354. + clocks = <&plld>;
  355. + divisor-reg = <0x310>;
  356. + };
  357. +
  358. + clkuart0: uart0 {
  359. + #clock-cells = <0>;
  360. + compatible = "via,vt8500-device-clock";
  361. + clocks = <&ref24>;
  362. + enable-reg = <0x254>;
  363. + enable-bit = <24>;
  364. + };
  365. +
  366. + clkuart1: uart1 {
  367. + #clock-cells = <0>;
  368. + compatible = "via,vt8500-device-clock";
  369. + clocks = <&ref24>;
  370. + enable-reg = <0x254>;
  371. + enable-bit = <25>;
  372. + };
  373. +
  374. + clkuart2: uart2 {
  375. + #clock-cells = <0>;
  376. + compatible = "via,vt8500-device-clock";
  377. + clocks = <&ref24>;
  378. + enable-reg = <0x254>;
  379. + enable-bit = <26>;
  380. + };
  381. +
  382. + clkuart3: uart3 {
  383. + #clock-cells = <0>;
  384. + compatible = "via,vt8500-device-clock";
  385. + clocks = <&ref24>;
  386. + enable-reg = <0x254>;
  387. + enable-bit = <27>;
  388. + };
  389. +
  390. + clkpwm: pwm {
  391. + #clock-cells = <0>;
  392. + compatible = "via,vt8500-device-clock";
  393. + clocks = <&pllb>;
  394. + divisor-reg = <0x350>;
  395. + enable-reg = <0x250>;
  396. + enable-bit = <17>;
  397. + };
  398. +
  399. + clksdhc: sdhc {
  400. + #clock-cells = <0>;
  401. + compatible = "via,vt8500-device-clock";
  402. + clocks = <&pllb>;
  403. + divisor-reg = <0x330>;
  404. + divisor-mask = <0x3f>;
  405. + enable-reg = <0x250>;
  406. + enable-bit = <0>;
  407. + };
  408. +
  409. + clksf: sf {
  410. + #clock-cells = <0>;
  411. + compatible = "via,vt8500-device-clock";
  412. + clocks = <&pllb>;
  413. + divisor-reg = <0x314>;
  414. + enable-reg = <0x254>;
  415. + enable-bit = <23>;
  416. + };
  417. +
  418. + clki2c0: i2c0clk {
  419. + #clock-cells = <0>;
  420. + compatible = "via,vt8500-device-clock";
  421. + clocks = <&pllb>;
  422. + divisor-reg = <0x3A0>;
  423. + enable-reg = <0x250>;
  424. + enable-bit = <8>;
  425. + };
  426. +
  427. + clki2c1: i2c1clk {
  428. + #clock-cells = <0>;
  429. + compatible = "via,vt8500-device-clock";
  430. + clocks = <&pllb>;
  431. + divisor-reg = <0x3A4>;
  432. + enable-reg = <0x250>;
  433. + enable-bit = <9>;
  434. + };
  435. +
  436. + clki2c2: i2c2clk {
  437. + #clock-cells = <0>;
  438. + compatible = "via,vt8500-device-clock";
  439. + clocks = <&pllb>;
  440. + divisor-reg = <0x3A8>;
  441. + enable-reg = <0x250>;
  442. + enable-bit = <10>;
  443. + };
  444. +
  445. + clki2c3: i2c3clk {
  446. + #clock-cells = <0>;
  447. + compatible = "via,vt8500-device-clock";
  448. + clocks = <&pllb>;
  449. + divisor-reg = <0x3AC>;
  450. + enable-reg = <0x250>;
  451. + enable-bit = <11>;
  452. + };
  453. + };
  454. + };
  455. +
  456. + fb: fb@d8051700 {
  457. + compatible = "wm,wm8505-fb";
  458. + reg = <0xd8051700 0x200>;
  459. + };
  460. +
  461. + ge_rops@d8050400 {
  462. + compatible = "wm,prizm-ge-rops";
  463. + reg = <0xd8050400 0x100>;
  464. + };
  465. +
  466. + sf@d8002000 {
  467. + compatible = "wm,wm8505-sf";
  468. + reg = <0xd8002000 0x400>;
  469. + clocks = <&clksf>;
  470. + };
  471. +
  472. + pwm: pwm@d8220000 {
  473. + #pwm-cells = <3>;
  474. + compatible = "via,vt8500-pwm";
  475. + reg = <0xd8220000 0x100>;
  476. + clocks = <&clkpwm>;
  477. + };
  478. +
  479. + timer@d8130100 {
  480. + compatible = "via,vt8500-timer";
  481. + reg = <0xd8130100 0x28>;
  482. + interrupts = <36>;
  483. + };
  484. +
  485. + ehci@d8007900 {
  486. + compatible = "via,vt8500-ehci";
  487. + reg = <0xd8007900 0x200>;
  488. + interrupts = <26>;
  489. + };
  490. +
  491. + uhci@d8007b00 {
  492. + compatible = "platform-uhci";
  493. + reg = <0xd8007b00 0x200>;
  494. + interrupts = <26>;
  495. + };
  496. +
  497. + uhci@d8008d00 {
  498. + compatible = "platform-uhci";
  499. + reg = <0xd8008d00 0x200>;
  500. + interrupts = <26>;
  501. + };
  502. +
  503. + uart0: serial@d8200000 {
  504. + compatible = "via,vt8500-uart";
  505. + reg = <0xd8200000 0x1040>;
  506. + interrupts = <32>;
  507. + clocks = <&clkuart0>;
  508. + status = "disabled";
  509. + };
  510. +
  511. + uart1: serial@d82b0000 {
  512. + compatible = "via,vt8500-uart";
  513. + reg = <0xd82b0000 0x1040>;
  514. + interrupts = <33>;
  515. + clocks = <&clkuart1>;
  516. + status = "disabled";
  517. + };
  518. +
  519. + uart2: serial@d8210000 {
  520. + compatible = "via,vt8500-uart";
  521. + reg = <0xd8210000 0x1040>;
  522. + interrupts = <47>;
  523. + clocks = <&clkuart2>;
  524. + status = "disabled";
  525. + };
  526. +
  527. + uart3: serial@d82c0000 {
  528. + compatible = "via,vt8500-uart";
  529. + reg = <0xd82c0000 0x1040>;
  530. + interrupts = <50>;
  531. + clocks = <&clkuart3>;
  532. + status = "disabled";
  533. + };
  534. +
  535. + rtc@d8100000 {
  536. + compatible = "via,vt8500-rtc";
  537. + reg = <0xd8100000 0x10000>;
  538. + interrupts = <48>;
  539. + };
  540. +
  541. + sdhc@d800a000 {
  542. + compatible = "wm,wm8505-sdhc";
  543. + reg = <0xd800a000 0x1000>;
  544. + interrupts = <20 21>;
  545. + clocks = <&clksdhc>;
  546. + bus-width = <4>;
  547. + sdon-inverted;
  548. + };
  549. +
  550. + ethernet@d8004000 {
  551. + compatible = "via,vt8500-rhine";
  552. + reg = <0xd8004000 0x100>;
  553. + interrupts = <10>;
  554. + };
  555. +
  556. + i2c_0: i2c@d8280000 {
  557. + compatible = "wm,wm8505-i2c";
  558. + reg = <0xd8280000 0x1000>;
  559. + interrupts = <19>;
  560. + clocks = <&clki2c0>;
  561. + clock-frequency = <400000>;
  562. + };
  563. +
  564. + i2c_1: i2c@d8320000 {
  565. + compatible = "wm,wm8505-i2c";
  566. + reg = <0xd8320000 0x1000>;
  567. + interrupts = <18>;
  568. + clocks = <&clki2c1>;
  569. + clock-frequency = <400000>;
  570. + };
  571. +
  572. + i2c_2: i2c@d83a0000 {
  573. + compatible = "wm,wm8505-i2c";
  574. + reg = <0xd83A0000 0x1000>;
  575. + interrupts = <7>;
  576. + clocks = <&clki2c2>;
  577. + clock-frequency = <400000>;
  578. + };
  579. +
  580. + i2c_3: i2c@d83b0000 {
  581. + compatible = "wm,wm8505-i2c";
  582. + reg = <0xd83B0000 0x1000>;
  583. + interrupts = <15>;
  584. + clocks = <&clki2c3>;
  585. + clock-frequency = <400000>;
  586. + };
  587. + };
  588. +};
  589. diff --git a/arch/arm/mach-vt8500/Kconfig b/arch/arm/mach-vt8500/Kconfig
  590. index aaaa24f..0a555e0 100644
  591. --- a/arch/arm/mach-vt8500/Kconfig
  592. +++ b/arch/arm/mach-vt8500/Kconfig
  593. @@ -27,3 +27,10 @@ config ARCH_WM8850
  594. select ARCH_VT8500
  595. help
  596. Support for WonderMedia WM8850 System-on-Chip.
  597. +
  598. +config ARCH_WM8950
  599. + bool "WonderMedia WM8950"
  600. + depends on ARCH_MULTI_V7
  601. + select ARCH_VT8500
  602. + help
  603. + Support for WonderMedia WM8950 System-on-Chip.
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