//////////////////////////////////////////////////////////////////////////////////
// TOP MODULE
//////////////////////////////////////////////////////////////////////////////////
module finalproject( sysclk, switches, buttons, red, grn, blue, hsync, vsync );
//port declaration
input sysclk;
input [7:0] switches;
input [3:0] buttons;
output [2:0] red;
output [2:0] grn;
output [1:0] blue;
output hsync;
output vsync;
//internal registers
integer cursorx = 6'b0;
integer cursory = 5'b0;
wire kb_int = 1'b0;
wire [6:0] kb_data;
wire [10:0] tiles_addr;
wire [6:0] tiles_dout;

//initialize vgacontroller and pass ports
vgacontroller vga1(
.sysclk (sysclk),
.red (red),
.grn (grn),
.blue (blue),
.vsync (vsync),
.hsync (hsync),
.tiles_addr(tiles_addr),
.tiles_dout(tiles_dout)
);

TileManager tm1 (
.sysclk(sysclk),
.tiles_addr(tiles_addr),
.tiles_dout(tiles_dout)
);

endmodule


`timescale 1ns / 1ps
//////////////////////////////////////////////////////////////////////////////////
// PixelPipeline - instantiated on same level as TileManager
//////////////////////////////////////////////////////////////////////////////////
module PixelPipeline(sysclk,clk,pix_x,pix_y,pixel_lit, tiles_addr, tiles_dout);
//port declarations
input sysclk;
input clk;
input pix_x;
input pix_y;
output tiles_addr;
input tiles_dout;
output pixel_lit;
//internal registers
wire [9:0] pix_x;
wire [9:0] pix_y;
reg pixel_lit;
wire [4:0] row;
wire [5:0] col;
wire [3:0] row_counter;
wire [3:0] col_counter;
reg [10:0] fm_addr;
wire [15:0] fm_dout;
reg [10:0] tiles_addr;
wire [6:0] tiles_dout;

assign row =  pix_y >> 4;
assign col =  pix_x >> 4;
assign row_counter = pix_y;
assign col_counter = pix_x;

font_map font (
  .clka(sysclk), // input clka
  .addra(fm_addr), // input [10 : 0] addra
  .douta(fm_dout) // output [15 : 0] douta
);

initial begin
    tiles_addr = 0;
    fm_addr = 0;
    pixel_lit = 0;
end

always @ (posedge sysclk)
begin
    // needs to notice when col_counter is getting close to rolling over, and prepare new col's data
    if(col_counter == 14)begin
        tiles_addr = row;
        tiles_addr = tiles_addr << 6 | col+1;
    end
end

always @ (posedge sysclk)
begin
    fm_addr = tiles_dout - 32;
    fm_addr = fm_addr << 4 | row_counter;
end

always @ (posedge sysclk)
begin
    pixel_lit = fm_dout[col_counter];
end

endmodule



//////////////////////////////////////////////////////////////////////////////////
// TileManager - RAM WRAPPER
//////////////////////////////////////////////////////////////////////////////////
module TileManager( sysclk, tiles_addr, tiles_dout );
//port declaration
input sysclk;
input tiles_addr;
output tiles_dout;
//internal registers

tile_map tilesRAM (
  .clka(sysclk), // input clka
  .wea(wea), // input [0 : 0] wea
  .addra(addra), // input [10 : 0] addra
  .dina(dina), // input [6 : 0] dina
  .clkb(sysclk), // input clkb
  .addrb(tiles_addr), // input [10 : 0] addrb
  .doutb(tiles_dout) // output [6 : 0] doutb
);

endmodule