LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
USE ieee.numeric_std.ALL;
LIBRARY UNISIM;
USE UNISIM.Vcomponents.ALL;
ENTITY pamiec22_pamiec22_sch_tb IS
END pamiec22_pamiec22_sch_tb;
ARCHITECTURE behavioral OF pamiec22_pamiec22_sch_tb IS

   COMPONENT pamiec22
   PORT( D0 :   IN  STD_LOGIC;
          D1    :   IN  STD_LOGIC;
          A :   IN  STD_LOGIC;
          Q0    :   OUT STD_LOGIC;
          Q1    :   OUT STD_LOGIC;
          Z :   IN  STD_LOGIC);
   END COMPONENT;

   SIGNAL D0    :   STD_LOGIC;
   SIGNAL D1    :   STD_LOGIC;
   SIGNAL A :   STD_LOGIC;
   SIGNAL Q0    :   STD_LOGIC;
   SIGNAL Q1    :   STD_LOGIC;
   SIGNAL Z :   STD_LOGIC;

BEGIN

   UUT: pamiec22 PORT MAP(
        D0 => D0,
        D1 => D1,
        A => A,
        Q0 => Q0,
        Q1 => Q1,
        Z => Z
   );

   D0 <= '0', '0' after 1ns, '0' after 3ns, '1' after 4ns;
    D1 <= '0', '1' after 1ns, '0' after 3ns, '0' after 4ns;
    A <= '0',  '0' after 1ns, '0' after 3ns, '1' after 4ns, '0' after 7ns, '1' after 8ns, '0' after 9ns, '1' after 10ns;
    Z <= '0',  '1' after 2ns, '0' after 3ns, '1' after 5ns, '0' after 6ns;
END;