ripplecarry

library IEEE;
use IEEE.STD_LOGIC_1164.ALL;

entity ripplecarry is
    Port ( a : in  STD_LOGIC_VECTOR (3 downto 0);
           b : in  STD_LOGIC_VECTOR (3 downto 0);
              cin: in STD_LOGIC;
           c : out  STD_LOGIC_VECTOR (3 downto 0);
           cout : out  STD_LOGIC);
end ripplecarry;

architecture Behavioral of ripplecarry is

signal SA, SB, SC: STD_LOGIC;

component fulladder port (
    a : in  STD_LOGIC;
    b : in  STD_LOGIC;
    cin : in  STD_LOGIC;
    cout : out  STD_LOGIC;
    s : out  STD_LOGIC);
end component;

begin

FAD1: fulladder port map (
    a => a(0),
    b => b(0),
    cin => cin,
    cout => SA,
    s => c(0)
);

FAD2: fulladder port map (
    a => a(1),
    b => b(1),
    cin => SA,
    cout => SB,
    s => c(1)
);

FAD3: fulladder port map (
    a => a(2),
    b => b(2),
    cin => SB,
    cout => SC,
    s => c(2)
);

FAD4: fulladder port map (
    a => a(3),
    b => b(3),
    cin => SC,
    cout => cout,
    s => c(3)
);

end Behavioral;