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-- Company:
-- Engineer:
--
-- Create Date: 12.10.2015 08:25:11
-- Design Name:
-- Module Name: main - Behavioral
-- Project Name:
-- Target Devices:
-- Tool Versions:
-- Description:
--
-- Dependencies:
--
-- Revision:
-- Revision 0.01 - File Created
-- Additional Comments:
--
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library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use work.mycomponents_package.ALL;

-- Uncomment the following library declaration if using
-- arithmetic functions with Signed or Unsigned values
--use IEEE.NUMERIC_STD.ALL;

-- Uncomment the following library declaration if instantiating
-- any Xilinx leaf cells in this code.
--library UNISIM;
--use UNISIM.VComponents.all;

entity main is
    PORT (
        X: in STD_LOGIC_VECTOR (7 downto 0);
        O: in STD_LOGIC_VECTOR (2 downto 0);
        I: in STD_LOGIC_VECTOR (1 downto 0);
        L: out STD_LOGIC_VECTOR (7 downto 0);
        --p0,p1,p2,p3: out STD_LOGIC_VECTOR (7 downto 0);
        --pin:out STD_LOGIC_VECTOR (3 downto 0);
        --pout: out STD_LOGIC_VECTOR (4 downto 0);
        En: in STD_LOGIC
        );
end main;

architecture Behavioral of main is

    SIGNAL dbu          : STD_LOGIC_VECTOR (7 downto 0);
    SIGNAL Rout         : STD_LOGIC_VECTOR (4 downto 0);
    SIGNAL Rin          : STD_LOGIC_VECTOR (3 downto 0);
    SIGNAL R0,R1,R2,R3  : STD_LOGIC_VECTOR (7 downto 0);
begin

    WITH O SELECT
        Rout <= "00001" WHEN "000",
                "00010" WHEN "001",
                "00100" WHEN "010",
                "01000" WHEN "011",
                "10000" WHEN "100",
                "00000" WHEN OTHERS;

    PROCESS
    BEGIN
        WAIT UNTIL En'EVENT AND En = '0' ;
        CASE I IS
            WHEN "00" =>
                Rin <= "0001";
            WHEN "01" =>
                Rin <= "0010";
            WHEN "10" =>
                Rin <= "0100";
            WHEN "11" =>
                Rin <= "1000";
            WHEN others =>
                Rin <= "0000";
        END CASE;
    END PROCESS;

    tri_ext: tris PORT MAP (X,Rout(4),dbu);
    reg0: REG PORT MAP(dbu,'1',Rin(0),R0);
    reg1: REG PORT MAP(dbu,'1',Rin(1),R1);
    reg2: REG PORT MAP(dbu,'1',Rin(2),R2);
    reg3: REG PORT MAP(dbu,'1',Rin(3),R3);
    tri0: tris PORT MAP (R0,Rout(0),dbu);
    tri1: tris PORT MAP (R1,Rout(1),dbu);
    tri2: tris PORT MAP (R2,Rout(2),dbu);
    tri3: tris PORT MAP (R3,Rout(3),dbu);
    L <= dbu;
    --p0 <= R0;
    --p1 <= R1;
    --p2 <= R2;
    --p3 <= R3;
    --pin <= Rin;
    --pout<= Rout;
end Behavioral;