bash generate-sockit-qsys.sh
2013.10.01.17:42:21 Progress: Loading data/sockit.qsys
2013.10.01.17:42:21 Progress: Reading input file
2013.10.01.17:42:22 Progress: Adding clk_0 [clock_source 13.0]
2013.10.01.17:42:23 Progress: Parameterizing module clk_0
2013.10.01.17:42:23 Progress: Adding hps_0 [altera_hps 13.0.1]
2013.10.01.17:42:28 Progress: Parameterizing module hps_0
2013.10.01.17:42:28 Progress: Adding mem_if_ddr3_emif_0 [altera_mem_if_ddr3_emif 13.0]
2013.10.01.17:42:29 Progress: Parameterizing module mem_if_ddr3_emif_0
2013.10.01.17:42:29 Progress: Adding mm_bridge_0 [altera_avalon_mm_bridge 13.0]
2013.10.01.17:42:30 Progress: Parameterizing module mm_bridge_0
2013.10.01.17:42:30 Progress: Building connections
2013.10.01.17:42:30 Progress: Parameterizing connections
2013.10.01.17:42:30 Progress: Validating
2013.10.01.17:43:09 Progress: Done reading input file
2013.10.01.17:43:16 Warning: sockit.hps_0: Setting the slave port width of interface f2h_sdram0 to 32 results in bandwidth under-utilization.  Altera recommends you set the interface data width to 64-bit or greater.
2013.10.01.17:43:16 Info: sockit.hps_0: Peripheral EMAC1 pin mapping: TX_CLK:MIXED1IO0, TXD0:MIXED1IO1, TXD1:MIXED1IO2, TXD2:MIXED1IO3, TXD3:MIXED1IO4, RXD0:MIXED1IO5, MDIO:MIXED1IO6, MDC:MIXED1IO7, RX_CTL:MIXED1IO8, TX_CTL:MIXED1IO9, RX_CLK:MIXED1IO10, RXD1:MIXED1IO11, RXD2:MIXED1IO12, RXD3:MIXED1IO13
2013.10.01.17:43:16 Info: sockit.hps_0: Peripheral QSPI pin mapping: IO0:MIXED1IO15, IO1:MIXED1IO16, IO2:MIXED1IO17, IO3:MIXED1IO18, SS0:MIXED1IO19, CLK:MIXED1IO20
2013.10.01.17:43:16 Info: sockit.hps_0: Peripheral SDIO pin mapping: CMD:FLASHIO0, D0:FLASHIO2, D1:FLASHIO3, CLK:FLASHIO9, D2:FLASHIO10, D3:FLASHIO11
2013.10.01.17:43:16 Info: sockit.hps_0: Peripheral USB1 pin mapping: D0:EMACIO1, D1:EMACIO2, D2:EMACIO3, D3:EMACIO4, D4:EMACIO5, D5:EMACIO6, D6:EMACIO7, D7:EMACIO8, CLK:EMACIO10, STP:EMACIO11, DIR:EMACIO12, NXT:EMACIO13
2013.10.01.17:43:16 Info: sockit.hps_0: Peripheral SPIM0 pin mapping: CLK:GENERALIO9, MOSI:GENERALIO10, MISO:GENERALIO11, SS0:GENERALIO12
2013.10.01.17:43:16 Info: sockit.hps_0: Peripheral SPIM1 pin mapping: CLK:GENERALIO15, MOSI:GENERALIO16, MISO:GENERALIO17, SS0:GENERALIO18
2013.10.01.17:43:16 Info: sockit.hps_0: Peripheral UART0 pin mapping: RX:GENERALIO1, TX:GENERALIO2
2013.10.01.17:43:16 Info: sockit.hps_0: Peripheral I2C1 pin mapping: SDA:GENERALIO3, SCL:GENERALIO4
2013.10.01.17:43:16 Warning: sockit.hps_0.fpga_interfaces.emac0_tx_reset: Associated reset sinks not declared
2013.10.01.17:43:16 Warning: sockit.hps_0.fpga_interfaces.emac0_rx_reset: Associated reset sinks not declared
2013.10.01.17:43:16 Warning: sockit.mem_if_ddr3_emif_0: The 'Type' value must be set to Bidirectional if you plan to simulate the example design.
2013.10.01.17:43:21 Progress: Loading data/sockit.qsys
2013.10.01.17:43:22 Progress: Reading input file
2013.10.01.17:43:22 Progress: Adding clk_0 [clock_source 13.0]
2013.10.01.17:43:23 Progress: Parameterizing module clk_0
2013.10.01.17:43:23 Progress: Adding hps_0 [altera_hps 13.0.1]
2013.10.01.17:43:28 Progress: Parameterizing module hps_0
2013.10.01.17:43:28 Progress: Adding mem_if_ddr3_emif_0 [altera_mem_if_ddr3_emif 13.0]
2013.10.01.17:43:29 Progress: Parameterizing module mem_if_ddr3_emif_0
2013.10.01.17:43:29 Progress: Adding mm_bridge_0 [altera_avalon_mm_bridge 13.0]
2013.10.01.17:43:30 Progress: Parameterizing module mm_bridge_0
2013.10.01.17:43:30 Progress: Building connections
2013.10.01.17:43:31 Progress: Parameterizing connections
2013.10.01.17:43:31 Progress: Validating
2013.10.01.17:44:09 Progress: Done reading input file
2013.10.01.17:44:16 Warning: sockit.hps_0: Setting the slave port width of interface f2h_sdram0 to 32 results in bandwidth under-utilization.  Altera recommends you set the interface data width to 64-bit or greater.
2013.10.01.17:44:16 Info: sockit.hps_0: Peripheral EMAC1 pin mapping: TX_CLK:MIXED1IO0, TXD0:MIXED1IO1, TXD1:MIXED1IO2, TXD2:MIXED1IO3, TXD3:MIXED1IO4, RXD0:MIXED1IO5, MDIO:MIXED1IO6, MDC:MIXED1IO7, RX_CTL:MIXED1IO8, TX_CTL:MIXED1IO9, RX_CLK:MIXED1IO10, RXD1:MIXED1IO11, RXD2:MIXED1IO12, RXD3:MIXED1IO13
2013.10.01.17:44:16 Info: sockit.hps_0: Peripheral QSPI pin mapping: IO0:MIXED1IO15, IO1:MIXED1IO16, IO2:MIXED1IO17, IO3:MIXED1IO18, SS0:MIXED1IO19, CLK:MIXED1IO20
2013.10.01.17:44:16 Info: sockit.hps_0: Peripheral SDIO pin mapping: CMD:FLASHIO0, D0:FLASHIO2, D1:FLASHIO3, CLK:FLASHIO9, D2:FLASHIO10, D3:FLASHIO11
2013.10.01.17:44:16 Info: sockit.hps_0: Peripheral USB1 pin mapping: D0:EMACIO1, D1:EMACIO2, D2:EMACIO3, D3:EMACIO4, D4:EMACIO5, D5:EMACIO6, D6:EMACIO7, D7:EMACIO8, CLK:EMACIO10, STP:EMACIO11, DIR:EMACIO12, NXT:EMACIO13
2013.10.01.17:44:16 Info: sockit.hps_0: Peripheral SPIM0 pin mapping: CLK:GENERALIO9, MOSI:GENERALIO10, MISO:GENERALIO11, SS0:GENERALIO12
2013.10.01.17:44:16 Info: sockit.hps_0: Peripheral SPIM1 pin mapping: CLK:GENERALIO15, MOSI:GENERALIO16, MISO:GENERALIO17, SS0:GENERALIO18
2013.10.01.17:44:16 Info: sockit.hps_0: Peripheral UART0 pin mapping: RX:GENERALIO1, TX:GENERALIO2
2013.10.01.17:44:16 Info: sockit.hps_0: Peripheral I2C1 pin mapping: SDA:GENERALIO3, SCL:GENERALIO4
2013.10.01.17:44:16 Warning: sockit.hps_0.fpga_interfaces.emac0_tx_reset: Associated reset sinks not declared
2013.10.01.17:44:16 Warning: sockit.hps_0.fpga_interfaces.emac0_rx_reset: Associated reset sinks not declared
2013.10.01.17:44:16 Warning: sockit.mem_if_ddr3_emif_0: The 'Type' value must be set to Bidirectional if you plan to simulate the example design.

2013.10.01.17:52:24 Info: sockit: Generating sockit "sockit" for QUARTUS_SYNTH
2013.10.01.17:52:37 Info: pipeline_bridge_swap_transform: After transform: 4 modules, 29 connections
2013.10.01.17:52:37 Info: No custom instruction connections, skipping transform
2013.10.01.17:52:38 Info: merlin_translator_transform: After transform: 6 modules, 35 connections
2013.10.01.17:52:39 Info: merlin_domain_transform: After transform: 16 modules, 85 connections
2013.10.01.17:52:39 Info: merlin_router_transform: After transform: 22 modules, 103 connections
2013.10.01.17:52:40 Info: merlin_burst_transform: After transform: 24 modules, 109 connections
2013.10.01.17:52:40 Info: com_altera_sopcmodel_transforms_avalon_CombinedWidthTransform: After transform: 25 modules, 113 connections
2013.10.01.17:52:40 Info: reset_adaptation_transform: After transform: 29 modules, 119 connections
2013.10.01.17:52:40 Info: merlin_network_to_switch_transform: After transform: 39 modules, 139 connections
2013.10.01.17:52:41 Info: merlin_mm_transform: After transform: 39 modules, 139 connections
2013.10.01.17:52:53 Info: hps_0: "Doing Pretransform for module: hps_0"
2013.10.01.17:52:53 Warning: hps_0: Setting the slave port width of interface f2h_sdram0 to 32 results in bandwidth under-utilization.  Altera recommends you set the interface data width to 64-bit or greater.
2013.10.01.17:52:53 Info: hps_0: Peripheral EMAC1 pin mapping: TX_CLK:MIXED1IO0, TXD0:MIXED1IO1, TXD1:MIXED1IO2, TXD2:MIXED1IO3, TXD3:MIXED1IO4, RXD0:MIXED1IO5, MDIO:MIXED1IO6, MDC:MIXED1IO7, RX_CTL:MIXED1IO8, TX_CTL:MIXED1IO9, RX_CLK:MIXED1IO10, RXD1:MIXED1IO11, RXD2:MIXED1IO12, RXD3:MIXED1IO13
2013.10.01.17:52:53 Info: hps_0: Peripheral QSPI pin mapping: IO0:MIXED1IO15, IO1:MIXED1IO16, IO2:MIXED1IO17, IO3:MIXED1IO18, SS0:MIXED1IO19, CLK:MIXED1IO20
2013.10.01.17:52:53 Info: hps_0: Peripheral SDIO pin mapping: CMD:FLASHIO0, D0:FLASHIO2, D1:FLASHIO3, CLK:FLASHIO9, D2:FLASHIO10, D3:FLASHIO11
2013.10.01.17:52:53 Info: hps_0: Peripheral USB1 pin mapping: D0:EMACIO1, D1:EMACIO2, D2:EMACIO3, D3:EMACIO4, D4:EMACIO5, D5:EMACIO6, D6:EMACIO7, D7:EMACIO8, CLK:EMACIO10, STP:EMACIO11, DIR:EMACIO12, NXT:EMACIO13
2013.10.01.17:52:53 Info: hps_0: Peripheral SPIM0 pin mapping: CLK:GENERALIO9, MOSI:GENERALIO10, MISO:GENERALIO11, SS0:GENERALIO12
2013.10.01.17:52:53 Info: hps_0: Peripheral SPIM1 pin mapping: CLK:GENERALIO15, MOSI:GENERALIO16, MISO:GENERALIO17, SS0:GENERALIO18
2013.10.01.17:52:53 Info: hps_0: Peripheral UART0 pin mapping: RX:GENERALIO1, TX:GENERALIO2
2013.10.01.17:52:53 Info: hps_0: Peripheral I2C1 pin mapping: SDA:GENERALIO3, SCL:GENERALIO4
2013.10.01.17:52:54 Warning: hps_0.fpga_interfaces.emac0_tx_reset: Associated reset sinks not declared
2013.10.01.17:52:54 Warning: hps_0.fpga_interfaces.emac0_rx_reset: Associated reset sinks not declared
2013.10.01.17:52:54 Info: pipeline_bridge_swap_transform: After transform: 2 modules, 0 connections
2013.10.01.17:52:54 Info: No custom instruction connections, skipping transform
2013.10.01.17:52:54 Info: No Avalon connections, skipping transform
2013.10.01.17:52:54 Info: merlin_translator_transform: After transform: 2 modules, 0 connections
2013.10.01.17:52:56 Info: hps_0: "sockit" instantiated altera_hps "hps_0"
2013.10.01.17:52:57 Info: pipeline_bridge_swap_transform: After transform: 21 modules, 38 connections
2013.10.01.17:52:57 Info: No custom instruction connections, skipping transform
2013.10.01.17:52:57 Info: merlin_translator_transform: After transform: 21 modules, 38 connections
2013.10.01.17:52:58 Info: mem_if_ddr3_emif_0: "sockit" instantiated altera_mem_if_ddr3_emif "mem_if_ddr3_emif_0"
2013.10.01.17:52:58 Info: mm_bridge_0: "sockit" instantiated altera_avalon_mm_bridge "mm_bridge_0"
2013.10.01.17:52:58 Info: mem_if_ddr3_emif_0_avl_1_translator: "sockit" instantiated altera_merlin_slave_translator "mem_if_ddr3_emif_0_avl_1_translator"
2013.10.01.17:52:58 Info: hps_0_h2f_axi_master_agent: "sockit" instantiated altera_merlin_axi_master_ni "hps_0_h2f_axi_master_agent"
2013.10.01.17:52:58 Info: mem_if_ddr3_emif_0_avl_1_translator_avalon_universal_slave_0_agent: "sockit" instantiated altera_merlin_slave_agent "mem_if_ddr3_emif_0_avl_1_translator_avalon_universal_slave_0_agent"
2013.10.01.17:52:58 Info: mem_if_ddr3_emif_0_avl_1_translator_avalon_universal_slave_0_agent_rsp_fifo: "sockit" instantiated altera_avalon_sc_fifo "mem_if_ddr3_emif_0_avl_1_translator_avalon_universal_slave_0_agent_rsp_fifo"
2013.10.01.17:52:58 Info: addr_router: "sockit" instantiated altera_merlin_router "addr_router"
2013.10.01.17:52:58 Info: id_router: "sockit" instantiated altera_merlin_router "id_router"
2013.10.01.17:52:58 Info: addr_router_002: "sockit" instantiated altera_merlin_router "addr_router_002"
2013.10.01.17:52:58 Info: id_router_001: "sockit" instantiated altera_merlin_router "id_router_001"
2013.10.01.17:52:58 Info: burst_adapter: "sockit" instantiated altera_merlin_burst_adapter "burst_adapter"
2013.10.01.17:52:58 Info: Reusing file /home/jack/HDL/src/openrisc/orpsocv3/build-orpsoc/build/sockit/src/qsys/synthesis/submodules/altera_merlin_address_alignment.sv
2013.10.01.17:52:58 Info: width_adapter: "sockit" instantiated altera_merlin_combined_width_adapter "width_adapter"
2013.10.01.17:52:58 Info: Reusing file /home/jack/HDL/src/openrisc/orpsocv3/build-orpsoc/build/sockit/src/qsys/synthesis/submodules/altera_merlin_address_alignment.sv
2013.10.01.17:52:58 Info: Reusing file /home/jack/HDL/src/openrisc/orpsocv3/build-orpsoc/build/sockit/src/qsys/synthesis/submodules/altera_merlin_burst_uncompressor.sv
2013.10.01.17:52:58 Info: Reusing file /home/jack/HDL/src/openrisc/orpsocv3/build-orpsoc/build/sockit/src/qsys/synthesis/submodules/altera_avalon_sc_fifo.v
2013.10.01.17:52:58 Info: rst_controller: "sockit" instantiated altera_reset_controller "rst_controller"
2013.10.01.17:52:58 Info: cmd_xbar_demux: "sockit" instantiated altera_merlin_demultiplexer "cmd_xbar_demux"
2013.10.01.17:52:58 Info: cmd_xbar_mux: "sockit" instantiated altera_merlin_multiplexer "cmd_xbar_mux"
2013.10.01.17:52:58 Info: rsp_xbar_demux: "sockit" instantiated altera_merlin_demultiplexer "rsp_xbar_demux"
2013.10.01.17:52:58 Info: cmd_xbar_demux_002: "sockit" instantiated altera_merlin_demultiplexer "cmd_xbar_demux_002"
2013.10.01.17:52:58 Info: cmd_xbar_mux_001: "sockit" instantiated altera_merlin_multiplexer "cmd_xbar_mux_001"
2013.10.01.17:52:58 Info: Reusing file /home/jack/HDL/src/openrisc/orpsocv3/build-orpsoc/build/sockit/src/qsys/synthesis/submodules/altera_merlin_arbitrator.sv
2013.10.01.17:52:58 Info: rsp_xbar_demux_001: "sockit" instantiated altera_merlin_demultiplexer "rsp_xbar_demux_001"
2013.10.01.17:52:59 Info: fpga_interfaces: "hps_0" instantiated altera_interface_generator "fpga_interfaces"
2013.10.01.17:52:59 Info: pipeline_bridge_swap_transform: After transform: 1 modules, 0 connections
2013.10.01.17:52:59 Info: No custom instruction connections, skipping transform
2013.10.01.17:52:59 Info: No Avalon connections, skipping transform
2013.10.01.17:52:59 Info: merlin_translator_transform: After transform: 1 modules, 0 connections
2013.10.01.17:52:59 Info: hps_io: "hps_0" instantiated altera_hps_io "hps_io"
2013.10.01.17:53:00 Info: pll0: "mem_if_ddr3_emif_0" instantiated altera_mem_if_ddr3_pll "pll0"
2013.10.01.17:53:00 Info: p0: Generating clock pair generator
2013.10.01.17:53:03 Info: p0: Generating sockit_mem_if_ddr3_emif_0_p0_altdqdqs
2013.10.01.17:53:14 Info: p0:
2013.10.01.17:53:14 Info: p0: *****************************
2013.10.01.17:53:14 Info: p0:
2013.10.01.17:53:14 Info: p0: Remember to run the sockit_mem_if_ddr3_emif_0_p0_pin_assignments.tcl
2013.10.01.17:53:14 Info: p0: script after running Synthesis and before Fitting.
2013.10.01.17:53:14 Info: p0:
2013.10.01.17:53:14 Info: p0: *****************************
2013.10.01.17:53:14 Info: p0:
2013.10.01.17:53:14 Info: p0: "mem_if_ddr3_emif_0" instantiated altera_mem_if_ddr3_hard_phy_core "p0"
2013.10.01.17:53:27 Info: s0: Generating Qsys sequencer system
2013.10.01.17:53:46 Info: s0: QSYS sequencer system generated successfully
2013.10.01.17:53:58 Error: s0: add_fileset_file: No such file /tmp/alt5979_2523067609113345449.dir/0019_s0_gen/qsys/sockit_mem_if_ddr3_emif_0_s0_sequencer_mem.hex
    while executing
"add_fileset_file $file_name [::alt_mem_if::util::hwtcl_utils::get_file_type $file_name 0] PATH $generated_file"
    ("foreach" body line 4)
    invoked from within
"foreach generated_file [alt_mem_if::gen::uniphy_gen::generate_sequencer_files $name "DDR3" $tmpdir QUARTUS_SYNTH] {
		set file_name [file tail $genera..."
    (procedure "generate_synth" line 8)
    invoked from within
"generate_synth sockit_mem_if_ddr3_emif_0_s0"
2013.10.01.17:53:58 Info: s0: "mem_if_ddr3_emif_0" instantiated altera_mem_if_ddr3_qseq "s0"
2013.10.01.17:53:58 Info: Reusing file /home/jack/HDL/src/openrisc/orpsocv3/build-orpsoc/build/sockit/src/qsys/synthesis/submodules/altera_avalon_sc_fifo.v
2013.10.01.17:53:59 Info: Reusing file /home/jack/HDL/src/openrisc/orpsocv3/build-orpsoc/build/sockit/src/qsys/synthesis/submodules/altera_merlin_slave_agent.sv
2013.10.01.17:53:59 Info: Reusing file /home/jack/HDL/src/openrisc/orpsocv3/build-orpsoc/build/sockit/src/qsys/synthesis/submodules/altera_merlin_slave_translator.sv
2013.10.01.17:53:59 Info: Reusing file /home/jack/HDL/src/openrisc/orpsocv3/build-orpsoc/build/sockit/src/qsys/synthesis/submodules/altera_merlin_arbitrator.sv
2013.10.01.17:53:59 Info: Reusing file /home/jack/HDL/src/openrisc/orpsocv3/build-orpsoc/build/sockit/src/qsys/synthesis/submodules/altera_merlin_burst_uncompressor.sv
2013.10.01.17:53:59 Error: Generation stopped, 4 or more modules remaining