//----------------------------------------
//module bit stream generator
//-----------------------------------------

module generator(
clk,
stream  //generated stream
);
output stream;
input clk;
reg c;
wire stream;
assign stream=c;

initial
begin
c=1'd0;
end

always@(posedge clk)
begin
    //c=!c;
    c = {$random} %2;
    //$display("a= %b",c);
end
endmodule



//----------------------------------------
//module D flip flip
//-----------------------------------------

module d(q_w,q0_w,d,c);
output q_w,q0_w;
input c,d;

//wire c;
reg q,q0;
wire q_w,q0_w;
assign q_w=q;
assign q0_w=q0;

    initial
       begin
           q=1'b0; q0=1'b1;
      end
    always @ (posedge c)
       begin
         q=d;
         q0= ~d;
       end
endmodule


//----------------------------------------
//module sequencedetector
//-----------------------------------------

module sequencedetector(
clk,
x,  //input bit stream
out //output from sequence detector
);

input x,clk;
output out;

wire x,y0,y_0,y1,y_1,g12,g32,g2d1,out;

d dff1(.q_w(y1),.q0_w(y_1),.d(g2d1),.c(clk));   //flip flop D1
d dff0(.q_w(y0),.q0_w(y_0),.d(x),.c(clk));  //Flip Flop D2

and gate1(g12,x,y0);
or gate2(g2d1,g12,g32);
and gate3(g32,y1,y0);
and gate4(out,x,y_0,y1);

endmodule


//----------------------------------------
//module sequencedetector testbench
//-----------------------------------------

module sequencedetector_tb;

reg clk;
wire out,x;

sequencedetector UUT(
.clk(clk),
.x(x),
.out(out));

generator UUTgen(
.clk(clk),
.stream(x));



initial begin
clk=1'b0;
//stream=1'b0;
//=1'b0;
end

initial
begin
    $dumpfile ("counter.vcd");
    $dumpvars(0);
end

always
    begin
    #20 clk=!clk;
    end

initial
    begin
    #20000 $finish;
    end
endmodule