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  1. Exynos 5 Octa (Odroid-XU)
  2.  
  3. tinymembench v0.3.9 (simple benchmark for memory throughput and latency)
  4.  
  5. ==========================================================================
  6. == Memory bandwidth tests ==
  7. == ==
  8. == Note 1: 1MB = 1000000 bytes ==
  9. == Note 2: Results for 'copy' tests show how many bytes can be ==
  10. == copied per second (adding together read and writen ==
  11. == bytes would have provided twice higher numbers) ==
  12. == Note 3: 2-pass copy means that we are using a small temporary buffer ==
  13. == to first fetch data into it, and only then write it to the ==
  14. == destination (source -> L1 cache, L1 cache -> destination) ==
  15. == Note 4: If sample standard deviation exceeds 0.1%, it is shown in ==
  16. == brackets ==
  17. ==========================================================================
  18.  
  19. C copy backwards : 1408.9 MB/s
  20. C copy : 1458.0 MB/s
  21. C copy prefetched (32 bytes step) : 1632.0 MB/s
  22. C copy prefetched (64 bytes step) : 1632.7 MB/s
  23. C 2-pass copy : 1299.5 MB/s (0.6%)
  24. C 2-pass copy prefetched (32 bytes step) : 1555.9 MB/s (0.7%)
  25. C 2-pass copy prefetched (64 bytes step) : 1556.3 MB/s
  26. C fill : 2865.8 MB/s
  27. ---
  28. standard memcpy : 2382.8 MB/s
  29. standard memset : 2861.9 MB/s (0.8%)
  30. ---
  31. NEON read : 3765.0 MB/s
  32. NEON read prefetched (32 bytes step) : 4661.8 MB/s
  33. NEON read prefetched (64 bytes step) : 4673.9 MB/s
  34. NEON read 2 data streams : 3809.4 MB/s
  35. NEON read 2 data streams prefetched (32 bytes step) : 4701.5 MB/s
  36. NEON read 2 data streams prefetched (64 bytes step) : 4702.1 MB/s
  37. NEON copy : 2366.7 MB/s
  38. NEON copy prefetched (32 bytes step) : 2422.4 MB/s (0.7%)
  39. NEON copy prefetched (64 bytes step) : 2404.0 MB/s
  40. NEON unrolled copy : 2197.9 MB/s
  41. NEON unrolled copy prefetched (32 bytes step) : 2523.3 MB/s
  42. NEON unrolled copy prefetched (64 bytes step) : 2525.9 MB/s
  43. NEON copy backwards : 1449.5 MB/s
  44. NEON copy backwards prefetched (32 bytes step) : 1625.0 MB/s
  45. NEON copy backwards prefetched (64 bytes step) : 1624.6 MB/s
  46. NEON 2-pass copy : 1690.0 MB/s
  47. NEON 2-pass copy prefetched (32 bytes step) : 1793.1 MB/s (0.5%)
  48. NEON 2-pass copy prefetched (64 bytes step) : 1810.1 MB/s (0.5%)
  49. NEON unrolled 2-pass copy : 1482.5 MB/s
  50. NEON unrolled 2-pass copy prefetched (32 bytes step) : 1825.5 MB/s
  51. NEON unrolled 2-pass copy prefetched (64 bytes step) : 1851.7 MB/s
  52. NEON fill : 2857.2 MB/s (0.8%)
  53. NEON fill backwards : 2156.5 MB/s
  54. VFP copy : 2373.5 MB/s
  55. VFP 2-pass copy : 1486.1 MB/s
  56. ARM fill (STRD) : 2859.6 MB/s (0.4%)
  57. ARM fill (STM with 8 registers) : 2860.0 MB/s (0.9%)
  58. ARM fill (STM with 4 registers) : 2855.3 MB/s (0.2%)
  59. ARM copy prefetched (incr pld) : 2471.9 MB/s
  60. ARM copy prefetched (wrap pld) : 2422.7 MB/s
  61. ARM 2-pass copy prefetched (incr pld) : 1739.1 MB/s
  62. ARM 2-pass copy prefetched (wrap pld) : 1693.7 MB/s
  63.  
  64. ==========================================================================
  65. == Memory latency test ==
  66. == ==
  67. == Average time is measured for random memory accesses in the buffers ==
  68. == of different sizes. The larger is the buffer, the more significant ==
  69. == are relative contributions of TLB, L1/L2 cache misses and SDRAM ==
  70. == accesses. For extremely large buffer sizes we are expecting to see ==
  71. == page table walk with several requests to SDRAM for almost every ==
  72. == memory access (though 64MiB is not nearly large enough to experience ==
  73. == this effect to its fullest). ==
  74. == ==
  75. == Note 1: All the numbers are representing extra time, which needs to ==
  76. == be added to L1 cache latency. The cycle timings for L1 cache ==
  77. == latency can be usually found in the processor documentation. ==
  78. == Note 2: Dual random read means that we are simultaneously performing ==
  79. == two independent memory accesses at a time. In the case if ==
  80. == the memory subsystem can't handle multiple outstanding ==
  81. == requests, dual random read has the same timings as two ==
  82. == single reads performed one after another. ==
  83. ==========================================================================
  84.  
  85. block size : single random read / dual random read
  86. 1024 : 0.0 ns / 0.0 ns
  87. 2048 : 0.0 ns / 0.0 ns
  88. 4096 : 0.0 ns / 0.0 ns
  89. 8192 : 0.0 ns / 0.0 ns
  90. 16384 : 0.0 ns / 0.1 ns
  91. 32768 : 0.0 ns / 0.1 ns
  92. 65536 : 5.5 ns / 8.6 ns
  93. 131072 : 8.4 ns / 11.3 ns
  94. 262144 : 12.0 ns / 14.9 ns
  95. 524288 : 13.8 ns / 17.0 ns
  96. 1048576 : 14.8 ns / 18.2 ns
  97. 2097152 : 19.4 ns / 24.4 ns
  98. 4194304 : 88.2 ns / 133.9 ns
  99. 8388608 : 123.7 ns / 173.3 ns
  100. 16777216 : 141.6 ns / 190.5 ns
  101. 33554432 : 158.6 ns / 214.1 ns
  102. 67108864 : 168.8 ns / 229.5 ns
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