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- Disassembly Listing for multiples pwm
- Generated From:
- /Users/andrestorti/Downloads/multiples pwm.X/dist/default/production/multiples_pwm.X.production.cof
- Sep 17, 2015 12:50:38 AM
- --- /Users/andrestorti/Downloads/multiples pwm.X/main.c -----------------------------------------------
- 1: /*
- 2: * File: main.c
- 3: * Author: LEO
- 4: *
- 5: * Created on 16 de septiembre de 2015, 16:46
- 6: */
- 7:
- 8: #include <xc.h>
- 9:
- 10: // CONFIG1H
- 11: #pragma config FOSC = INTIO67 // Oscillator Selection bits (Internal oscillator block, port function on RA6 and RA7)
- 12: #pragma config FCMEN = OFF // Fail-Safe Clock Monitor Enable bit (Fail-Safe Clock Monitor disabled)
- 13: #pragma config IESO = OFF // Internal/External Oscillator Switchover bit (Oscillator Switchover mode disabled)
- 14:
- 15: // CONFIG2L
- 16: #pragma config PWRT = OFF // Power-up Timer Enable bit (PWRT disabled)
- 17: #pragma config BOREN = SBORDIS // Brown-out Reset Enable bits (Brown-out Reset enabled in hardware only (SBOREN is disabled))
- 18: #pragma config BORV = 18 // Brown Out Reset Voltage bits (VBOR set to 1.8 V nominal)
- 19:
- 20: // CONFIG2H
- 21: #pragma config WDTEN = OFF // Watchdog Timer Enable bit (WDT is controlled by SWDTEN bit of the WDTCON register)
- 22: #pragma config WDTPS = 32768 // Watchdog Timer Postscale Select bits (1:32768)
- 23:
- 24: // CONFIG3H
- 25: #pragma config CCP2MX = PORTC // CCP2 MUX bit (CCP2 input/output is multiplexed with RC1)
- 26: #pragma config PBADEN = OFF // PORTB A/D Enable bit (PORTB<4:0> pins are configured as digital I/O on Reset)
- 27: #pragma config LPT1OSC = OFF // Low-Power Timer1 Oscillator Enable bit (Timer1 configured for higher power operation)
- 28: #pragma config HFOFST = OFF // HFINTOSC Fast Start-up (The system clock is held off until the HFINTOSC is stable.)
- 29: #pragma config MCLRE = OFF // MCLR Pin Enable bit (RE3 input pin enabled; MCLR disabled)
- 30:
- 31: // CONFIG4L
- 32: #pragma config STVREN = OFF // Stack Full/Underflow Reset Enable bit (Stack full/underflow will not cause Reset)
- 33: #pragma config LVP = ON // Single-Supply ICSP Enable bit (Single-Supply ICSP enabled)
- 34: #pragma config XINST = OFF // Extended Instruction Set Enable bit (Instruction set extension and Indexed Addressing mode disabled (Legacy mode))
- 35:
- 36: // CONFIG5L
- 37: #pragma config CP0 = OFF // Code Protection Block 0 (Block 0 (000800-001FFFh) not code-protected)
- 38: #pragma config CP1 = OFF // Code Protection Block 1 (Block 1 (002000-003FFFh) not code-protected)
- 39: #pragma config CP2 = OFF // Code Protection Block 2 (Block 2 (004000-005FFFh) not code-protected)
- 40: #pragma config CP3 = OFF // Code Protection Block 3 (Block 3 (006000-007FFFh) not code-protected)
- 41:
- 42: // CONFIG5H
- 43: #pragma config CPB = OFF // Boot Block Code Protection bit (Boot block (000000-0007FFh) not code-protected)
- 44: #pragma config CPD = OFF // Data EEPROM Code Protection bit (Data EEPROM not code-protected)
- 45:
- 46: // CONFIG6L
- 47: #pragma config WRT0 = OFF // Write Protection Block 0 (Block 0 (000800-001FFFh) not write-protected)
- 48: #pragma config WRT1 = OFF // Write Protection Block 1 (Block 1 (002000-003FFFh) not write-protected)
- 49: #pragma config WRT2 = OFF // Write Protection Block 2 (Block 2 (004000-005FFFh) not write-protected)
- 50: #pragma config WRT3 = OFF // Write Protection Block 3 (Block 3 (006000-007FFFh) not write-protected)
- 51:
- 52: // CONFIG6H
- 53: #pragma config WRTC = OFF // Configuration Register Write Protection bit (Configuration registers (300000-3000FFh) not write-protected)
- 54: #pragma config WRTB = OFF // Boot Block Write Protection bit (Boot Block (000000-0007FFh) not write-protected)
- 55: #pragma config WRTD = OFF // Data EEPROM Write Protection bit (Data EEPROM not write-protected)
- 56:
- 57: // CONFIG7L
- 58: #pragma config EBTR0 = OFF // Table Read Protection Block 0 (Block 0 (000800-001FFFh) not protected from table reads executed in other blocks)
- 59: #pragma config EBTR1 = OFF // Table Read Protection Block 1 (Block 1 (002000-003FFFh) not protected from table reads executed in other blocks)
- 60: #pragma config EBTR2 = OFF // Table Read Protection Block 2 (Block 2 (004000-005FFFh) not protected from table reads executed in other blocks)
- 61: #pragma config EBTR3 = OFF // Table Read Protection Block 3 (Block 3 (006000-007FFFh) not protected from table reads executed in other blocks)
- 62:
- 63: // CONFIG7H
- 64: #pragma config EBTRB = OFF // Boot Block Table Read Protection bit (Boot Block (000000-0007FFh) not protected from table reads executed in other blocks)
- 65:
- 66: #define led1red LATAbits.LATA4
- 67: #define led1green LATAbits.LATA5
- 68: #define led1blue LATEbits.LATE0
- 69:
- 70: #define led2red LATEbits.LATE1
- 71: #define led2green LATEbits.LATE2
- 72: #define led2blue LATAbits.LATA7
- 73:
- 74: #define led3red LATAbits.LATA6
- 75: #define led3green LATCbits.LATC0
- 76: #define led3blue LATCbits.LATC1
- 77:
- 78: #define led4red LATCbits.LATC2
- 79: #define led4green LATCbits.LATC3
- 80: #define led4blue LATDbits.LATD0
- 81:
- 82: #define led5red LATDbits.LATD1
- 83: #define led5green LATDbits.LATD2
- 84: #define led5blue LATDbits.LATD3
- 85:
- 86: #define led6red LATCbits.LATC4
- 87: #define led6green LATCbits.LATC6
- 88: #define led6blue LATDbits.LATD4
- 89:
- 90: #define led7red LATDbits.LATD5
- 91: #define led7green LATDbits.LATD6
- 92: #define led7blue LATDbits.LATD7
- 93:
- 94: #define led8red LATBbits.LATB0
- 95: #define led8green LATBbits.LATB1
- 96: #define led8blue LATBbits.LATB2
- 97:
- 98: #define led9red LATBbits.LATB3
- 99: #define led9green LATBbits.LATB4
- 100: #define led9blue LATBbits.LATB5
- 101:
- 102:
- 103: //demas pines utilizados
- 104: #define MCLR PORTEbits.RE3
- 105: #define PGC LATBbits.LATB6
- 106: #define PGD LATBbits.LATB7
- 107: #define ANALOG0 PORTAbits.RA0
- 108: #define ANALOG1 PORTAbits.RA1
- 109: #define ANALOG2 PORTAbits.RA2
- 110: #define ANALOG3 PORTAbits.RA3
- 111:
- 112:
- 113:
- 114:
- 115:
- 116: #define duty1red dutys[0]
- 117: #define duty1green dutys[1]
- 118: #define duty1blue dutys[2]
- 119: #define duty2red dutys[3]
- 120: #define duty2green dutys[4]
- 121: #define duty2blue dutys[5]
- 122: #define duty3red dutys[6]
- 123: #define duty3green dutys[7]
- 124: #define duty3blue dutys[8]
- 125: #define duty4red dutys[9]
- 126: #define duty4green dutys[10]
- 127: #define duty4blue dutys[11]
- 128: #define duty5red dutys[12]
- 129: #define duty5green dutys[13]
- 130: #define duty5blue dutys[14]
- 131: #define duty6red dutys[15]
- 132: #define duty6green dutys[16]
- 133: #define duty6blue dutys[17]
- 134: #define duty7red dutys[18]
- 135: #define duty7green dutys[19]
- 136: #define duty7blue dutys[20]
- 137: #define duty8red dutys[21]
- 138: #define duty8green dutys[22]
- 139: #define duty8blue dutys[23]
- 140: #define duty9red dutys[24]
- 141: #define duty9green dutys[25]
- 142: #define duty9blue dutys[26]
- 143:
- 144: unsigned char anchodepulso=0;
- 145: unsigned char dutys[27] = { 245,100,100,
- 146: 10,10,10,
- 147: 10,10,10,
- 148: 10,10,10,
- 149: 10,10,10,
- 150: 10,150,10,
- 151: 10,10,10,
- 152: 10,10,10,
- 153: 100,100,100
- 154: };
- 155:
- 156: void interrupt YourHighPriorityISRCode(){
- 0008 CFFA MOVFF PCLATH, 0x12
- 00A8 CFEA MOVFF FSR0H, 0x15
- 00AA F015 NOP
- 00AC CFE1 MOVFF FSR1, 0x16
- 00AE F016 NOP
- 00B0 CFE2 MOVFF FSR1H, 0x17
- 00B2 F017 NOP
- 00B4 CFD9 MOVFF FSR2, 0x18
- 00B6 F018 NOP
- 00B8 CFDA MOVFF FSR2H, 0x19
- 00BA F019 NOP
- 00BC CFF3 MOVFF PROD, 0x1A
- 00BE F01A NOP
- 00C0 CFF4 MOVFF PRODH, 0x1B
- 00C2 F01B NOP
- 00C4 CFF6 MOVFF TBLPTR, 0x1C
- 00C6 F01C NOP
- 00C8 CFF7 MOVFF TBLPTRH, 0x1D
- 00CA F01D NOP
- 00CC CFF8 MOVFF TBLPTRU, 0x1E
- 00CE F01E NOP
- 00D0 CFF5 MOVFF TABLAT, 0x1F
- 00D2 F01F NOP
- 157: if(INTCONbits.TMR0IF){
- 00D4 A4F2 BTFSS INTCON, 2, ACCESS
- 00D6 D0DE BRA 0x294
- 158: anchodepulso++;
- 00D8 2A3B INCF anchodepulso, F, ACCESS
- 159:
- 160: if(anchodepulso<=duty1red){
- 00DA 503B MOVF anchodepulso, W, ACCESS
- 00DC 5C20 SUBWF dutys, W, ACCESS
- 00DE A0D8 BTFSS STATUS, 0, ACCESS
- 00E0 D002 BRA 0xE6
- 161: led1red=1;
- 00E2 8889 BSF LATA, 4, ACCESS
- 162: }else led1red=0;
- 00E4 D002 BRA 0xEA
- 00E6 9889 BCF LATA, 4, ACCESS
- 00E8 D000 BRA 0xEA
- 163:
- 164: if(anchodepulso<=duty1green){
- 00EA 503B MOVF anchodepulso, W, ACCESS
- 00EC 5C21 SUBWF 0x21, W, ACCESS
- 00EE A0D8 BTFSS STATUS, 0, ACCESS
- 00F0 D002 BRA 0xF6
- 165: led1green=1;
- 00F2 8A89 BSF LATA, 5, ACCESS
- 166: }else led1green=0;
- 00F4 D002 BRA 0xFA
- 00F6 9A89 BCF LATA, 5, ACCESS
- 00F8 D000 BRA 0xFA
- 167: if(anchodepulso<=duty1blue){
- 00FA 503B MOVF anchodepulso, W, ACCESS
- 00FC 5C22 SUBWF 0x22, W, ACCESS
- 00FE A0D8 BTFSS STATUS, 0, ACCESS
- 0100 D002 BRA 0x106
- 168: led1blue=1;
- 0102 808D BSF LATE, 0, ACCESS
- 169: }else led1blue=0;
- 0104 D002 BRA 0x10A
- 0106 908D BCF LATE, 0, ACCESS
- 0108 D000 BRA 0x10A
- 170:
- 171: if(anchodepulso<=duty2red){
- 010A 503B MOVF anchodepulso, W, ACCESS
- 010C 5C23 SUBWF 0x23, W, ACCESS
- 010E A0D8 BTFSS STATUS, 0, ACCESS
- 0110 D002 BRA 0x116
- 172: led2red=1;
- 0112 828D BSF LATE, 1, ACCESS
- 173: }else led2red=0;
- 0114 D002 BRA 0x11A
- 0116 928D BCF LATE, 1, ACCESS
- 0118 D000 BRA 0x11A
- 174: if(anchodepulso<=duty2green){
- 011A 503B MOVF anchodepulso, W, ACCESS
- 011C 5C24 SUBWF 0x24, W, ACCESS
- 011E A0D8 BTFSS STATUS, 0, ACCESS
- 0120 D002 BRA 0x126
- 175: led2green=1;
- 0122 848D BSF LATE, 2, ACCESS
- 176: }else led2green=0;
- 0124 D002 BRA 0x12A
- 0126 948D BCF LATE, 2, ACCESS
- 0128 D000 BRA 0x12A
- 177: if(anchodepulso<=duty2blue){
- 012A 503B MOVF anchodepulso, W, ACCESS
- 012C 5C25 SUBWF 0x25, W, ACCESS
- 012E A0D8 BTFSS STATUS, 0, ACCESS
- 0130 D002 BRA 0x136
- 178: led2blue=1;
- 0132 8E89 BSF LATA, 7, ACCESS
- 179: }else led2blue=0;
- 0134 D002 BRA 0x13A
- 0136 9E89 BCF LATA, 7, ACCESS
- 0138 D000 BRA 0x13A
- 180:
- 181: if(anchodepulso<=duty3red){
- 013A 503B MOVF anchodepulso, W, ACCESS
- 013C 5C26 SUBWF 0x26, W, ACCESS
- 013E A0D8 BTFSS STATUS, 0, ACCESS
- 0140 D002 BRA 0x146
- 182: led3red=1;
- 0142 8C89 BSF LATA, 6, ACCESS
- 183: }else led3red=0;
- 0144 D002 BRA 0x14A
- 0146 9C89 BCF LATA, 6, ACCESS
- 0148 D000 BRA 0x14A
- 184: if(anchodepulso<=duty3green){
- 014A 503B MOVF anchodepulso, W, ACCESS
- 014C 5C27 SUBWF 0x27, W, ACCESS
- 014E A0D8 BTFSS STATUS, 0, ACCESS
- 0150 D002 BRA 0x156
- 185: led3green=1;
- 0152 808B BSF LATC, 0, ACCESS
- 186: }else led3green=0;
- 0154 D002 BRA 0x15A
- 0156 908B BCF LATC, 0, ACCESS
- 0158 D000 BRA 0x15A
- 187: if(anchodepulso<=duty3blue){
- 015A 503B MOVF anchodepulso, W, ACCESS
- 015C 5C28 SUBWF 0x28, W, ACCESS
- 015E A0D8 BTFSS STATUS, 0, ACCESS
- 0160 D002 BRA 0x166
- 188: led3blue=1;
- 0162 828B BSF LATC, 1, ACCESS
- 189: }else led3blue=0;
- 0164 D002 BRA 0x16A
- 0166 928B BCF LATC, 1, ACCESS
- 0168 D000 BRA 0x16A
- 190:
- 191: if(anchodepulso<=duty4red){
- 016A 503B MOVF anchodepulso, W, ACCESS
- 016C 5C29 SUBWF 0x29, W, ACCESS
- 016E A0D8 BTFSS STATUS, 0, ACCESS
- 0170 D002 BRA 0x176
- 192: led4red=1;
- 0172 848B BSF LATC, 2, ACCESS
- 193: }else led4red=0;
- 0174 D002 BRA 0x17A
- 0176 948B BCF LATC, 2, ACCESS
- 0178 D000 BRA 0x17A
- 194: if(anchodepulso<=duty4green){
- 017A 503B MOVF anchodepulso, W, ACCESS
- 017C 5C2A SUBWF 0x2A, W, ACCESS
- 017E A0D8 BTFSS STATUS, 0, ACCESS
- 0180 D002 BRA 0x186
- 195: led4green=1;
- 0182 868B BSF LATC, 3, ACCESS
- 196: }else led4green=0;
- 0184 D002 BRA 0x18A
- 0186 968B BCF LATC, 3, ACCESS
- 0188 D000 BRA 0x18A
- 197: if(anchodepulso<=duty4blue){
- 018A 503B MOVF anchodepulso, W, ACCESS
- 018C 5C2B SUBWF 0x2B, W, ACCESS
- 018E A0D8 BTFSS STATUS, 0, ACCESS
- 0190 D002 BRA 0x196
- 198: led4blue=1;
- 0192 808C BSF LATD, 0, ACCESS
- 199: }else led4blue=0;
- 0194 D002 BRA 0x19A
- 0196 908C BCF LATD, 0, ACCESS
- 0198 D000 BRA 0x19A
- 200:
- 201: if(anchodepulso<=duty5red){
- 019A 503B MOVF anchodepulso, W, ACCESS
- 019C 5C2C SUBWF 0x2C, W, ACCESS
- 019E A0D8 BTFSS STATUS, 0, ACCESS
- 01A0 D002 BRA 0x1A6
- 202: led5red=1;
- 01A2 828C BSF LATD, 1, ACCESS
- 203: }else led5red=0;
- 01A4 D002 BRA 0x1AA
- 01A6 928C BCF LATD, 1, ACCESS
- 01A8 D000 BRA 0x1AA
- 204: if(anchodepulso<=duty5green){
- 01AA 503B MOVF anchodepulso, W, ACCESS
- 01AC 5C2D SUBWF 0x2D, W, ACCESS
- 01AE A0D8 BTFSS STATUS, 0, ACCESS
- 01B0 D002 BRA 0x1B6
- 205: led5green=1;
- 01B2 848C BSF LATD, 2, ACCESS
- 206: }else led5green=0;
- 01B4 D002 BRA 0x1BA
- 01B6 948C BCF LATD, 2, ACCESS
- 01B8 D000 BRA 0x1BA
- 207: if(anchodepulso<=duty5blue){
- 01BA 503B MOVF anchodepulso, W, ACCESS
- 01BC 5C2E SUBWF 0x2E, W, ACCESS
- 01BE A0D8 BTFSS STATUS, 0, ACCESS
- 01C0 D002 BRA 0x1C6
- 208: led5blue=1;
- 01C2 868C BSF LATD, 3, ACCESS
- 209: }else led5blue=0;
- 01C4 D002 BRA 0x1CA
- 01C6 968C BCF LATD, 3, ACCESS
- 01C8 D000 BRA 0x1CA
- 210:
- 211: if(anchodepulso<=duty6red){
- 01CA 503B MOVF anchodepulso, W, ACCESS
- 01CC 5C2F SUBWF 0x2F, W, ACCESS
- 01CE A0D8 BTFSS STATUS, 0, ACCESS
- 01D0 D002 BRA 0x1D6
- 212: led6red=1;
- 01D2 888B BSF LATC, 4, ACCESS
- 213: }else led6red=0;
- 01D4 D002 BRA 0x1DA
- 01D6 988B BCF LATC, 4, ACCESS
- 01D8 D000 BRA 0x1DA
- 214: if(anchodepulso<=duty6green){
- 01DA 503B MOVF anchodepulso, W, ACCESS
- 01DC 5C30 SUBWF 0x30, W, ACCESS
- 01DE A0D8 BTFSS STATUS, 0, ACCESS
- 01E0 D002 BRA 0x1E6
- 215: led6green=1;
- 01E2 8C8B BSF LATC, 6, ACCESS
- 216: }else led6green=0;
- 01E4 D002 BRA 0x1EA
- 01E6 9C8B BCF LATC, 6, ACCESS
- 01E8 D000 BRA 0x1EA
- 217: if(anchodepulso<=duty6blue){
- 01EA 503B MOVF anchodepulso, W, ACCESS
- 01EC 5C31 SUBWF 0x31, W, ACCESS
- 01EE A0D8 BTFSS STATUS, 0, ACCESS
- 01F0 D002 BRA 0x1F6
- 218: led6blue=1;
- 01F2 888C BSF LATD, 4, ACCESS
- 219: }else led6blue=0;
- 01F4 D002 BRA 0x1FA
- 01F6 988C BCF LATD, 4, ACCESS
- 01F8 D000 BRA 0x1FA
- 220:
- 221: if(anchodepulso<=duty7red){
- 01FA 503B MOVF anchodepulso, W, ACCESS
- 01FC 5C32 SUBWF 0x32, W, ACCESS
- 01FE A0D8 BTFSS STATUS, 0, ACCESS
- 0200 D002 BRA 0x206
- 222: led7red=1;
- 0202 8A8C BSF LATD, 5, ACCESS
- 223: }else led7red=0;
- 0204 D002 BRA 0x20A
- 0206 9A8C BCF LATD, 5, ACCESS
- 0208 D000 BRA 0x20A
- 224: if(anchodepulso<=duty7green){
- 020A 503B MOVF anchodepulso, W, ACCESS
- 020C 5C33 SUBWF 0x33, W, ACCESS
- 020E A0D8 BTFSS STATUS, 0, ACCESS
- 0210 D002 BRA 0x216
- 225: led7green=1;
- 0212 8C8C BSF LATD, 6, ACCESS
- 226: }else led7green=0;
- 0214 D002 BRA 0x21A
- 0216 9C8C BCF LATD, 6, ACCESS
- 0218 D000 BRA 0x21A
- 227: if(anchodepulso<=duty7blue){
- 021A 503B MOVF anchodepulso, W, ACCESS
- 021C 5C34 SUBWF 0x34, W, ACCESS
- 021E A0D8 BTFSS STATUS, 0, ACCESS
- 0220 D002 BRA 0x226
- 228: led7blue=1;
- 0222 8E8C BSF LATD, 7, ACCESS
- 229: }else led7blue=0;
- 0224 D002 BRA 0x22A
- 0226 9E8C BCF LATD, 7, ACCESS
- 0228 D000 BRA 0x22A
- 230:
- 231: if(anchodepulso<=duty8red){
- 022A 503B MOVF anchodepulso, W, ACCESS
- 022C 5C35 SUBWF 0x35, W, ACCESS
- 022E A0D8 BTFSS STATUS, 0, ACCESS
- 0230 D002 BRA 0x236
- 232: led8red=1;
- 0232 808A BSF LATB, 0, ACCESS
- 233: }else led8red=0;
- 0234 D002 BRA 0x23A
- 0236 908A BCF LATB, 0, ACCESS
- 0238 D000 BRA 0x23A
- 234: if(anchodepulso<=duty8green){
- 023A 503B MOVF anchodepulso, W, ACCESS
- 023C 5C36 SUBWF 0x36, W, ACCESS
- 023E A0D8 BTFSS STATUS, 0, ACCESS
- 0240 D002 BRA 0x246
- 235: led8green=1;
- 0242 828A BSF LATB, 1, ACCESS
- 236: }else led8green=0;
- 0244 D002 BRA 0x24A
- 0246 928A BCF LATB, 1, ACCESS
- 0248 D000 BRA 0x24A
- 237: if(anchodepulso<=duty8blue){
- 024A 503B MOVF anchodepulso, W, ACCESS
- 024C 5C37 SUBWF 0x37, W, ACCESS
- 024E A0D8 BTFSS STATUS, 0, ACCESS
- 0250 D002 BRA 0x256
- 238: led8blue=1;
- 0252 848A BSF LATB, 2, ACCESS
- 239: }else led8blue=0;
- 0254 D002 BRA 0x25A
- 0256 948A BCF LATB, 2, ACCESS
- 0258 D000 BRA 0x25A
- 240:
- 241: if(anchodepulso<=duty9red){
- 025A 503B MOVF anchodepulso, W, ACCESS
- 025C 5C38 SUBWF 0x38, W, ACCESS
- 025E A0D8 BTFSS STATUS, 0, ACCESS
- 0260 D002 BRA 0x266
- 242: led9red=1;
- 0262 868A BSF LATB, 3, ACCESS
- 243: }else led9red=0;
- 0264 D002 BRA 0x26A
- 0266 968A BCF LATB, 3, ACCESS
- 0268 D000 BRA 0x26A
- 244: if(anchodepulso<=duty9green){
- 026A 503B MOVF anchodepulso, W, ACCESS
- 026C 5C39 SUBWF 0x39, W, ACCESS
- 026E A0D8 BTFSS STATUS, 0, ACCESS
- 0270 D002 BRA 0x276
- 245: led9green=1;
- 0272 888A BSF LATB, 4, ACCESS
- 246: }else led9green=0;
- 0274 D002 BRA 0x27A
- 0276 988A BCF LATB, 4, ACCESS
- 0278 D000 BRA 0x27A
- 247: if(anchodepulso<=duty9blue){
- 027A 503B MOVF anchodepulso, W, ACCESS
- 027C 5C3A SUBWF 0x3A, W, ACCESS
- 027E A0D8 BTFSS STATUS, 0, ACCESS
- 0280 D002 BRA 0x286
- 248: led9blue=1;
- 0282 8A8A BSF LATB, 5, ACCESS
- 249: }else led9blue=0;
- 0284 D002 BRA 0x28A
- 0286 9A8A BCF LATB, 5, ACCESS
- 0288 D000 BRA 0x28A
- 250: if(anchodepulso==255){
- 251: anchodepulso==0;
- 252: }
- 253: INTCONbits.TMR0IF=0;
- 028A 94F2 BCF INTCON, 2, ACCESS
- 254: TMR0H = 0;
- 028C 0E00 MOVLW 0x0
- 028E 6ED7 MOVWF TMR0H, ACCESS
- 255: TMR0L= 255;
- 0290 68D6 SETF TMR0, ACCESS
- 0292 D000 BRA 0x294
- 256: }
- 257: INTCONbits.GIEH = 1; //IMPORTANTE HABILITARLAS PORQ SE DESHABILITAN CON INTERRUP
- 0294 8EF2 BSF INTCON, 7, ACCESS
- 258: }
- 0296 C01F MOVFF 0x1F, TABLAT
- 259:
- 260: void interrupt low_priority YourLowPriorityISRCode(){
- 0018 CFD8 MOVFF STATUS, 0x1
- 261:
- 262: INTCONbits.GIEL = 1;//IMPORTANTE HABILITARLAS PORQ SE DESHABILITAN CON INTERRUP
- 005C 8CF2 BSF INTCON, 6, ACCESS
- 263: }
- 0008 CFFA MOVFF PCLATH, 0x12
- 000A F012 NOP
- 000C CFFB MOVFF PCLATU, 0x13
- 000E F013 NOP
- 0010 CFE9 MOVFF FSR0, 0x14
- 0012 F014 NOP
- 0014 EF54 GOTO 0xA8
- 0016 F000 NOP
- 005E C011 MOVFF 0x11, TABLAT
- 264:
- 265:
- 266: void main(void) {
- 267:
- 268: OSCCONbits.IDLEN=0;
- 02D0 9ED3 BCF OSCCON, 7, ACCESS
- 269: OSCCONbits.IRCF =0b111; //oscilador interno de 16Mhz
- 02D2 88D3 BSF OSCCON, 4, ACCESS
- 02D4 8AD3 BSF OSCCON, 5, ACCESS
- 02D6 8CD3 BSF OSCCON, 6, ACCESS
- 270: while(OSCCONbits.OSTS); // sino esta corriendo con oscilador interno quedarse aca
- 02D8 D000 BRA 0x2DA
- 02DA A6D3 BTFSS OSCCON, 3, ACCESS
- 02DC D002 BRA 0x2E2
- 02DE D7FD BRA 0x2DA
- 271: while(!OSCCONbits.IOFS); // espera que frecuencia del clok sea estable
- 02E0 D000 BRA 0x2E2
- 02E2 A4D3 BTFSS OSCCON, 2, ACCESS
- 02E4 D7FE BRA 0x2E2
- 272: OSCCONbits.SCS = 0b11; // clock del sistema sea interno
- 02E6 0E03 MOVLW 0x3
- 02E8 12D3 IORWF OSCCON, F, ACCESS
- 273: OSCTUNEbits.INTSRC=1;
- 02EA 8E9B BSF OSCTUNE, 7, ACCESS
- 274: OSCTUNEbits.PLLEN= 1; //habilito PLL osea que en 16Mhz con PLL DE 4 --> Fosc= 64MHz
- 02EC 8C9B BSF OSCTUNE, 6, ACCESS
- 275: OSCTUNEbits.TUN= 0; //oscilador funcione calibrado de fabrica
- 02EE 909B BCF OSCTUNE, 0, ACCESS
- 02F0 929B BCF OSCTUNE, 1, ACCESS
- 02F2 949B BCF OSCTUNE, 2, ACCESS
- 02F4 969B BCF OSCTUNE, 3, ACCESS
- 02F6 989B BCF OSCTUNE, 4, ACCESS
- 02F8 9A9B BCF OSCTUNE, 5, ACCESS
- 276:
- 277: INTCONbits.TMR0IE=0;
- 02FA 9AF2 BCF INTCON, 5, ACCESS
- 278: INTCONbits.INT0IE = 0;
- 02FC 98F2 BCF INTCON, 4, ACCESS
- 279: INTCONbits.RBIE = 0;
- 02FE 96F2 BCF INTCON, 3, ACCESS
- 280: INTCONbits.PEIE_GIEL=1;
- 0300 8CF2 BSF INTCON, 6, ACCESS
- 281: INTCONbits.GIE_GIEH=1;
- 0302 8EF2 BSF INTCON, 7, ACCESS
- 282:
- 283: INTCON2bits.RBPU=0;
- 0304 9EF1 BCF INTCON2, 7, ACCESS
- 284: INTCON2bits.TMR0IP=0;
- 0306 94F1 BCF INTCON2, 2, ACCESS
- 285: INTCON2bits.RBIP=0;
- 0308 90F1 BCF INTCON2, 0, ACCESS
- 286:
- 287: INTCON3bits.INT2E=0;
- 030A 98F0 BCF INTCON3, 4, ACCESS
- 288: INTCON3bits.INT1E=0;
- 030C 96F0 BCF INTCON3, 3, ACCESS
- 289: INTCON3bits.INT1IP=0;
- 030E 9CF0 BCF INTCON3, 6, ACCESS
- 290: INTCON3bits.INT2IP=0;
- 0310 9EF0 BCF INTCON3, 7, ACCESS
- 291:
- 292: PIE1bits.ADIE=0;
- 0312 9C9D BCF PIE1, 6, ACCESS
- 293: PIE1bits.PSPIE=0;
- 0314 9E9D BCF PIE1, 7, ACCESS
- 294: PIE1bits.RCIE=0; //INT DEL EUSART
- 0316 9A9D BCF PIE1, 5, ACCESS
- 295: PIE1bits.TXIE=0; //INT DEL EUSART
- 0318 989D BCF PIE1, 4, ACCESS
- 296: PIE1bits.CCP1IE=0;
- 031A 949D BCF PIE1, 2, ACCESS
- 297: PIE1bits.TMR1IE=0;
- 031C 909D BCF PIE1, 0, ACCESS
- 298: PIE1bits.TMR2IE=0;
- 031E 929D BCF PIE1, 1, ACCESS
- 299:
- 300: PIE2bits.BCLIE=0;
- 0320 96A0 BCF PIE2, 3, ACCESS
- 301: PIE2bits.C1IE=0;
- 0322 9CA0 BCF PIE2, 6, ACCESS
- 302: PIE2bits.C2IE=0;
- 0324 9AA0 BCF PIE2, 5, ACCESS
- 303: PIE2bits.EEIE=0;
- 0326 98A0 BCF PIE2, 4, ACCESS
- 304: PIE2bits.HLVDIE=0;
- 0328 94A0 BCF PIE2, 2, ACCESS
- 305: PIE2bits.TMR3IE=0;
- 032A 92A0 BCF PIE2, 1, ACCESS
- 306: PIE2bits.CCP2IE=0;
- 032C 90A0 BCF PIE2, 0, ACCESS
- 307:
- 308: TRISB = 0b00000000; // 6 PWM DOS OCUPADOS POR PROGRAMACION RB6 Y RB7
- 032E 0E00 MOVLW 0x0
- 0330 6E93 MOVWF TRISB, ACCESS
- 309: TRISC = 0b10000000; // 6 PWM DOS OCUPADOS POR USART RC6 Y RC7
- 0332 0E80 MOVLW 0x80
- 0334 6E94 MOVWF TRISC, ACCESS
- 310: TRISD = 0b00000000; // 8 PWM
- 0336 0E00 MOVLW 0x0
- 0338 6E95 MOVWF TRISD, ACCESS
- 311: TRISE = 0b1000; // 3 PWM RE3 ES MCLR
- 033A 0E08 MOVLW 0x8
- 033C 6E96 MOVWF TRISE, ACCESS
- 312: TRISA = 0b00000011; // 4 PWM , SOBRAN 4 ADC RA0 RA1 RA2 Y RA3
- 033E 0E03 MOVLW 0x3
- 0340 6E92 MOVWF TRISA, ACCESS
- 313:
- 314: T0CONbits.T08BIT = 1;
- 0342 8CD5 BSF T0CON, 6, ACCESS
- 315: T0CONbits.T0CS=0;
- 0344 9AD5 BCF T0CON, 5, ACCESS
- 316: T0CONbits.PSA= 1; // SIN PRESCALER OSEA PRESCALER =1
- 0346 86D5 BSF T0CON, 3, ACCESS
- 317: TMR0L= 244; // desborda cada 75uS , cuando llega a 100 veces cumple un periodo de 13,333 KHz
- 0348 0EF4 MOVLW 0xF4
- 034A 6ED6 MOVWF TMR0, ACCESS
- 318: INTCONbits.TMR0IE=1;
- 034C 8AF2 BSF INTCON, 5, ACCESS
- 319:
- 320: while(1){
- 321:
- 322: }
- 034E D7FF BRA 0x34E
- 323: }
- 0018 CFD8 MOVFF STATUS, 0x1
- 001A F001 NOP
- 001C CFE8 MOVFF WREG, 0x2
- 001E F002 NOP
- 0020 CFE0 MOVFF BSR, 0x3
- 0022 F003 NOP
- 0024 CFFA MOVFF PCLATH, 0x4
- 0026 F004 NOP
- 0028 CFFB MOVFF PCLATU, 0x5
- 002A F005 NOP
- 002C CFE9 MOVFF FSR0, 0x6
- 002E F006 NOP
- 0030 CFEA MOVFF FSR0H, 0x7
- 0032 F007 NOP
- 0034 CFE1 MOVFF FSR1, 0x8
- 0036 F008 NOP
- 0038 CFE2 MOVFF FSR1H, 0x9
- 003A F009 NOP
- 003C CFD9 MOVFF FSR2, 0xA
- 003E F00A NOP
- 0040 CFDA MOVFF FSR2H, 0xB
- 0042 F00B NOP
- 0044 CFF3 MOVFF PROD, 0xC
- 0046 F00C NOP
- 0048 CFF4 MOVFF PRODH, 0xD
- 004A F00D NOP
- 004C CFF6 MOVFF TBLPTR, 0xE
- 004E F00E NOP
- 0050 CFF7 MOVFF TBLPTRH, 0xF
- 0052 F00F NOP
- 0054 CFF8 MOVFF TBLPTRU, 0x10
- 0056 F010 NOP
- 0058 CFF5 MOVFF TABLAT, 0x11
- 005A F011 NOP
- 0350 EF52 GOTO 0xA4
- 324:
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