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  1. /*
  2. * Copyright (C) 2010-2011 Freescale Semiconductor, Inc. All Rights Reserved.
  3. */
  4.  
  5. /*
  6. * This program is free software; you can redistribute it and/or modify
  7. * it under the terms of the GNU General Public License as published by
  8. * the Free Software Foundation; either version 2 of the License, or
  9. * (at your option) any later version.
  10.  
  11. * This program is distributed in the hope that it will be useful,
  12. * but WITHOUT ANY WARRANTY; without even the implied warranty of
  13. * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
  14. * GNU General Public License for more details.
  15.  
  16. * You should have received a copy of the GNU General Public License along
  17. * with this program; if not, write to the Free Software Foundation, Inc.,
  18. * 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA.
  19. */
  20.  
  21. #include <linux/types.h>
  22. #include <linux/sched.h>
  23. #include <linux/delay.h>
  24. #include <linux/pm.h>
  25. #include <linux/interrupt.h>
  26. #include <linux/irq.h>
  27. #include <linux/init.h>
  28. #include <linux/input.h>
  29. #include <linux/nodemask.h>
  30. #include <linux/clk.h>
  31. #include <linux/platform_device.h>
  32. #include <linux/fsl_devices.h>
  33. #include <linux/spi/spi.h>
  34. #include <linux/can/platform/flexcan.h>
  35.  
  36. #include <linux/spi/spi_gpio.h>
  37. #include <linux/spi/ads7846.h>
  38.  
  39. #include <linux/i2c.h>
  40. #include <linux/ata.h>
  41. #include <linux/mtd/mtd.h>
  42. #include <linux/mtd/map.h>
  43. #include <linux/mtd/partitions.h>
  44. #include <linux/regulator/consumer.h>
  45. #include <linux/pmic_external.h>
  46. #include <linux/pmic_status.h>
  47. #include <linux/ipu.h>
  48. #include <linux/mxcfb.h>
  49. #include <linux/pwm_backlight.h>
  50. #include <linux/fec.h>
  51. #include <linux/powerkey.h>
  52. #include <linux/ahci_platform.h>
  53. #include <linux/gpio_keys.h>
  54. #include <linux/mfd/da9052/da9052.h>
  55. #include <mach/common.h>
  56. #include <mach/hardware.h>
  57. #include <asm/irq.h>
  58. #include <asm/setup.h>
  59. #include <asm/mach-types.h>
  60. #include <asm/mach/arch.h>
  61. #include <asm/mach/time.h>
  62. #include <asm/mach/keypad.h>
  63. #include <asm/mach/flash.h>
  64. #include <mach/memory.h>
  65. #include <mach/gpio.h>
  66. #include <mach/mmc.h>
  67. #include <mach/mxc_dvfs.h>
  68. #include <mach/iomux-mx53.h>
  69. #include <mach/i2c.h>
  70. #include <mach/mxc_iim.h>
  71. #include <mach/check_fuse.h>
  72.  
  73. #include "crm_regs.h"
  74. #include "devices.h"
  75. #include "usb.h"
  76. #include "pmic.h"
  77.  
  78. /*!
  79. * @file mach-mx5/mx53_loco.c
  80. *
  81. * @brief This file contains MX53 loco board specific initialization routines.
  82. *
  83. * @ingroup MSL_MX53
  84. */
  85.  
  86. #define SD1_CD (0*32 + 7) /* GPIO_7 */
  87. #define SD2_CD (0*32 + 1) /* GPIO_1 */
  88.  
  89. #define FEC_RST (3*32 + 5) /* GPIO_4_5 */
  90.  
  91. //TS0 from LVDS0 or TFT connector
  92. #define TS0_PENIRQ_FROM_LVDS0
  93.  
  94. /* TS LVDS0 */
  95. #ifdef TS0_PENIRQ_FROM_LVDS0
  96. #define TS0_PENIRQ (0*32 + 9) /* GPIO_9 */
  97. #else
  98. #define TS0_PENIRQ (2*32 + 21) /* GPIO_3_21 */
  99. #endif
  100. #define TS0_CS (2*32 + 23) /* GPIO_3_23 */
  101. #define TS0_SCK (4*32 + 22) /* GPIO_5_22 */
  102. #define TS0_MOSI (2*32 + 18) /* GPIO_3_18 */
  103. #define TS0_MISO (2*32 + 17) /* GPIO_3_17 */
  104.  
  105. /* TS LVDS1 */
  106. #define TS1_PENIRQ (0*32 + 3) /* GPIO_3 */
  107. #define TS1_CS (4*32 + 29) /* GPIO_5_29 */
  108. #define TS1_SCK (4*32 + 26) /* GPIO_5_26 */
  109. #define TS1_MOSI (4*32 + 27) /* GPIO_5_27 */
  110. #define TS1_MISO (4*32 + 28) /* GPIO_5_28 */
  111.  
  112.  
  113. extern void pm_i2c_init(u32 base_addr);
  114. static u32 mx53_loco_mc34708_irq;
  115. static iomux_v3_cfg_t mx53_loco_pads[] = {
  116. /* CSI0 */
  117. MX53_PAD_CSI0_DAT12__IPU_CSI0_D_12,
  118. MX53_PAD_CSI0_DAT13__IPU_CSI0_D_13,
  119. MX53_PAD_CSI0_DAT14__IPU_CSI0_D_14,
  120. MX53_PAD_CSI0_DAT15__IPU_CSI0_D_15,
  121. MX53_PAD_CSI0_DAT16__IPU_CSI0_D_16,
  122. MX53_PAD_CSI0_DAT17__IPU_CSI0_D_17,
  123. MX53_PAD_CSI0_DAT18__IPU_CSI0_D_18,
  124. MX53_PAD_CSI0_DAT19__IPU_CSI0_D_19,
  125. MX53_PAD_CSI0_VSYNC__IPU_CSI0_VSYNC,
  126. MX53_PAD_CSI0_MCLK__IPU_CSI0_HSYNC,
  127. MX53_PAD_CSI0_PIXCLK__IPU_CSI0_PIXCLK,
  128.  
  129. /* FEC */
  130. MX53_PAD_FEC_MDC__FEC_MDC,
  131. MX53_PAD_FEC_MDIO__FEC_MDIO,
  132. MX53_PAD_FEC_REF_CLK__FEC_TX_CLK,
  133. MX53_PAD_FEC_RX_ER__FEC_RX_ER,
  134. MX53_PAD_FEC_CRS_DV__FEC_RX_DV,
  135. MX53_PAD_FEC_RXD1__FEC_RDATA_1,
  136. MX53_PAD_FEC_RXD0__FEC_RDATA_0,
  137. MX53_PAD_FEC_TX_EN__FEC_TX_EN,
  138. MX53_PAD_FEC_TXD1__FEC_TDATA_1,
  139. MX53_PAD_FEC_TXD0__FEC_TDATA_0,
  140. /* PHY CLK */
  141. // MX53_PAD_GPIO_5__CCM_CLKO,
  142. /* PHY RESET */
  143. MX53_PAD_GPIO_19__GPIO4_5,
  144.  
  145. /* CAN1 */
  146. MX53_PAD_PATA_INTRQ__CAN1_TXCAN,
  147. MX53_PAD_PATA_DIOR__CAN1_RXCAN,
  148.  
  149. /* CAN2 */
  150. MX53_PAD_PATA_RESET_B__CAN2_TXCAN,
  151. MX53_PAD_PATA_IORDY__CAN2_RXCAN,
  152.  
  153. /* AUDMUX5 */
  154. MX53_PAD_KEY_COL0__AUDMUX_AUD5_TXC,
  155. MX53_PAD_KEY_ROW0__AUDMUX_AUD5_TXD,
  156. MX53_PAD_KEY_COL1__AUDMUX_AUD5_TXFS,
  157. MX53_PAD_KEY_ROW1__AUDMUX_AUD5_RXD,
  158.  
  159. /* I2C2 */
  160. MX53_PAD_EIM_EB2__I2C2_SCL,
  161. MX53_PAD_KEY_ROW3__I2C2_SDA,
  162.  
  163. /* SD1 */
  164. MX53_PAD_SD1_CMD__ESDHC1_CMD,
  165. MX53_PAD_SD1_CLK__ESDHC1_CLK,
  166. MX53_PAD_SD1_DATA0__ESDHC1_DAT0,
  167. MX53_PAD_SD1_DATA1__ESDHC1_DAT1,
  168. MX53_PAD_SD1_DATA2__ESDHC1_DAT2,
  169. MX53_PAD_SD1_DATA3__ESDHC1_DAT3,
  170. /* SD1_CD */
  171. MX53_PAD_GPIO_7__GPIO1_7,
  172.  
  173. /* SD2 */
  174. MX53_PAD_SD2_DATA0__ESDHC2_DAT0,
  175. MX53_PAD_SD2_DATA1__ESDHC2_DAT1,
  176. MX53_PAD_SD2_DATA2__ESDHC2_DAT2,
  177. MX53_PAD_SD2_DATA3__ESDHC2_DAT3,
  178. MX53_PAD_SD2_CLK__ESDHC2_CLK,
  179. MX53_PAD_SD2_CMD__ESDHC2_CMD,
  180. /* SD2_CD */
  181. MX53_PAD_GPIO_1__GPIO1_1,
  182.  
  183. /* LVDS */
  184. MX53_PAD_LVDS0_TX3_P__LDB_LVDS0_TX3,
  185. MX53_PAD_LVDS0_CLK_P__LDB_LVDS0_CLK,
  186. MX53_PAD_LVDS0_TX2_P__LDB_LVDS0_TX2,
  187. MX53_PAD_LVDS0_TX1_P__LDB_LVDS0_TX1,
  188. MX53_PAD_LVDS0_TX0_P__LDB_LVDS0_TX0,
  189. MX53_PAD_LVDS1_TX3_P__LDB_LVDS1_TX3,
  190. MX53_PAD_LVDS1_TX2_P__LDB_LVDS1_TX2,
  191. MX53_PAD_LVDS1_CLK_P__LDB_LVDS1_CLK,
  192. MX53_PAD_LVDS1_TX1_P__LDB_LVDS1_TX1,
  193. MX53_PAD_LVDS1_TX0_P__LDB_LVDS1_TX0,
  194.  
  195. /* TS LVDS0 */
  196. #ifdef TS0_PENIRQ_FROM_LVDS0
  197. MX53_PAD_GPIO_9__GPIO1_9,
  198. #else
  199. MX53_PAD_EIM_D21__GPIO3_21,
  200. #endif
  201. MX53_PAD_EIM_D23__GPIO3_23,
  202. MX53_PAD_CSI0_DAT4__GPIO5_22,
  203. MX53_PAD_EIM_D18__GPIO3_18,
  204. MX53_PAD_EIM_D17__GPIO3_17,
  205.  
  206. /* TS LVDS1 */
  207. MX53_PAD_GPIO_3__GPIO1_3,
  208. MX53_PAD_CSI0_DAT11__GPIO5_29,
  209. MX53_PAD_CSI0_DAT8__GPIO5_26,
  210. MX53_PAD_CSI0_DAT9__GPIO5_27,
  211. MX53_PAD_CSI0_DAT10__GPIO5_28,
  212.  
  213. /* UART1 */
  214. MX53_PAD_PATA_DIOW__UART1_TXD_MUX,
  215. MX53_PAD_PATA_DMACK__UART1_RXD_MUX,
  216.  
  217. /* UART2 */
  218. MX53_PAD_PATA_DMARQ__UART2_TXD_MUX,
  219. MX53_PAD_PATA_BUFFER_EN__UART2_RXD_MUX,
  220.  
  221. /* UART3 */
  222. MX53_PAD_EIM_D24__UART3_TXD_MUX,
  223. MX53_PAD_EIM_D25__UART3_RXD_MUX,
  224.  
  225. /* DISPLAY */
  226. MX53_PAD_DI0_DISP_CLK__IPU_DI0_DISP_CLK,
  227. MX53_PAD_DI0_PIN15__IPU_DI0_PIN15,
  228. MX53_PAD_DI0_PIN2__IPU_DI0_PIN2,
  229. MX53_PAD_DI0_PIN3__IPU_DI0_PIN3,
  230. MX53_PAD_DISP0_DAT0__IPU_DISP0_DAT_0,
  231. MX53_PAD_DISP0_DAT1__IPU_DISP0_DAT_1,
  232. MX53_PAD_DISP0_DAT2__IPU_DISP0_DAT_2,
  233. MX53_PAD_DISP0_DAT3__IPU_DISP0_DAT_3,
  234. MX53_PAD_DISP0_DAT4__IPU_DISP0_DAT_4,
  235. MX53_PAD_DISP0_DAT5__IPU_DISP0_DAT_5,
  236. MX53_PAD_DISP0_DAT6__IPU_DISP0_DAT_6,
  237. MX53_PAD_DISP0_DAT7__IPU_DISP0_DAT_7,
  238. MX53_PAD_DISP0_DAT8__IPU_DISP0_DAT_8,
  239. MX53_PAD_DISP0_DAT9__IPU_DISP0_DAT_9,
  240. MX53_PAD_DISP0_DAT10__IPU_DISP0_DAT_10,
  241. MX53_PAD_DISP0_DAT11__IPU_DISP0_DAT_11,
  242. MX53_PAD_DISP0_DAT12__IPU_DISP0_DAT_12,
  243. MX53_PAD_DISP0_DAT13__IPU_DISP0_DAT_13,
  244. MX53_PAD_DISP0_DAT14__IPU_DISP0_DAT_14,
  245. MX53_PAD_DISP0_DAT15__IPU_DISP0_DAT_15,
  246. MX53_PAD_DISP0_DAT16__IPU_DISP0_DAT_16,
  247. MX53_PAD_DISP0_DAT17__IPU_DISP0_DAT_17,
  248. MX53_PAD_DISP0_DAT18__IPU_DISP0_DAT_18,
  249. MX53_PAD_DISP0_DAT19__IPU_DISP0_DAT_19,
  250. MX53_PAD_DISP0_DAT20__IPU_DISP0_DAT_20,
  251. MX53_PAD_DISP0_DAT21__IPU_DISP0_DAT_21,
  252. MX53_PAD_DISP0_DAT22__IPU_DISP0_DAT_22,
  253. MX53_PAD_DISP0_DAT23__IPU_DISP0_DAT_23,
  254.  
  255. /* Audio CLK*/
  256. MX53_PAD_GPIO_0__CCM_SSI_EXT1_CLK,
  257. };
  258.  
  259. static iomux_v3_cfg_t mx53_nand_pads[] = {
  260. MX53_PAD_NANDF_CLE__EMI_NANDF_CLE,
  261. MX53_PAD_NANDF_ALE__EMI_NANDF_ALE,
  262. MX53_PAD_NANDF_WP_B__EMI_NANDF_WP_B,
  263. MX53_PAD_NANDF_WE_B__EMI_NANDF_WE_B,
  264. MX53_PAD_NANDF_RE_B__EMI_NANDF_RE_B,
  265. MX53_PAD_NANDF_RB0__EMI_NANDF_RB_0,
  266. MX53_PAD_NANDF_CS0__EMI_NANDF_CS_0,
  267. MX53_PAD_NANDF_CS1__EMI_NANDF_CS_1,
  268. MX53_PAD_NANDF_CS2__EMI_NANDF_CS_2,
  269. MX53_PAD_NANDF_CS3__EMI_NANDF_CS_3,
  270. MX53_PAD_EIM_DA0__EMI_NAND_WEIM_DA_0,
  271. MX53_PAD_EIM_DA1__EMI_NAND_WEIM_DA_1,
  272. MX53_PAD_EIM_DA2__EMI_NAND_WEIM_DA_2,
  273. MX53_PAD_EIM_DA3__EMI_NAND_WEIM_DA_3,
  274. MX53_PAD_EIM_DA4__EMI_NAND_WEIM_DA_4,
  275. MX53_PAD_EIM_DA5__EMI_NAND_WEIM_DA_5,
  276. MX53_PAD_EIM_DA6__EMI_NAND_WEIM_DA_6,
  277. MX53_PAD_EIM_DA7__EMI_NAND_WEIM_DA_7,
  278. };
  279.  
  280. #if defined(CONFIG_TOUCHSCREEN_ADS7846)
  281. struct spi_gpio_platform_data sk_spi0_gpio_platform_data = {
  282. .sck = TS0_SCK,
  283. .mosi = TS0_MOSI,
  284. .miso = TS0_MISO,
  285. .num_chipselect = 1,
  286. };
  287.  
  288. struct spi_gpio_platform_data sk_spi1_gpio_platform_data = {
  289. .sck = TS1_SCK,
  290. .mosi = TS1_MOSI,
  291. .miso = TS1_MISO,
  292. .num_chipselect = 1,
  293. };
  294.  
  295. struct platform_device sk_spi0_gpio_device = {
  296. .name = "spi_gpio",
  297. .id = 0,
  298. .dev = {
  299. .platform_data = &sk_spi0_gpio_platform_data,
  300. },
  301. };
  302.  
  303. struct platform_device sk_spi1_gpio_device = {
  304. .name = "spi_gpio",
  305. .id = 1,
  306. .dev = {
  307. .platform_data = &sk_spi1_gpio_platform_data,
  308. },
  309. };
  310.  
  311. static int ads7846_pendown_state0(void)
  312. {
  313. /* Touchscreen PENIRQ */
  314. return !gpio_get_value(TS0_PENIRQ);
  315. }
  316.  
  317. static int ads7846_pendown_state1(void)
  318. {
  319. /* Touchscreen PENIRQ */
  320. return !gpio_get_value(TS1_PENIRQ);
  321. }
  322.  
  323. static struct ads7846_platform_data ads_info0 = {
  324. .model = 7843,
  325. .x_min = 150,
  326. .x_max = 3830,
  327. .y_min = 190,
  328. .y_max = 3830,
  329. .vref_delay_usecs = 100,
  330. .x_plate_ohms = 450,
  331. .y_plate_ohms = 250,
  332. .pressure_max = 15000,
  333. .debounce_max = 5,
  334. .debounce_rep = 0,
  335. .debounce_tol = 10,
  336. .get_pendown_state = ads7846_pendown_state0,
  337. };
  338.  
  339. static struct ads7846_platform_data ads_info1 = {
  340. .model = 7843,
  341. .x_min = 150,
  342. .x_max = 3830,
  343. .y_min = 190,
  344. .y_max = 3830,
  345. .vref_delay_usecs = 100,
  346. .x_plate_ohms = 450,
  347. .y_plate_ohms = 250,
  348. .pressure_max = 15000,
  349. .debounce_max = 5,
  350. .debounce_rep = 0,
  351. .debounce_tol = 10,
  352. .get_pendown_state = ads7846_pendown_state1,
  353. };
  354.  
  355.  
  356. static struct spi_board_info mxc_ts_device[] __initdata = {
  357. {
  358. .modalias = "ads7846",
  359. .max_speed_hz = 1000 * 1000, /* max spi clock (SCK) speed in HZ */
  360. .bus_num = 0,
  361. .chip_select = 0,
  362. .controller_data = (void *)TS0_CS,
  363. .platform_data = &ads_info0,
  364. .irq = gpio_to_irq(TS0_PENIRQ),
  365. },
  366. {
  367. .modalias = "ads7846",
  368. .max_speed_hz = 1000 * 1000, /* max spi clock (SCK) speed in HZ */
  369. .bus_num = 1,
  370. .chip_select = 0,
  371. .controller_data = (void *)TS1_CS,
  372. .platform_data = &ads_info1,
  373. .irq = gpio_to_irq(TS1_PENIRQ),
  374. },
  375.  
  376. #if 0
  377. {
  378. .modalias = "spidev",
  379. .max_speed_hz = 1000 * 1000, /* max spi clock (SCK) speed in HZ */
  380. .bus_num = 0,
  381. .chip_select = 0,
  382. .controller_data = (void *)TS_CS,
  383. },
  384. #endif
  385. };
  386. #endif
  387.  
  388.  
  389.  
  390.  
  391. static struct fb_videomode video_modes[] = {
  392. // {
  393. /* 1920x1080 for HDMI, Attention!!! must be turn on only DI0 !!! */
  394. // "SK-1920x1080-HDMI", 60, 1920, 1080, 7692, 100, 40, 30, 3, 10, 2, 0,
  395. // FB_SYNC_CLK_LAT_FALL,
  396. // FB_VMODE_NONINTERLACED,
  397. // FB_MODE_IS_DETAILED,},
  398. // {
  399. /* 1024x768 for TFT parallel channel and HDMI */
  400. // "SK-1024x768-HDMI", 60, 1024, 768, 15385, 220, 40, 21, 7, 60, 10,
  401. // FB_SYNC_CLK_LAT_FALL,
  402. // FB_VMODE_NONINTERLACED,
  403. // 0,},
  404. // {
  405. // /* 800x480 for LVDS channels */
  406. // "SK-800x480-LVDS", 60, 800, 480, 15385, 220, 40, 21, 7, 60, 10, 0,
  407. // FB_VMODE_NONINTERLACED,
  408. // 0,},
  409. // {
  410. /* 800x480 for TFT parallel channel and HDMI */
  411. // "SK-800x480-TFT", 60, 800, 480, 15385 * 2, 220, 40, 21, 7, 60, 10,
  412. // FB_SYNC_CLK_LAT_FALL,
  413. // FB_VMODE_NONINTERLACED,
  414. // 0,},
  415. // {
  416. /* 480x272 for SK-MI0430FT_plug */
  417. // "SK-480x272", 30, 480, 272, /*100000*/ 150000, 40, 60, 10, 10, 20, 10,
  418. // FB_SYNC_CLK_LAT_FALL,
  419. // FB_VMODE_NONINTERLACED,
  420. // 0,},
  421. {
  422. /* 800x480 @ 57 Hz , pixel clk @ 27MHz */
  423. "SK-800x480-TFT", 30, 800, 480, /*74074*/ /*59700*/ 37037,/*Left*/ 68,/*Right*/ 180,/*Upper*/ 23,/*Lower*/ 10, 20, 10,
  424. 0, //FB_SYNC_CLK_LAT_FALL,
  425. FB_VMODE_NONINTERLACED,
  426. 0,},
  427. // {
  428. // /* 800x480 @ 60 Hz , pixel clk @ 32MHz */
  429. // "SEIKO-WVGA", 60, 800, 480, 29850, 89, 164, 23, 10, 10, 10,
  430. // FB_SYNC_CLK_LAT_FALL,
  431. // FB_VMODE_NONINTERLACED,
  432. // 0,},
  433. // {
  434. /* 1600x1200 @ 60 Hz 162M pixel clk*/
  435. // "UXGA", 60, 1600, 1200, 6172,
  436. // 304, 64,
  437. // 1, 46,
  438. // 192, 3,
  439. // FB_SYNC_HOR_HIGH_ACT|FB_SYNC_VERT_HIGH_ACT,
  440. // FB_VMODE_NONINTERLACED,
  441. // 0,},
  442. };
  443.  
  444. static struct platform_pwm_backlight_data mxc_pwm_backlight_data = {
  445. .pwm_id = 1,
  446. .max_brightness = 255,
  447. .dft_brightness = 128,
  448. .pwm_period_ns = 50000,
  449. };
  450.  
  451. static void flexcan_xcvr_enable(int enable)
  452. {
  453.  
  454. }
  455.  
  456. static struct flexcan_platform_data flexcan0_data = {
  457. .transceiver_switch = flexcan_xcvr_enable
  458. };
  459.  
  460. static struct flexcan_platform_data flexcan1_data = {
  461. .transceiver_switch = flexcan_xcvr_enable
  462. };
  463.  
  464. extern void mx5_ipu_reset(void);
  465. static struct mxc_ipu_config mxc_ipu_data = {
  466. .rev = 3,
  467. .reset = mx5_ipu_reset,
  468. };
  469.  
  470. extern void mx5_vpu_reset(void);
  471. static struct mxc_vpu_platform_data mxc_vpu_data = {
  472. .iram_enable = true,
  473. .iram_size = 0x14000,
  474. .reset = mx5_vpu_reset,
  475. };
  476.  
  477. static inline void mx53_loco_fec_init(void)
  478. {
  479. struct clk *cko1_clk;
  480. struct clk *pll2_sw_clk;
  481. int rate;
  482. int ret;
  483.  
  484. /* cko1_clk = clk_get(NULL, "cko1");
  485. if (IS_ERR(cko1_clk)) {
  486. printk(KERN_INFO "Error: can't find cko1_clk\n");
  487. return;
  488. }
  489.  
  490. pll2_sw_clk = clk_get(NULL, "pll2");
  491. if (IS_ERR(pll2_sw_clk)) {
  492. printk(KERN_INFO "Error: can't find pll2_sw_clk\n");
  493. return;
  494. }
  495.  
  496. clk_set_parent(cko1_clk, pll2_sw_clk);
  497.  
  498. rate = clk_round_rate(cko1_clk, 50000000);
  499. if (rate != 50000000) {
  500. printk(KERN_INFO "Error: FEC PHY freq %d out of range\n", rate);
  501. clk_put(cko1_clk);
  502. return;
  503. } else
  504. printk(KERN_INFO "FEC PHY freq %d\n", rate);
  505.  
  506. clk_set_rate(cko1_clk, rate);
  507. clk_enable(cko1_clk);
  508. */
  509. /* reset FEC PHY */
  510. ret = gpio_request(FEC_RST, "fec-phy-reset");
  511. if (ret) {
  512. pr_err("failed to get GPIO FEC_PHY_RST: %d\n", ret);
  513. return;
  514. }
  515. gpio_direction_output(FEC_RST, 0);
  516. msleep(1);
  517. gpio_set_value(FEC_RST, 1);
  518. }
  519.  
  520. static struct fec_platform_data fec_data = {
  521. .phy = PHY_INTERFACE_MODE_RMII,
  522. };
  523.  
  524. static struct mxc_dvfs_platform_data dvfs_core_data = {
  525. .clk1_id = "cpu_clk",
  526. .clk2_id = "gpc_dvfs_clk",
  527. .gpc_cntr_offset = MXC_GPC_CNTR_OFFSET,
  528. .gpc_vcr_offset = MXC_GPC_VCR_OFFSET,
  529. .ccm_cdcr_offset = MXC_CCM_CDCR_OFFSET,
  530. .ccm_cacrr_offset = MXC_CCM_CACRR_OFFSET,
  531. .ccm_cdhipr_offset = MXC_CCM_CDHIPR_OFFSET,
  532. .prediv_mask = 0x1F800,
  533. .prediv_offset = 11,
  534. .prediv_val = 3,
  535. .div3ck_mask = 0xE0000000,
  536. .div3ck_offset = 29,
  537. .div3ck_val = 2,
  538. .emac_val = 0x08,
  539. .upthr_val = 25,
  540. .dnthr_val = 9,
  541. .pncthr_val = 33,
  542. .upcnt_val = 10,
  543. .dncnt_val = 10,
  544. .delay_time = 30,
  545. };
  546.  
  547. static struct mxc_bus_freq_platform_data bus_freq_data;
  548.  
  549. static struct tve_platform_data tve_data = {
  550. .boot_enable = MXC_TVE_VGA,
  551. };
  552.  
  553. static struct ldb_platform_data ldb_data = {
  554. .ext_ref = 1,
  555. .boot_enable = MXC_LDBDI0 | MXC_LDBDI1,
  556. };
  557.  
  558. static void mxc_iim_enable_fuse(void)
  559. {
  560. u32 reg;
  561.  
  562. if (!ccm_base)
  563. return;
  564.  
  565. /* enable fuse blown */
  566. reg = readl(ccm_base + 0x64);
  567. reg |= 0x10;
  568. writel(reg, ccm_base + 0x64);
  569. }
  570.  
  571. static void mxc_iim_disable_fuse(void)
  572. {
  573. u32 reg;
  574.  
  575. if (!ccm_base)
  576. return;
  577. /* enable fuse blown */
  578. reg = readl(ccm_base + 0x64);
  579. reg &= ~0x10;
  580. writel(reg, ccm_base + 0x64);
  581. }
  582.  
  583. static struct mxc_iim_data iim_data = {
  584. .bank_start = MXC_IIM_MX53_BANK_START_ADDR,
  585. .bank_end = MXC_IIM_MX53_BANK_END_ADDR,
  586. .enable_fuse = mxc_iim_enable_fuse,
  587. .disable_fuse = mxc_iim_disable_fuse,
  588. };
  589.  
  590. static struct resource mxcfb_resources[] = {
  591. [0] = {
  592. .flags = IORESOURCE_MEM,
  593. },
  594. };
  595.  
  596. static struct mxc_fb_platform_data fb_data[] = {
  597. {
  598. .interface_pix_fmt = IPU_PIX_FMT_RGB24,
  599. .mode_str = "SK-800x480-LVDS",
  600. .mode = video_modes,
  601. .num_modes = ARRAY_SIZE(video_modes),
  602. },
  603. {
  604. .interface_pix_fmt = IPU_PIX_FMT_RGB24,
  605. .mode_str = "SK-800x480-LVDS",
  606. .mode = video_modes,
  607. .num_modes = ARRAY_SIZE(video_modes),
  608. },
  609. };
  610.  
  611. extern int primary_di;
  612. static int __init mxc_init_fb(void)
  613. {
  614. primary_di = 0;
  615.  
  616. if (primary_di) {
  617. printk(KERN_INFO "DI1 is primary\n");
  618. /* DI1 -> DP-BG channel: */
  619. mxc_fb_devices[1].num_resources = ARRAY_SIZE(mxcfb_resources);
  620. mxc_fb_devices[1].resource = mxcfb_resources;
  621. mxc_register_device(&mxc_fb_devices[1], &fb_data[1]);
  622.  
  623. /* DI0 -> DC channel: */
  624. mxc_register_device(&mxc_fb_devices[0], &fb_data[0]);
  625. } else {
  626. printk(KERN_INFO "DI0 is primary\n");
  627.  
  628. /* DI0 -> DP-BG channel: */
  629. mxc_fb_devices[0].num_resources = ARRAY_SIZE(mxcfb_resources);
  630. mxc_fb_devices[0].resource = mxcfb_resources;
  631. mxc_register_device(&mxc_fb_devices[0], &fb_data[0]);
  632.  
  633. /* DI1 -> DC channel: */
  634. mxc_register_device(&mxc_fb_devices[1], &fb_data[1]);
  635. }
  636.  
  637. /*
  638. * DI0/1 DP-FG channel:
  639. */
  640. mxc_register_device(&mxc_fb_devices[2], NULL);
  641.  
  642. return 0;
  643. }
  644. device_initcall(mxc_init_fb);
  645.  
  646. static struct mxc_tvin_platform_data adv7180_data = {
  647. .dvddio_reg = NULL,
  648. .dvdd_reg = NULL,
  649. .avdd_reg = NULL,
  650. .pvdd_reg = NULL,
  651. .pwdn = NULL,
  652. .reset = NULL,
  653. .cvbs = 1,
  654. };
  655.  
  656.  
  657. static struct imxi2c_platform_data mxci2c_data = {
  658. .bitrate = 100000,
  659. };
  660.  
  661.  
  662. static struct mxc_camera_platform_data camera_data = {
  663. .analog_regulator = "DA9052_LDO7",
  664. .core_regulator = "DA9052_LDO9",
  665. .mclk = 24000000,
  666. .csi = 0,
  667. };
  668.  
  669. static struct i2c_board_info mxc_i2c1_board_info[] __initdata = {
  670. {
  671. .type = "adv7180",
  672. .addr = 0x21,
  673. .platform_data = (void *)&adv7180_data,
  674. },
  675. {
  676. .type = "ov5642",
  677. .addr = 0x3c,
  678. .platform_data = (void *)&camera_data,
  679. },
  680. {
  681. .type = "tlv320aic23",
  682. .addr = 0x1a,
  683. },
  684. {
  685. .type = "ds1338",
  686. .addr = 0x68,
  687. },
  688. };
  689.  
  690. static unsigned int sdhc_get_card_det_status(struct device *dev)
  691. {
  692. int ret;
  693.  
  694. if (to_platform_device(dev)->id == 0)
  695. ret = gpio_get_value(SD1_CD);
  696. else
  697. ret = gpio_get_value(SD2_CD);
  698.  
  699. return ret;
  700.  
  701. }
  702.  
  703. static struct mxc_mmc_platform_data mmc1_data = {
  704. .ocr_mask = MMC_VDD_27_28 | MMC_VDD_28_29 | MMC_VDD_29_30
  705. | MMC_VDD_31_32,
  706. .caps = MMC_CAP_4_BIT_DATA,
  707. .min_clk = 400000,
  708. .max_clk = 50000000,
  709. .card_inserted_state = 0,
  710. .status = sdhc_get_card_det_status,
  711. .clock_mmc = "esdhc_clk",
  712. .power_mmc = NULL,
  713. };
  714.  
  715. static struct mxc_mmc_platform_data mmc2_data = {
  716. .ocr_mask = MMC_VDD_27_28 | MMC_VDD_28_29 | MMC_VDD_29_30
  717. | MMC_VDD_31_32,
  718. .caps = MMC_CAP_4_BIT_DATA,
  719. .min_clk = 400000,
  720. .max_clk = 50000000,
  721. .card_inserted_state = 0,
  722. .status = sdhc_get_card_det_status,
  723. .clock_mmc = "esdhc_clk",
  724. };
  725.  
  726. static int mxc_sgtl5000_init(void);
  727.  
  728. static struct mxc_audio_platform_data sgtl5000_data = {
  729. .ssi_num = 1,
  730. .src_port = 2,
  731. .ext_port = 5,
  732. .init = mxc_sgtl5000_init,
  733. .ext_ram_rx = 1,
  734. };
  735.  
  736. static int mxc_sgtl5000_init(void)
  737. {
  738. struct clk *ssi_ext1;
  739. int rate;
  740.  
  741. ssi_ext1 = clk_get(NULL, "ssi_ext1_clk");
  742. if (IS_ERR(ssi_ext1))
  743. return -1;
  744.  
  745. rate = clk_round_rate(ssi_ext1, 12000000);
  746. if (rate < 8000000 || rate > 27000000) {
  747. printk(KERN_ERR "Error: SGTL5000 mclk freq %d out of range!\n",
  748. rate);
  749. clk_put(ssi_ext1);
  750. return -1;
  751. }
  752.  
  753. clk_set_rate(ssi_ext1, rate);
  754. clk_enable(ssi_ext1);
  755. sgtl5000_data.sysclk = rate;
  756.  
  757. return 0;
  758. }
  759.  
  760. static struct platform_device mxc_sgtl5000_device = {
  761. .name = "imx-3stack-sgtl5000",
  762. };
  763.  
  764. /* NAND Flash Partitions */
  765. #ifdef CONFIG_MTD_PARTITIONS
  766. static struct mtd_partition nand_flash_partitions[] = {
  767. /* MX53 ROM require the boot FCB/DBBT support which need
  768. * more space to store such info on NAND boot partition.
  769. * 16M should cover all kind of NAND boot support on MX53.
  770. */
  771. {
  772. .name = "bootloader and kernel",
  773. .offset = 0,
  774. .size = 32 * 1024 * 1024},
  775. {
  776. .name = "nand.rootfs",
  777. .offset = MTDPART_OFS_APPEND,
  778. .size = MTDPART_SIZ_FULL},
  779. };
  780. #endif
  781.  
  782. static int nand_init(void)
  783. {
  784. u32 i, reg;
  785. void __iomem *base;
  786.  
  787. #define M4IF_GENP_WEIM_MM_MASK 0x00000001
  788. #define WEIM_GCR2_MUX16_BYP_GRANT_MASK 0x00001000
  789.  
  790. base = ioremap(MX53_BASE_ADDR(M4IF_BASE_ADDR), SZ_4K);
  791. reg = __raw_readl(base + 0xc);
  792. reg &= ~M4IF_GENP_WEIM_MM_MASK;
  793. __raw_writel(reg, base + 0xc);
  794.  
  795. iounmap(base);
  796.  
  797. base = ioremap(MX53_BASE_ADDR(WEIM_BASE_ADDR), SZ_4K);
  798. for (i = 0x4; i < 0x94; i += 0x18) {
  799. reg = __raw_readl((u32)base + i);
  800. reg &= ~WEIM_GCR2_MUX16_BYP_GRANT_MASK;
  801. __raw_writel(reg, (u32)base + i);
  802. }
  803.  
  804. iounmap(base);
  805.  
  806. return 0;
  807. }
  808.  
  809. static struct flash_platform_data mxc_nand_data = {
  810. #ifdef CONFIG_MTD_PARTITIONS
  811. .parts = nand_flash_partitions,
  812. .nr_parts = ARRAY_SIZE(nand_flash_partitions),
  813. #endif
  814. .width = 1,
  815. .init = nand_init,
  816. };
  817.  
  818. static struct mxc_asrc_platform_data mxc_asrc_data = {
  819. .channel_bits = 4,
  820. .clk_map_ver = 2,
  821. };
  822.  
  823. static struct mxc_spdif_platform_data mxc_spdif_data = {
  824. .spdif_tx = 1,
  825. .spdif_rx = 0,
  826. .spdif_clk_44100 = -1, /* Souce from CKIH1 for 44.1K */
  827. /* Source from CCM spdif_clk (24M) for 48k and 32k
  828. * It's not accurate
  829. */
  830. .spdif_clk_48000 = 1,
  831. .spdif_clkid = 0,
  832. .spdif_clk = NULL, /* spdif bus clk */
  833. };
  834.  
  835. static struct mxc_audio_platform_data spdif_audio_data = {
  836. .ext_ram_tx = 1,
  837. };
  838.  
  839. static struct platform_device mxc_spdif_audio_device = {
  840. .name = "imx-spdif-audio-device",
  841. };
  842.  
  843. static void mx53_gpio_usbotg_driver_vbus(bool on)
  844. {
  845.  
  846. }
  847.  
  848. static void mx53_loco_usbh1_vbus(bool on)
  849. {
  850.  
  851. }
  852.  
  853. #if defined(CONFIG_KEYBOARD_GPIO) || defined(CONFIG_KEYBOARD_GPIO_MODULE)
  854. #define GPIO_BUTTON(gpio_num, ev_code, act_low, descr, wake) \
  855. { \
  856. .gpio = gpio_num, \
  857. .type = EV_KEY, \
  858. .code = ev_code, \
  859. .active_low = act_low, \
  860. .desc = "btn " descr, \
  861. .wakeup = wake, \
  862. }
  863.  
  864. static struct gpio_keys_button loco_buttons[] = {
  865. GPIO_BUTTON(MX53_nONKEY, KEY_POWER, 1, "power", 0),
  866. GPIO_BUTTON(USER_UI1, KEY_VOLUMEUP, 1, "volume-up", 0),
  867. GPIO_BUTTON(USER_UI2, KEY_VOLUMEDOWN, 1, "volume-down", 0),
  868. };
  869.  
  870. static struct gpio_keys_platform_data loco_button_data = {
  871. .buttons = loco_buttons,
  872. .nbuttons = ARRAY_SIZE(loco_buttons),
  873. };
  874.  
  875. static struct platform_device loco_button_device = {
  876. .name = "gpio-keys",
  877. .id = -1,
  878. .num_resources = 0,
  879. .dev = {
  880. .platform_data = &loco_button_data,
  881. }
  882. };
  883.  
  884. static void __init loco_add_device_buttons(void)
  885. {
  886. platform_device_register(&loco_button_device);
  887. }
  888. #else
  889. static void __init loco_add_device_buttons(void) {}
  890. #endif
  891.  
  892. #if 0
  893. static void mxc_register_powerkey(pwrkey_callback pk_cb)
  894. {
  895. pmic_event_callback_t power_key_event;
  896.  
  897. power_key_event.param = (void *)1;
  898. power_key_event.func = (void *)pk_cb;
  899. pmic_event_subscribe(EVENT_PWRONI, power_key_event);
  900. }
  901.  
  902. static int mxc_pwrkey_getstatus(int id)
  903. {
  904. int sense;
  905.  
  906. pmic_read_reg(REG_INT_SENSE1, &sense, 0xffffffff);
  907. if (sense & (1 << 3))
  908. return 0;
  909.  
  910. return 1;
  911. }
  912.  
  913. static struct power_key_platform_data pwrkey_data = {
  914. .key_value = KEY_F4,
  915. .register_pwrkey = mxc_register_powerkey,
  916. .get_key_status = mxc_pwrkey_getstatus,
  917. };
  918. #endif
  919. /*!
  920. * Board specific fixup function. It is called by \b setup_arch() in
  921. * setup.c file very early on during kernel starts. It allows the user to
  922. * statically fill in the proper values for the passed-in parameters. None of
  923. * the parameters is used currently.
  924. *
  925. * @param desc pointer to \b struct \b machine_desc
  926. * @param tags pointer to \b struct \b tag
  927. * @param cmdline pointer to the command line
  928. * @param mi pointer to \b struct \b meminfo
  929. */
  930. static void __init fixup_mxc_board(struct machine_desc *desc, struct tag *tags,
  931. char **cmdline, struct meminfo *mi)
  932. {
  933. struct tag *t;
  934. struct tag *mem_tag = 0;
  935. int total_mem = SZ_256M;
  936. int left_mem = 0;
  937. int gpu_mem = 0; //SZ_128M;
  938. int fb_mem = SZ_32M;
  939. char *str;
  940.  
  941. mxc_set_cpu_type(MXC_CPU_MX53);
  942.  
  943. for_each_tag(mem_tag, tags) {
  944. if (mem_tag->hdr.tag == ATAG_MEM) {
  945. total_mem = mem_tag->u.mem.size;
  946. break;
  947. }
  948. }
  949.  
  950. for_each_tag(t, tags) {
  951. if (t->hdr.tag == ATAG_CMDLINE) {
  952. str = t->u.cmdline.cmdline;
  953. str = strstr(str, "mem=");
  954. if (str != NULL) {
  955. str += 4;
  956. left_mem = memparse(str, &str);
  957. }
  958.  
  959. str = t->u.cmdline.cmdline;
  960. str = strstr(str, "gpu_nommu");
  961. if (str != NULL)
  962. gpu_data.enable_mmu = 0;
  963.  
  964. str = t->u.cmdline.cmdline;
  965. str = strstr(str, "gpu_memory=");
  966. if (str != NULL) {
  967. str += 11;
  968. gpu_mem = memparse(str, &str);
  969. }
  970.  
  971. break;
  972. }
  973. }
  974.  
  975. if (gpu_data.enable_mmu)
  976. gpu_mem = 0;
  977.  
  978. if (left_mem == 0 || left_mem > total_mem)
  979. left_mem = total_mem - gpu_mem - fb_mem;
  980.  
  981. if (mem_tag) {
  982. fb_mem = total_mem - left_mem - gpu_mem;
  983. if (fb_mem < 0) {
  984. gpu_mem = total_mem - left_mem;
  985. fb_mem = 0;
  986. }
  987. mem_tag->u.mem.size = left_mem;
  988.  
  989. /*reserve memory for gpu*/
  990. if (!gpu_data.enable_mmu) {
  991. gpu_device.resource[5].start =
  992. mem_tag->u.mem.start + left_mem;
  993. gpu_device.resource[5].end =
  994. gpu_device.resource[5].start + gpu_mem - 1;
  995. }
  996. #if defined(CONFIG_FB_MXC_SYNC_PANEL) || \
  997. defined(CONFIG_FB_MXC_SYNC_PANEL_MODULE)
  998. if (fb_mem) {
  999. mxcfb_resources[0].start =
  1000. gpu_data.enable_mmu ?
  1001. mem_tag->u.mem.start + left_mem :
  1002. gpu_device.resource[5].end + 1;
  1003. mxcfb_resources[0].end =
  1004. mxcfb_resources[0].start + fb_mem - 1;
  1005. } else {
  1006. mxcfb_resources[0].start = 0;
  1007. mxcfb_resources[0].end = 0;
  1008. }
  1009. #endif
  1010. }
  1011. }
  1012.  
  1013. static void __init mx53_loco_io_init(void)
  1014. {
  1015. mxc_iomux_v3_setup_multiple_pads(mx53_loco_pads,
  1016. ARRAY_SIZE(mx53_loco_pads));
  1017.  
  1018. mxc_iomux_v3_setup_multiple_pads(mx53_nand_pads,
  1019. ARRAY_SIZE(mx53_nand_pads));
  1020.  
  1021. /* SD1 */
  1022. gpio_request(SD1_CD, "sd1-cd");
  1023. gpio_direction_input(SD1_CD);
  1024.  
  1025. /* SD2 */
  1026. gpio_request(SD2_CD, "sd2-cd");
  1027. gpio_direction_input(SD2_CD);
  1028.  
  1029. #if defined(CONFIG_TOUCHSCREEN_ADS7846)
  1030. gpio_request(TS0_PENIRQ, "ts0-penirq");
  1031. gpio_direction_input(TS0_PENIRQ);
  1032.  
  1033. gpio_request(TS1_PENIRQ, "ts1-penirq");
  1034. gpio_direction_input(TS1_PENIRQ);
  1035. #endif
  1036.  
  1037. #if 0
  1038. /* LCD panel power enable */
  1039. gpio_request(DISP0_POWER_EN, "disp0-power-en");
  1040. gpio_direction_output(DISP0_POWER_EN, 1);
  1041. #endif
  1042. }
  1043.  
  1044. /*!
  1045. * Board specific initialization.
  1046. */
  1047. static void __init mxc_board_init(void)
  1048. {
  1049.  
  1050. // iomux_v3_cfg_t mc34708_int = MX53_PAD_CSI0_DAT12__GPIO5_30;
  1051. // iomux_v3_cfg_t da9052_csi0_d12;
  1052.  
  1053. mx53_loco_fec_init();
  1054.  
  1055. mxc_ipu_data.di_clk[0] = clk_get(NULL, "ipu_di0_clk");
  1056. mxc_ipu_data.di_clk[1] = clk_get(NULL, "ipu_di1_clk");
  1057. mxc_ipu_data.csi_clk[0] = clk_get(NULL, "ssi_ext1_clk");
  1058. mxc_spdif_data.spdif_core_clk = clk_get(NULL, "spdif_xtal_clk");
  1059. clk_put(mxc_spdif_data.spdif_core_clk);
  1060.  
  1061. mxcsdhc1_device.resource[2].start = gpio_to_irq(SD1_CD);
  1062. mxcsdhc1_device.resource[2].end = gpio_to_irq(SD1_CD);
  1063. mxcsdhc2_device.resource[2].start = gpio_to_irq(SD2_CD);
  1064. mxcsdhc2_device.resource[2].end = gpio_to_irq(SD2_CD);
  1065.  
  1066. mxc_cpu_common_init();
  1067. mx53_loco_io_init();
  1068.  
  1069. mxc_register_device(&mxc_dma_device, NULL);
  1070. mxc_register_device(&mxc_wdt_device, NULL);
  1071. mxc_register_device(&mxci2c_devices[0], &mxci2c_data);
  1072. mxc_register_device(&mxci2c_devices[1], &mxci2c_data);
  1073. mxc_register_device(&mxci2c_devices[2], &mxci2c_data);
  1074.  
  1075. #if 0
  1076. if (board_is_mx53_loco_mc34708()) {
  1077. /* set pmic INT gpio pin */
  1078. if (board_is_rev(BOARD_REV_2)) {/*Board rev A*/
  1079. mc34708_int = MX53_PAD_CSI0_DAT12__GPIO5_30;
  1080. mx53_loco_mc34708_irq = MX53_LOCO_MC34708_IRQ_REVA;
  1081. } else if (board_is_rev(BOARD_REV_4)) {/*Board rev B*/
  1082. mc34708_int = MX53_PAD_CSI0_DAT5__GPIO5_23;
  1083. mx53_loco_mc34708_irq = MX53_LOCO_MC34708_IRQ_REVB;
  1084. }
  1085. mxc_iomux_v3_setup_pad(mc34708_int);
  1086. gpio_request(mx53_loco_mc34708_irq, "pmic-int");
  1087. gpio_direction_input(mx53_loco_mc34708_irq);
  1088. mx53_loco_init_mc34708(mx53_loco_mc34708_irq);
  1089. dvfs_core_data.reg_id = "SW1A";
  1090. tve_data.dac_reg = "VDAC";
  1091. bus_freq_data.gp_reg_id = "SW1A";
  1092. bus_freq_data.lp_reg_id = "SW2";
  1093. mxc_register_device(&mxc_powerkey_device, &pwrkey_data);
  1094. }
  1095. else {
  1096. da9052_csi0_d12 = MX53_PAD_CSI0_DAT12__IPU_CSI0_D_12;
  1097. mxc_iomux_v3_setup_pad(da9052_csi0_d12);
  1098. mx53_loco_init_da9052();
  1099. dvfs_core_data.reg_id = "DA9052_BUCK_CORE";
  1100. tve_data.dac_reg = "DA9052_LDO7";
  1101. bus_freq_data.gp_reg_id = "DA9052_BUCK_CORE";
  1102. bus_freq_data.lp_reg_id = "DA9052_BUCK_PRO";
  1103. }
  1104. #endif
  1105.  
  1106. mxc_register_device(&mxc_rtc_device, NULL);
  1107. mxc_register_device(&mxc_ipu_device, &mxc_ipu_data);
  1108. mxc_register_device(&mxc_ldb_device, &ldb_data);
  1109. // mxc_register_device(&mxc_tve_device, &tve_data);
  1110. if (!mxc_fuse_get_vpu_status())
  1111. mxc_register_device(&mxcvpu_device, &mxc_vpu_data);
  1112. if (!mxc_fuse_get_gpu_status())
  1113. mxc_register_device(&gpu_device, &gpu_data);
  1114. mxc_register_device(&mxcscc_device, NULL);
  1115. // mxc_register_device(&pm_device, &loco_pm_data);
  1116. mxc_register_device(&mxc_dvfs_core_device, &dvfs_core_data);
  1117. mxc_register_device(&busfreq_device, &bus_freq_data);
  1118.  
  1119. mxc_register_device(&mxc_iim_device, &iim_data);
  1120.  
  1121. mxc_register_device(&mxc_flexcan0_device, &flexcan0_data);
  1122. mxc_register_device(&mxc_flexcan1_device, &flexcan1_data);
  1123.  
  1124. // mxc_register_device(&mxc_pwm2_device, NULL);
  1125. // mxc_register_device(&mxc_pwm1_backlight_device, &mxc_pwm_backlight_data);
  1126. mxc_register_device(&mxcsdhc1_device, &mmc1_data);
  1127. mxc_register_device(&mxcsdhc2_device, &mmc2_data);
  1128.  
  1129. mxc_register_device(&mxc_ssi1_device, NULL);
  1130. mxc_register_device(&mxc_ssi2_device, NULL);
  1131. mxc_register_device(&mxc_alsa_spdif_device, &mxc_spdif_data);
  1132. mxc_register_device(&ahci_fsl_device, &sata_data);
  1133. mxc_register_device(&imx_ahci_device_hwmon, NULL);
  1134. mxc_register_device(&mxc_fec_device, &fec_data);
  1135. mxc_register_device(&mxc_ptp_device, NULL);
  1136. /* ASRC is only available for MX53 TO2.0 */
  1137. if (mx53_revision() >= IMX_CHIP_REVISION_2_0) {
  1138. mxc_asrc_data.asrc_core_clk = clk_get(NULL, "asrc_clk");
  1139. clk_put(mxc_asrc_data.asrc_core_clk);
  1140. mxc_asrc_data.asrc_audio_clk = clk_get(NULL, "asrc_serial_clk");
  1141. clk_put(mxc_asrc_data.asrc_audio_clk);
  1142. mxc_register_device(&mxc_asrc_device, &mxc_asrc_data);
  1143. }
  1144.  
  1145. #if defined(CONFIG_TOUCHSCREEN_ADS7846)
  1146. // spi_register_board_info(mxc_ts_device,
  1147. // ARRAY_SIZE(mxc_ts_device));
  1148. // platform_device_register(&sk_spi_gpio_device);
  1149. spi_register_board_info(mxc_ts_device, ARRAY_SIZE(mxc_ts_device));
  1150. platform_device_register(&sk_spi0_gpio_device);
  1151. platform_device_register(&sk_spi1_gpio_device);
  1152. #endif
  1153. // i2c_register_board_info(0, mxc_i2c0_board_info,
  1154. // ARRAY_SIZE(mxc_i2c0_board_info));
  1155. i2c_register_board_info(1, mxc_i2c1_board_info,
  1156. ARRAY_SIZE(mxc_i2c1_board_info));
  1157. // i2c_register_board_info(2, mxc_i2c2_board_info,
  1158. // ARRAY_SIZE(mxc_i2c2_board_info));
  1159.  
  1160. sgtl5000_data.ext_ram_clk = clk_get(NULL, "emi_fast_clk");
  1161. clk_put(sgtl5000_data.ext_ram_clk);
  1162. mxc_register_device(&mxc_sgtl5000_device, &sgtl5000_data);
  1163.  
  1164. spdif_audio_data.ext_ram_clk = clk_get(NULL, "emi_fast_clk");
  1165. clk_put(spdif_audio_data.ext_ram_clk);
  1166. mxc_register_device(&mxc_spdif_audio_device, &spdif_audio_data);
  1167.  
  1168. mx5_set_otghost_vbus_func(mx53_gpio_usbotg_driver_vbus);
  1169. mx5_usb_dr_init();
  1170. mx5_set_host1_vbus_func(mx53_loco_usbh1_vbus);
  1171. mx5_usbh1_init();
  1172. mxc_register_device(&mxc_nandv2_mtd_device, &mxc_nand_data);
  1173. mxc_register_device(&mxc_v4l2_device, NULL);
  1174. mxc_register_device(&mxc_v4l2out_device, NULL);
  1175. // loco_add_device_buttons();
  1176. // pm_power_off = da9053_power_off;
  1177. // pm_i2c_init(I2C1_BASE_ADDR - MX53_OFFSET);
  1178. }
  1179.  
  1180. static void __init mx53_loco_timer_init(void)
  1181. {
  1182. struct clk *uart_clk;
  1183.  
  1184. mx53_clocks_init(32768, 24000000, 0, 0);
  1185.  
  1186. uart_clk = clk_get_sys("mxcintuart.0", NULL);
  1187. early_console_setup(MX53_BASE_ADDR(UART1_BASE_ADDR), uart_clk);
  1188. }
  1189.  
  1190. static struct sys_timer mxc_timer = {
  1191. .init = mx53_loco_timer_init,
  1192. };
  1193.  
  1194. /*
  1195. * The following uses standard kernel macros define in arch.h in order to
  1196. * initialize __mach_desc_MX53_LOCO data structure.
  1197. */
  1198. MACHINE_START(MX53_LOCO, "Freescale MX53 LOCO Board")
  1199. /* Maintainer: Freescale Semiconductor, Inc. */
  1200. .fixup = fixup_mxc_board,
  1201. .map_io = mx5_map_io,
  1202. .init_irq = mx5_init_irq,
  1203. .init_machine = mxc_board_init,
  1204. .timer = &mxc_timer,
  1205. MACHINE_END
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