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  1. /*
  2. * sama5d2.dtsi - Device Tree Include file for SAMA5D2 family SoC
  3. *
  4. * Copyright (C) 2015 Atmel,
  5. * 2015 Ludovic Desroches <ludovic.desroches@atmel.com>
  6. *
  7. * This file is dual-licensed: you can use it either under the terms
  8. * of the GPL or the X11 license, at your option. Note that this dual
  9. * licensing only applies to this file, and not this project as a
  10. * whole.
  11. *
  12. * a) This file is free software; you can redistribute it and/or
  13. * modify it under the terms of the GNU General Public License as
  14. * published by the Free Software Foundation; either version 2 of the
  15. * License, or (at your option) any later version.
  16. *
  17. * This file is distributed in the hope that it will be useful,
  18. * but WITHOUT ANY WARRANTY; without even the implied warranty of
  19. * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
  20. * GNU General Public License for more details.
  21. *
  22. * Or, alternatively,
  23. *
  24. * b) Permission is hereby granted, free of charge, to any person
  25. * obtaining a copy of this software and associated documentation
  26. * files (the "Software"), to deal in the Software without
  27. * restriction, including without limitation the rights to use,
  28. * copy, modify, merge, publish, distribute, sublicense, and/or
  29. * sell copies of the Software, and to permit persons to whom the
  30. * Software is furnished to do so, subject to the following
  31. * conditions:
  32. *
  33. * The above copyright notice and this permission notice shall be
  34. * included in all copies or substantial portions of the Software.
  35. *
  36. * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
  37. * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
  38. * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
  39. * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT
  40. * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
  41. * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
  42. * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
  43. * OTHER DEALINGS IN THE SOFTWARE.
  44. */
  45.  
  46. #include "skeleton.dtsi"
  47. #include <dt-bindings/dma/at91.h>
  48. #include <dt-bindings/interrupt-controller/irq.h>
  49. #include <dt-bindings/clock/at91.h>
  50.  
  51. / {
  52. model = "Atmel SAMA5D2 family SoC";
  53. compatible = "atmel,sama5d2";
  54. interrupt-parent = <&aic>;
  55.  
  56. aliases {
  57. serial0 = &uart1;
  58. serial1 = &uart2;
  59. serial2 = &uart3;
  60. tcb0 = &tcb0;
  61. tcb1 = &tcb1;
  62. i2s0 = &i2s0;
  63. i2s1 = &i2s1;
  64. };
  65.  
  66. cpus {
  67. #address-cells = <1>;
  68. #size-cells = <0>;
  69.  
  70. cpu@0 {
  71. device_type = "cpu";
  72. compatible = "arm,cortex-a5";
  73. reg = <0>;
  74. next-level-cache = <&L2>;
  75. };
  76. };
  77.  
  78. memory {
  79. reg = <0x20000000 0x20000000>;
  80. };
  81.  
  82. clocks {
  83. slow_xtal: slow_xtal {
  84. compatible = "fixed-clock";
  85. #clock-cells = <0>;
  86. clock-frequency = <0>;
  87. };
  88.  
  89. main_xtal: main_xtal {
  90. compatible = "fixed-clock";
  91. #clock-cells = <0>;
  92. clock-frequency = <0>;
  93. };
  94. };
  95.  
  96. ns_sram: sram@00200000 {
  97. compatible = "mmio-sram";
  98. reg = <0x00200000 0x20000>;
  99. };
  100.  
  101. ahb {
  102. compatible = "simple-bus";
  103. #address-cells = <1>;
  104. #size-cells = <1>;
  105. ranges;
  106.  
  107. usb0: gadget@00300000 {
  108. #address-cells = <1>;
  109. #size-cells = <0>;
  110. compatible = "atmel,sama5d3-udc";
  111. reg = <0x00300000 0x100000
  112. 0xfc02c000 0x400>;
  113. interrupts = <42 IRQ_TYPE_LEVEL_HIGH 2>;
  114. clocks = <&udphs_clk>, <&utmi>;
  115. clock-names = "pclk", "hclk";
  116. status = "disabled";
  117.  
  118. ep0 {
  119. reg = <0>;
  120. atmel,fifo-size = <64>;
  121. atmel,nb-banks = <1>;
  122. };
  123.  
  124. ep1 {
  125. reg = <1>;
  126. atmel,fifo-size = <1024>;
  127. atmel,nb-banks = <3>;
  128. atmel,can-dma;
  129. atmel,can-isoc;
  130. };
  131.  
  132. ep2 {
  133. reg = <2>;
  134. atmel,fifo-size = <1024>;
  135. atmel,nb-banks = <3>;
  136. atmel,can-dma;
  137. atmel,can-isoc;
  138. };
  139.  
  140. ep3 {
  141. reg = <3>;
  142. atmel,fifo-size = <1024>;
  143. atmel,nb-banks = <2>;
  144. atmel,can-dma;
  145. atmel,can-isoc;
  146. };
  147.  
  148. ep4 {
  149. reg = <4>;
  150. atmel,fifo-size = <1024>;
  151. atmel,nb-banks = <2>;
  152. atmel,can-dma;
  153. atmel,can-isoc;
  154. };
  155.  
  156. ep5 {
  157. reg = <5>;
  158. atmel,fifo-size = <1024>;
  159. atmel,nb-banks = <2>;
  160. atmel,can-dma;
  161. atmel,can-isoc;
  162. };
  163.  
  164. ep6 {
  165. reg = <6>;
  166. atmel,fifo-size = <1024>;
  167. atmel,nb-banks = <2>;
  168. atmel,can-dma;
  169. atmel,can-isoc;
  170. };
  171.  
  172. ep7 {
  173. reg = <7>;
  174. atmel,fifo-size = <1024>;
  175. atmel,nb-banks = <2>;
  176. atmel,can-dma;
  177. atmel,can-isoc;
  178. };
  179.  
  180. ep8 {
  181. reg = <8>;
  182. atmel,fifo-size = <1024>;
  183. atmel,nb-banks = <2>;
  184. atmel,can-isoc;
  185. };
  186.  
  187. ep9 {
  188. reg = <9>;
  189. atmel,fifo-size = <1024>;
  190. atmel,nb-banks = <2>;
  191. atmel,can-isoc;
  192. };
  193.  
  194. ep10 {
  195. reg = <10>;
  196. atmel,fifo-size = <1024>;
  197. atmel,nb-banks = <2>;
  198. atmel,can-isoc;
  199. };
  200.  
  201. ep11 {
  202. reg = <11>;
  203. atmel,fifo-size = <1024>;
  204. atmel,nb-banks = <2>;
  205. atmel,can-isoc;
  206. };
  207.  
  208. ep12 {
  209. reg = <12>;
  210. atmel,fifo-size = <1024>;
  211. atmel,nb-banks = <2>;
  212. atmel,can-isoc;
  213. };
  214.  
  215. ep13 {
  216. reg = <13>;
  217. atmel,fifo-size = <1024>;
  218. atmel,nb-banks = <2>;
  219. atmel,can-isoc;
  220. };
  221.  
  222. ep14 {
  223. reg = <14>;
  224. atmel,fifo-size = <1024>;
  225. atmel,nb-banks = <2>;
  226. atmel,can-isoc;
  227. };
  228.  
  229. ep15 {
  230. reg = <15>;
  231. atmel,fifo-size = <1024>;
  232. atmel,nb-banks = <2>;
  233. atmel,can-isoc;
  234. };
  235. };
  236.  
  237. usb1: ohci@00400000 {
  238. compatible = "atmel,at91rm9200-ohci", "usb-ohci";
  239. reg = <0x00400000 0x100000>;
  240. interrupts = <41 IRQ_TYPE_LEVEL_HIGH 2>;
  241. clocks = <&uhphs_clk>, <&uhphs_clk>, <&uhpck>;
  242. clock-names = "ohci_clk", "hclk", "uhpck";
  243. status = "disabled";
  244. };
  245.  
  246. usb2: ehci@00500000 {
  247. compatible = "atmel,at91sam9g45-ehci", "usb-ehci";
  248. reg = <0x00500000 0x100000>;
  249. interrupts = <41 IRQ_TYPE_LEVEL_HIGH 2>;
  250. clocks = <&utmi>, <&uhphs_clk>;
  251. clock-names = "usb_clk", "ehci_clk";
  252. status = "disabled";
  253. };
  254.  
  255. L2: cache-controller@00a00000 {
  256. compatible = "arm,pl310-cache";
  257. reg = <0x00a00000 0x1000>;
  258. interrupts = <63 IRQ_TYPE_LEVEL_HIGH 4>;
  259. cache-unified;
  260. cache-level = <2>;
  261. };
  262.  
  263. nand0: nand@80000000 {
  264. compatible = "atmel,sama5d2-nand";
  265. #address-cells = <1>;
  266. #size-cells = <1>;
  267. ranges;
  268. reg = < /* EBI CS3 */
  269. 0x80000000 0x08000000
  270. /* SMC PMECC regs */
  271. 0xf8014070 0x00000490
  272. /* SMC PMECC Error Location regs */
  273. 0xf8014500 0x00000200
  274. /* ROM Galois tables */
  275. 0x00040000 0x00018000
  276. >;
  277. interrupts = <17 IRQ_TYPE_LEVEL_HIGH 6>;
  278. atmel,nand-addr-offset = <21>;
  279. atmel,nand-cmd-offset = <22>;
  280. atmel,nand-has-dma;
  281. atmel,has-pmecc;
  282. atmel,pmecc-cap = <4>; /* Correctable ECC bits, can be 2,4,8,12,24 bits */
  283. atmel,pmecc-sector-size = <512>; /* Sector size in bytes, can be 512, 1024 */
  284. atmel,pmecc-lookup-table-offset = <0x0 0x8000>;
  285. status = "disabled";
  286.  
  287. /*nfc@c0000000 {
  288. compatible = "atmel,sama5d3-nfc";
  289. #address-cells = <1>;
  290. #size-cells = <1>;
  291. reg = <
  292. 0xc0000000 0x08000000
  293.  
  294. 0xf8014000 0x00000070
  295.  
  296. 0x00100000 0x00100000
  297. >;
  298. clocks = <&hsmc_clk>;
  299. atmel,write-by-sram;
  300. };*/
  301. };
  302.  
  303. sdmmc0: sdio-host@a0000000 {
  304. compatible = "atmel,sama5d2-sdhci";
  305. reg = <0xa0000000 0x300>;
  306. interrupts = <31 IRQ_TYPE_LEVEL_HIGH 0>;
  307. clocks = <&sdmmc0_hclk>, <&sdmmc0_gclk>, <&main>;
  308. clock-names = "hclock", "multclk", "baseclk";
  309. status = "disabled";
  310. };
  311.  
  312. sdmmc1: sdio-host@b0000000 {
  313. compatible = "atmel,sama5d2-sdhci";
  314. reg = <0xb0000000 0x300>;
  315. interrupts = <32 IRQ_TYPE_LEVEL_HIGH 0>;
  316. clocks = <&sdmmc1_hclk>, <&sdmmc1_gclk>, <&main>;
  317. clock-names = "hclock", "multclk", "baseclk";
  318. status = "disabled";
  319. };
  320.  
  321. apb {
  322. compatible = "simple-bus";
  323. #address-cells = <1>;
  324. #size-cells = <1>;
  325. ranges;
  326.  
  327. hlcdc: hlcdc@f0000000 {
  328. compatible = "atmel,sama5d2-hlcdc";
  329. reg = <0xf0000000 0x2000>;
  330. interrupts = <45 IRQ_TYPE_LEVEL_HIGH 0>;
  331. clocks = <&lcdc_clk>, <&lcdck>, <&clk32k>;
  332. clock-names = "periph_clk","sys_clk", "slow_clk";
  333. status = "disabled";
  334.  
  335. hlcdc-display-controller {
  336. compatible = "atmel,hlcdc-display-controller";
  337. #address-cells = <1>;
  338. #size-cells = <0>;
  339.  
  340. port@0 {
  341. #address-cells = <1>;
  342. #size-cells = <0>;
  343. reg = <0>;
  344. };
  345. };
  346.  
  347. hlcdc_pwm: hlcdc-pwm {
  348. compatible = "atmel,hlcdc-pwm";
  349. #pwm-cells = <3>;
  350. };
  351. };
  352.  
  353. ramc0: ramc@f000c000 {
  354. compatible = "atmel,sama5d3-ddramc";
  355. reg = <0xf000c000 0x200>;
  356. clocks = <&ddrck>, <&mpddr_clk>;
  357. clock-names = "ddrck", "mpddr";
  358. };
  359.  
  360. dma0: dma-controller@f0010000 {
  361. compatible = "atmel,sama5d4-dma";
  362. reg = <0xf0010000 0x1000>;
  363. interrupts = <6 IRQ_TYPE_LEVEL_HIGH 0>;
  364. #dma-cells = <1>;
  365. clocks = <&dma0_clk>;
  366. clock-names = "dma_clk";
  367. };
  368.  
  369. pmc: pmc@f0014000 {
  370. compatible = "atmel,sama5d2-pmc", "syscon";
  371. reg = <0xf0014000 0x160>;
  372. interrupts = <74 IRQ_TYPE_LEVEL_HIGH 7>;
  373. interrupt-controller;
  374. #address-cells = <1>;
  375. #size-cells = <0>;
  376. #interrupt-cells = <1>;
  377.  
  378. main_rc_osc: main_rc_osc {
  379. compatible = "atmel,at91sam9x5-clk-main-rc-osc";
  380. #clock-cells = <0>;
  381. interrupt-parent = <&pmc>;
  382. interrupts = <AT91_PMC_MOSCRCS>;
  383. clock-frequency = <12000000>;
  384. clock-accuracy = <100000000>;
  385. };
  386.  
  387. main_osc: main_osc {
  388. compatible = "atmel,at91rm9200-clk-main-osc";
  389. #clock-cells = <0>;
  390. interrupt-parent = <&pmc>;
  391. interrupts = <AT91_PMC_MOSCS>;
  392. clocks = <&main_xtal>;
  393. };
  394.  
  395. main: mainck {
  396. compatible = "atmel,at91sam9x5-clk-main";
  397. #clock-cells = <0>;
  398. interrupt-parent = <&pmc>;
  399. interrupts = <AT91_PMC_MOSCSELS>;
  400. clocks = <&main_rc_osc &main_osc>;
  401. };
  402.  
  403. plla: pllack {
  404. compatible = "atmel,sama5d3-clk-pll";
  405. #clock-cells = <0>;
  406. interrupt-parent = <&pmc>;
  407. interrupts = <AT91_PMC_LOCKA>;
  408. clocks = <&main>;
  409. reg = <0>;
  410. atmel,clk-input-range = <12000000 12000000>;
  411. #atmel,pll-clk-output-range-cells = <4>;
  412. atmel,pll-clk-output-ranges = <600000000 1200000000 0 0>;
  413. };
  414.  
  415. plladiv: plladivck {
  416. compatible = "atmel,at91sam9x5-clk-plldiv";
  417. #clock-cells = <0>;
  418. clocks = <&plla>;
  419. };
  420.  
  421. audio_pll_frac: audiopll_fracck {
  422. compatible = "atmel,sama5d2-clk-audio-pll-frac";
  423. #clock-cells = <0>;
  424. clocks = <&main>;
  425. };
  426.  
  427. audio_pll_pad: audiopll_padck {
  428. compatible = "atmel,sama5d2-clk-audio-pll-pad";
  429. #clock-cells = <0>;
  430. clocks = <&audio_pll_frac>;
  431. };
  432.  
  433. audio_pll_pmc: audiopll_pmcck {
  434. compatible = "atmel,sama5d2-clk-audio-pll-pmc";
  435. #clock-cells = <0>;
  436. clocks = <&audio_pll_frac>;
  437. };
  438.  
  439. utmi: utmick {
  440. compatible = "atmel,at91sam9x5-clk-utmi";
  441. #clock-cells = <0>;
  442. interrupt-parent = <&pmc>;
  443. interrupts = <AT91_PMC_LOCKU>;
  444. clocks = <&main>;
  445. };
  446.  
  447. mck: masterck {
  448. compatible = "atmel,at91sam9x5-clk-master";
  449. #clock-cells = <0>;
  450. interrupt-parent = <&pmc>;
  451. interrupts = <AT91_PMC_MCKRDY>;
  452. clocks = <&clk32k>, <&main>, <&plladiv>, <&utmi>;
  453. atmel,clk-output-range = <124000000 166000000>;
  454. atmel,clk-divisors = <1 2 4 3>;
  455. };
  456.  
  457. h32ck: h32mxck {
  458. #clock-cells = <0>;
  459. compatible = "atmel,sama5d4-clk-h32mx";
  460. clocks = <&mck>;
  461. };
  462.  
  463. usb: usbck {
  464. compatible = "atmel,at91sam9x5-clk-usb";
  465. #clock-cells = <0>;
  466. clocks = <&plladiv>, <&utmi>;
  467. };
  468.  
  469. prog: progck {
  470. compatible = "atmel,at91sam9x5-clk-programmable";
  471. #address-cells = <1>;
  472. #size-cells = <0>;
  473. interrupt-parent = <&pmc>;
  474. clocks = <&clk32k>, <&main>, <&plladiv>, <&utmi>, <&mck>;
  475.  
  476. prog0: prog0 {
  477. #clock-cells = <0>;
  478. reg = <0>;
  479. interrupts = <AT91_PMC_PCKRDY(0)>;
  480. };
  481.  
  482. prog1: prog1 {
  483. #clock-cells = <0>;
  484. reg = <1>;
  485. interrupts = <AT91_PMC_PCKRDY(1)>;
  486. };
  487.  
  488. prog2: prog2 {
  489. #clock-cells = <0>;
  490. reg = <2>;
  491. interrupts = <AT91_PMC_PCKRDY(2)>;
  492. };
  493. };
  494.  
  495. systemck {
  496. compatible = "atmel,at91rm9200-clk-system";
  497. #address-cells = <1>;
  498. #size-cells = <0>;
  499.  
  500. ddrck: ddrck {
  501. #clock-cells = <0>;
  502. reg = <2>;
  503. clocks = <&mck>;
  504. };
  505.  
  506. lcdck: lcdck {
  507. #clock-cells = <0>;
  508. reg = <3>;
  509. clocks = <&mck>;
  510. };
  511.  
  512. uhpck: uhpck {
  513. #clock-cells = <0>;
  514. reg = <6>;
  515. clocks = <&usb>;
  516. };
  517.  
  518. udpck: udpck {
  519. #clock-cells = <0>;
  520. reg = <7>;
  521. clocks = <&usb>;
  522. };
  523.  
  524. pck0: pck0 {
  525. #clock-cells = <0>;
  526. reg = <8>;
  527. clocks = <&prog0>;
  528. };
  529.  
  530. pck1: pck1 {
  531. #clock-cells = <0>;
  532. reg = <9>;
  533. clocks = <&prog1>;
  534. };
  535.  
  536. pck2: pck2 {
  537. #clock-cells = <0>;
  538. reg = <10>;
  539. clocks = <&prog2>;
  540. };
  541.  
  542. iscck: iscck {
  543. #clock-cells = <0>;
  544. reg = <18>;
  545. clocks = <&mck>;
  546. };
  547. };
  548.  
  549. periph32ck {
  550. compatible = "atmel,at91sam9x5-clk-peripheral";
  551. #address-cells = <1>;
  552. #size-cells = <0>;
  553. clocks = <&h32ck>;
  554.  
  555. macb0_clk: macb0_clk {
  556. #clock-cells = <0>;
  557. reg = <5>;
  558. atmel,clk-output-range = <0 83000000>;
  559. };
  560.  
  561. tdes_clk: tdes_clk {
  562. #clock-cells = <0>;
  563. reg = <11>;
  564. atmel,clk-output-range = <0 83000000>;
  565. };
  566.  
  567. matrix1_clk: matrix1_clk {
  568. #clock-cells = <0>;
  569. reg = <14>;
  570. };
  571.  
  572. hsmc_clk: hsmc_clk {
  573. #clock-cells = <0>;
  574. reg = <17>;
  575. };
  576.  
  577. pioA_clk: pioA_clk {
  578. #clock-cells = <0>;
  579. reg = <18>;
  580. atmel,clk-output-range = <0 83000000>;
  581. };
  582.  
  583. flx0_clk: flx0_clk {
  584. #clock-cells = <0>;
  585. reg = <19>;
  586. atmel,clk-output-range = <0 83000000>;
  587. };
  588.  
  589. flx1_clk: flx1_clk {
  590. #clock-cells = <0>;
  591. reg = <20>;
  592. atmel,clk-output-range = <0 83000000>;
  593. };
  594.  
  595. flx2_clk: flx2_clk {
  596. #clock-cells = <0>;
  597. reg = <21>;
  598. atmel,clk-output-range = <0 83000000>;
  599. };
  600.  
  601. flx3_clk: flx3_clk {
  602. #clock-cells = <0>;
  603. reg = <22>;
  604. atmel,clk-output-range = <0 83000000>;
  605. };
  606.  
  607. flx4_clk: flx4_clk {
  608. #clock-cells = <0>;
  609. reg = <23>;
  610. atmel,clk-output-range = <0 83000000>;
  611. };
  612.  
  613. uart0_clk: uart0_clk {
  614. #clock-cells = <0>;
  615. reg = <24>;
  616. atmel,clk-output-range = <0 83000000>;
  617. };
  618.  
  619. uart1_clk: uart1_clk {
  620. #clock-cells = <0>;
  621. reg = <25>;
  622. atmel,clk-output-range = <0 83000000>;
  623. };
  624.  
  625. uart2_clk: uart2_clk {
  626. #clock-cells = <0>;
  627. reg = <26>;
  628. atmel,clk-output-range = <0 83000000>;
  629. };
  630.  
  631. uart3_clk: uart3_clk {
  632. #clock-cells = <0>;
  633. reg = <27>;
  634. atmel,clk-output-range = <0 83000000>;
  635. };
  636.  
  637. uart4_clk: uart4_clk {
  638. #clock-cells = <0>;
  639. reg = <28>;
  640. atmel,clk-output-range = <0 83000000>;
  641. };
  642.  
  643. twi0_clk: twi0_clk {
  644. reg = <29>;
  645. #clock-cells = <0>;
  646. atmel,clk-output-range = <0 83000000>;
  647. };
  648.  
  649. twi1_clk: twi1_clk {
  650. #clock-cells = <0>;
  651. reg = <30>;
  652. atmel,clk-output-range = <0 83000000>;
  653. };
  654.  
  655. spi0_clk: spi0_clk {
  656. #clock-cells = <0>;
  657. reg = <33>;
  658. atmel,clk-output-range = <0 83000000>;
  659. };
  660.  
  661. spi1_clk: spi1_clk {
  662. #clock-cells = <0>;
  663. reg = <34>;
  664. atmel,clk-output-range = <0 83000000>;
  665. };
  666.  
  667. tcb0_clk: tcb0_clk {
  668. #clock-cells = <0>;
  669. reg = <35>;
  670. atmel,clk-output-range = <0 83000000>;
  671. };
  672.  
  673. tcb1_clk: tcb1_clk {
  674. #clock-cells = <0>;
  675. reg = <36>;
  676. atmel,clk-output-range = <0 83000000>;
  677. };
  678.  
  679. pwm_clk: pwm_clk {
  680. #clock-cells = <0>;
  681. reg = <38>;
  682. atmel,clk-output-range = <0 83000000>;
  683. };
  684.  
  685. adc_clk: adc_clk {
  686. #clock-cells = <0>;
  687. reg = <40>;
  688. atmel,clk-output-range = <0 83000000>;
  689. };
  690.  
  691. uhphs_clk: uhphs_clk {
  692. #clock-cells = <0>;
  693. reg = <41>;
  694. atmel,clk-output-range = <0 83000000>;
  695. };
  696.  
  697. udphs_clk: udphs_clk {
  698. #clock-cells = <0>;
  699. reg = <42>;
  700. atmel,clk-output-range = <0 83000000>;
  701. };
  702.  
  703. ssc0_clk: ssc0_clk {
  704. #clock-cells = <0>;
  705. reg = <43>;
  706. atmel,clk-output-range = <0 83000000>;
  707. };
  708.  
  709. ssc1_clk: ssc1_clk {
  710. #clock-cells = <0>;
  711. reg = <44>;
  712. atmel,clk-output-range = <0 83000000>;
  713. };
  714.  
  715. trng_clk: trng_clk {
  716. #clock-cells = <0>;
  717. reg = <47>;
  718. atmel,clk-output-range = <0 83000000>;
  719. };
  720.  
  721. pdmic_clk: pdmic_clk {
  722. #clock-cells = <0>;
  723. reg = <48>;
  724. atmel,clk-output-range = <0 83000000>;
  725. };
  726.  
  727. i2s0_clk: i2s0_clk {
  728. #clock-cells = <0>;
  729. reg = <54>;
  730. atmel,clk-output-range = <0 83000000>;
  731. };
  732.  
  733. i2s1_clk: i2s1_clk {
  734. #clock-cells = <0>;
  735. reg = <55>;
  736. atmel,clk-output-range = <0 83000000>;
  737. };
  738.  
  739. can0_clk: can0_clk {
  740. #clock-cells = <0>;
  741. reg = <56>;
  742. atmel,clk-output-range = <0 83000000>;
  743. };
  744.  
  745. can1_clk: can1_clk {
  746. #clock-cells = <0>;
  747. reg = <57>;
  748. atmel,clk-output-range = <0 83000000>;
  749. };
  750.  
  751. classd_clk: classd_clk {
  752. #clock-cells = <0>;
  753. reg = <59>;
  754. atmel,clk-output-range = <0 83000000>;
  755. };
  756. };
  757.  
  758. periph64ck {
  759. compatible = "atmel,at91sam9x5-clk-peripheral";
  760. #address-cells = <1>;
  761. #size-cells = <0>;
  762. clocks = <&mck>;
  763.  
  764. dma0_clk: dma0_clk {
  765. #clock-cells = <0>;
  766. reg = <6>;
  767. };
  768.  
  769. dma1_clk: dma1_clk {
  770. #clock-cells = <0>;
  771. reg = <7>;
  772. };
  773.  
  774. aes_clk: aes_clk {
  775. #clock-cells = <0>;
  776. reg = <9>;
  777. };
  778.  
  779. aesb_clk: aesb_clk {
  780. #clock-cells = <0>;
  781. reg = <10>;
  782. };
  783.  
  784. sha_clk: sha_clk {
  785. #clock-cells = <0>;
  786. reg = <12>;
  787. };
  788.  
  789. mpddr_clk: mpddr_clk {
  790. #clock-cells = <0>;
  791. reg = <13>;
  792. };
  793.  
  794. matrix0_clk: matrix0_clk {
  795. #clock-cells = <0>;
  796. reg = <15>;
  797. };
  798.  
  799. sdmmc0_hclk: sdmmc0_hclk {
  800. #clock-cells = <0>;
  801. reg = <31>;
  802. };
  803.  
  804. sdmmc1_hclk: sdmmc1_hclk {
  805. #clock-cells = <0>;
  806. reg = <32>;
  807. };
  808.  
  809. lcdc_clk: lcdc_clk {
  810. #clock-cells = <0>;
  811. reg = <45>;
  812. };
  813.  
  814. isc_clk: isc_clk {
  815. #clock-cells = <0>;
  816. reg = <46>;
  817. };
  818.  
  819. qspi0_clk: qspi0_clk {
  820. #clock-cells = <0>;
  821. reg = <52>;
  822. };
  823.  
  824. qspi1_clk: qspi1_clk {
  825. #clock-cells = <0>;
  826. reg = <53>;
  827. };
  828. };
  829.  
  830. gck {
  831. compatible = "atmel,sama5d2-clk-generated";
  832. #address-cells = <1>;
  833. #size-cells = <0>;
  834. interrupt-parent = <&pmc>;
  835. clocks = <&clk32k>, <&main>, <&plladiv>, <&utmi>, <&mck>, <&audio_pll_pmc>;
  836.  
  837. sdmmc0_gclk: sdmmc0_gclk {
  838. #clock-cells = <0>;
  839. reg = <31>;
  840. };
  841.  
  842. sdmmc1_gclk: sdmmc1_gclk {
  843. #clock-cells = <0>;
  844. reg = <32>;
  845. };
  846.  
  847. tcb0_gclk: tcb0_gclk {
  848. #clock-cells = <0>;
  849. reg = <35>;
  850. atmel,clk-output-range = <0 83000000>;
  851. };
  852.  
  853. tcb1_gclk: tcb1_gclk {
  854. #clock-cells = <0>;
  855. reg = <36>;
  856. atmel,clk-output-range = <0 83000000>;
  857. };
  858.  
  859. pwm_gclk: pwm_gclk {
  860. #clock-cells = <0>;
  861. reg = <38>;
  862. atmel,clk-output-range = <0 83000000>;
  863. };
  864.  
  865. pdmic_gclk: pdmic_gclk {
  866. #clock-cells = <0>;
  867. reg = <48>;
  868. };
  869.  
  870. i2s0_gclk: i2s0_gclk {
  871. #clock-cells = <0>;
  872. reg = <54>;
  873. };
  874.  
  875. i2s1_gclk: i2s1_gclk {
  876. #clock-cells = <0>;
  877. reg = <55>;
  878. };
  879.  
  880. can0_gclk: can0_gclk {
  881. #clock-cells = <0>;
  882. reg = <56>;
  883. atmel,clk-output-range = <0 80000000>;
  884. };
  885.  
  886. can1_gclk: can1_gclk {
  887. #clock-cells = <0>;
  888. reg = <57>;
  889. atmel,clk-output-range = <0 80000000>;
  890. };
  891.  
  892. classd_gclk: classd_gclk {
  893. #clock-cells = <0>;
  894. reg = <59>;
  895. atmel,clk-output-range = <0 100000000>;
  896. };
  897. };
  898. };
  899.  
  900. qspi0: spi@f0020000 {
  901. compatible = "atmel,sama5d2-qspi";
  902. reg = <0xf0020000 0x100>, <0xd0000000 0x08000000>;
  903. reg-names = "qspi_base", "qspi_mmap";
  904. interrupts = <52 IRQ_TYPE_LEVEL_HIGH 7>;
  905. clocks = <&qspi0_clk>;
  906. #address-cells = <1>;
  907. #size-cells = <0>;
  908. status = "disabled";
  909. };
  910.  
  911. qspi1: spi@f0024000 {
  912. compatible = "atmel,sama5d2-qspi";
  913. reg = <0xf0024000 0x100>, <0xd8000000 0x08000000>;
  914. reg-names = "qspi_base", "qspi_mmap";
  915. interrupts = <53 IRQ_TYPE_LEVEL_HIGH 7>;
  916. clocks = <&qspi1_clk>;
  917. #address-cells = <1>;
  918. #size-cells = <0>;
  919. status = "disabled";
  920. };
  921.  
  922. sha@f0028000 {
  923. compatible = "atmel,at91sam9g46-sha";
  924. reg = <0xf0028000 0x100>;
  925. interrupts = <12 IRQ_TYPE_LEVEL_HIGH 0>;
  926. dmas = <&dma0
  927. (AT91_XDMAC_DT_MEM_IF(0) | AT91_XDMAC_DT_PER_IF(1) |
  928. AT91_XDMAC_DT_PERID(30))>;
  929. dma-names = "tx";
  930. clocks = <&sha_clk>;
  931. clock-names = "sha_clk";
  932. status = "okay";
  933. };
  934.  
  935. aes@f002c000 {
  936. compatible = "atmel,at91sam9g46-aes";
  937. reg = <0xf002c000 0x100>;
  938. interrupts = <9 IRQ_TYPE_LEVEL_HIGH 0>;
  939. dmas = <&dma0
  940. (AT91_XDMAC_DT_MEM_IF(0) | AT91_XDMAC_DT_PER_IF(1) |
  941. AT91_XDMAC_DT_PERID(26))>,
  942. <&dma0
  943. (AT91_XDMAC_DT_MEM_IF(0) | AT91_XDMAC_DT_PER_IF(1) |
  944. AT91_XDMAC_DT_PERID(27))>;
  945. dma-names = "tx", "rx";
  946. clocks = <&aes_clk>;
  947. clock-names = "aes_clk";
  948. status = "okay";
  949. };
  950.  
  951. spi0: spi@f8000000 {
  952. compatible = "atmel,at91rm9200-spi";
  953. reg = <0xf8000000 0x100>;
  954. interrupts = <33 IRQ_TYPE_LEVEL_HIGH 7>;
  955. dmas = <&dma0
  956. (AT91_XDMAC_DT_MEM_IF(0) | AT91_XDMAC_DT_PER_IF(1) |
  957. AT91_XDMAC_DT_PERID(6))>,
  958. <&dma0
  959. (AT91_XDMAC_DT_MEM_IF(0) | AT91_XDMAC_DT_PER_IF(1) |
  960. AT91_XDMAC_DT_PERID(7))>;
  961. dma-names = "tx", "rx";
  962. clocks = <&spi0_clk>;
  963. clock-names = "spi_clk";
  964. atmel,fifo-size = <16>;
  965. #address-cells = <1>;
  966. #size-cells = <0>;
  967. status = "disabled";
  968. };
  969.  
  970. macb0: ethernet@f8008000 {
  971. compatible = "atmel,sama5d2-gem";
  972. reg = <0xf8008000 0x1000>;
  973. interrupts = <5 IRQ_TYPE_LEVEL_HIGH 3 /* Queue 0 */
  974. 66 IRQ_TYPE_LEVEL_HIGH 3 /* Queue 1 */
  975. 67 IRQ_TYPE_LEVEL_HIGH 3>; /* Queue 2 */
  976. #address-cells = <1>;
  977. #size-cells = <0>;
  978. clocks = <&macb0_clk>, <&macb0_clk>;
  979. clock-names = "hclk", "pclk";
  980. status = "disabled";
  981. };
  982.  
  983. tcb0: timer@f800c000 {
  984. compatible = "atmel,at91sam9x5-tcb";
  985. reg = <0xf800c000 0x100>;
  986. interrupts = <35 IRQ_TYPE_LEVEL_HIGH 0>;
  987. clocks = <&tcb0_clk>, <&clk32k>;
  988. clock-names = "t0_clk", "slow_clk";
  989. };
  990.  
  991. tcb1: timer@f8010000 {
  992. compatible = "atmel,at91sam9x5-tcb";
  993. reg = <0xf8010000 0x100>;
  994. interrupts = <36 IRQ_TYPE_LEVEL_HIGH 0>;
  995. clocks = <&tcb1_clk>, <&clk32k>;
  996. clock-names = "t0_clk", "slow_clk";
  997. };
  998.  
  999. pdmic: pdmic@f8018000 {
  1000. compatible = "atmel,sama5d2-pdmic";
  1001. reg = <0xf8018000 0x124>;
  1002. interrupts = <48 IRQ_TYPE_LEVEL_HIGH 7>;
  1003. dmas = <&dma0
  1004. (AT91_XDMAC_DT_MEM_IF(0) | AT91_XDMAC_DT_PER_IF(1)
  1005. | AT91_XDMAC_DT_PERID(50))>;
  1006. dma-names = "rx";
  1007. clocks = <&pdmic_clk>, <&pdmic_gclk>;
  1008. clock-names = "pclk", "gclk";
  1009. status = "disabled";
  1010. };
  1011.  
  1012. uart0: serial@f801c000 {
  1013. compatible = "atmel,at91sam9260-usart";
  1014. reg = <0xf801c000 0x100>;
  1015. interrupts = <24 IRQ_TYPE_LEVEL_HIGH 7>;
  1016. dmas = <&dma0
  1017. (AT91_XDMAC_DT_MEM_IF(0) | AT91_XDMAC_DT_PER_IF(1) |
  1018. AT91_XDMAC_DT_PERID(35))>,
  1019. <&dma0
  1020. (AT91_XDMAC_DT_MEM_IF(0) | AT91_XDMAC_DT_PER_IF(1) |
  1021. AT91_XDMAC_DT_PERID(36))>;
  1022. dma-names = "tx", "rx";
  1023. clocks = <&uart0_clk>;
  1024. clock-names = "usart";
  1025. status = "disabled";
  1026. };
  1027.  
  1028. uart1: serial@f8020000 {
  1029. compatible = "atmel,at91sam9260-usart";
  1030. reg = <0xf8020000 0x100>;
  1031. interrupts = <25 IRQ_TYPE_LEVEL_HIGH 7>;
  1032. dmas = <&dma0
  1033. (AT91_XDMAC_DT_MEM_IF(0) | AT91_XDMAC_DT_PER_IF(1) |
  1034. AT91_XDMAC_DT_PERID(37))>,
  1035. <&dma0
  1036. (AT91_XDMAC_DT_MEM_IF(0) | AT91_XDMAC_DT_PER_IF(1) |
  1037. AT91_XDMAC_DT_PERID(38))>;
  1038. dma-names = "tx", "rx";
  1039. clocks = <&uart1_clk>;
  1040. clock-names = "usart";
  1041. status = "disabled";
  1042. };
  1043.  
  1044. uart2: serial@f8024000 {
  1045. compatible = "atmel,at91sam9260-usart";
  1046. reg = <0xf8024000 0x100>;
  1047. interrupts = <26 IRQ_TYPE_LEVEL_HIGH 7>;
  1048. dmas = <&dma0
  1049. (AT91_XDMAC_DT_MEM_IF(0) | AT91_XDMAC_DT_PER_IF(1) |
  1050. AT91_XDMAC_DT_PERID(39))>,
  1051. <&dma0
  1052. (AT91_XDMAC_DT_MEM_IF(0) | AT91_XDMAC_DT_PER_IF(1) |
  1053. AT91_XDMAC_DT_PERID(40))>;
  1054. dma-names = "tx", "rx";
  1055. clocks = <&uart2_clk>;
  1056. clock-names = "usart";
  1057. status = "disabled";
  1058. };
  1059.  
  1060. pwm0: pwm@f002c000 {
  1061. compatible = "atmel,sama5d3-pwm";
  1062. reg = <0xf002c000 0x300>;
  1063. interrupts = <28 IRQ_TYPE_LEVEL_HIGH 4>;
  1064. #pwm-cells = <3>;
  1065. clocks = <&pwm_clk>;
  1066. status = "disabled";
  1067. };
  1068.  
  1069. i2c0: i2c@f8028000 {
  1070. compatible = "atmel,sama5d2-i2c";
  1071. reg = <0xf8028000 0x100>;
  1072. interrupts = <29 IRQ_TYPE_LEVEL_HIGH 7>;
  1073. dmas = <&dma0
  1074. (AT91_XDMAC_DT_MEM_IF(0) | AT91_XDMAC_DT_PER_IF(1) |
  1075. AT91_XDMAC_DT_PERID(0))>,
  1076. <&dma0
  1077. (AT91_XDMAC_DT_MEM_IF(0) | AT91_XDMAC_DT_PER_IF(1) |
  1078. AT91_XDMAC_DT_PERID(1))>;
  1079. dma-names = "tx", "rx";
  1080. #address-cells = <1>;
  1081. #size-cells = <0>;
  1082. clocks = <&twi0_clk>;
  1083. status = "disabled";
  1084. };
  1085.  
  1086. sfr: sfr@f8030000 {
  1087. compatible = "atmel,sama5d2-sfr", "syscon";
  1088. reg = <0xf8030000 0x98>;
  1089. };
  1090.  
  1091. flx0: flexcom@f8034000 {
  1092. compatible = "atmel,sama5d2-flexcom";
  1093. reg = <0xf8034000 0x200>;
  1094. clocks = <&flx0_clk>;
  1095. #address-cells = <1>;
  1096. #size-cells = <1>;
  1097. ranges = <0x0 0xf8034000 0x800>;
  1098. status = "disabled";
  1099. };
  1100.  
  1101. flx1: flexcom@f8038000 {
  1102. compatible = "atmel,sama5d2-flexcom";
  1103. reg = <0xf8038000 0x200>;
  1104. clocks = <&flx1_clk>;
  1105. #address-cells = <1>;
  1106. #size-cells = <1>;
  1107. ranges = <0x0 0xf8038000 0x800>;
  1108. status = "disabled";
  1109. };
  1110.  
  1111. rstc@f8048000 {
  1112. compatible = "atmel,sama5d3-rstc";
  1113. reg = <0xf8048000 0x10>;
  1114. clocks = <&clk32k>;
  1115. };
  1116.  
  1117. shdwc@f8048010 {
  1118. compatible = "atmel,sama5d2-shdwc";
  1119. reg = <0xf8048010 0x10>;
  1120. clocks = <&clk32k>;
  1121. #address-cells = <1>;
  1122. #size-cells = <0>;
  1123. atmel,wakeup-rtc-timer;
  1124. };
  1125.  
  1126. pit: timer@f8048030 {
  1127. compatible = "atmel,at91sam9260-pit";
  1128. reg = <0xf8048030 0x10>;
  1129. interrupts = <3 IRQ_TYPE_LEVEL_HIGH 5>;
  1130. clocks = <&h32ck>;
  1131. };
  1132.  
  1133. watchdog@f8048040 {
  1134. compatible = "atmel,sama5d4-wdt";
  1135. reg = <0xf8048040 0x10>;
  1136. interrupts = <4 IRQ_TYPE_LEVEL_HIGH 7>;
  1137. clocks = <&clk32k>;
  1138. status = "disabled";
  1139. };
  1140.  
  1141. sckc@f8048050 {
  1142. compatible = "atmel,at91sam9x5-sckc";
  1143. reg = <0xf8048050 0x4>;
  1144.  
  1145. slow_rc_osc: slow_rc_osc {
  1146. compatible = "atmel,at91sam9x5-clk-slow-rc-osc";
  1147. #clock-cells = <0>;
  1148. clock-frequency = <32768>;
  1149. clock-accuracy = <250000000>;
  1150. atmel,startup-time-usec = <75>;
  1151. };
  1152.  
  1153. slow_osc: slow_osc {
  1154. compatible = "atmel,at91sam9x5-clk-slow-osc";
  1155. #clock-cells = <0>;
  1156. clocks = <&slow_xtal>;
  1157. atmel,startup-time-usec = <1200000>;
  1158. };
  1159.  
  1160. clk32k: slowck {
  1161. compatible = "atmel,at91sam9x5-clk-slow";
  1162. #clock-cells = <0>;
  1163. clocks = <&slow_rc_osc &slow_osc>;
  1164. };
  1165. };
  1166.  
  1167. rtc@f80480b0 {
  1168. compatible = "atmel,at91rm9200-rtc";
  1169. reg = <0xf80480b0 0x30>;
  1170. interrupts = <74 IRQ_TYPE_LEVEL_HIGH 7>;
  1171. clocks = <&clk32k>;
  1172. };
  1173.  
  1174. i2s0: i2s@f8050000 {
  1175. compatible = "atmel,sama5d2-i2s";
  1176. reg = <0xf8050000 0x100>;
  1177. interrupts = <54 IRQ_TYPE_LEVEL_HIGH 7>;
  1178. dmas = <&dma0
  1179. (AT91_XDMAC_DT_MEM_IF(0) | AT91_XDMAC_DT_PER_IF(1) |
  1180. AT91_XDMAC_DT_PERID(31))>,
  1181. <&dma0
  1182. (AT91_XDMAC_DT_MEM_IF(0) | AT91_XDMAC_DT_PER_IF(1) |
  1183. AT91_XDMAC_DT_PERID(32))>;
  1184. dma-names = "tx", "rx";
  1185. clocks = <&i2s0_clk>, <&i2s0_gclk>, <&audio_pll_pmc>;
  1186. clock-names = "pclk", "gclk", "aclk";
  1187. status = "disabled";
  1188. };
  1189.  
  1190. can0: can@f8054000 {
  1191. compatible = "bosch,m_can";
  1192. reg = <0xf8054000 0x4000>, <0x210000 0x4000>;
  1193. reg-names = "m_can", "message_ram";
  1194. interrupts = <56 IRQ_TYPE_LEVEL_HIGH 7>,
  1195. <64 IRQ_TYPE_LEVEL_HIGH 7>;
  1196. interrupt-names = "int0", "int1";
  1197. clocks = <&can0_clk>, <&can0_gclk>;
  1198. clock-names = "hclk", "cclk";
  1199. assigned-clocks = <&can0_gclk>;
  1200. assigned-clock-parents = <&utmi>;
  1201. assigned-clock-rates = <40000000>;
  1202. bosch,mram-cfg = <0x0 0 0 32 0 0 0 1>;
  1203. status = "disabled";
  1204. };
  1205.  
  1206. spi1: spi@fc000000 {
  1207. compatible = "atmel,at91rm9200-spi";
  1208. reg = <0xfc000000 0x100>;
  1209. interrupts = <34 IRQ_TYPE_LEVEL_HIGH 7>;
  1210. dmas = <&dma0
  1211. (AT91_XDMAC_DT_MEM_IF(0) | AT91_XDMAC_DT_PER_IF(1) |
  1212. AT91_XDMAC_DT_PERID(8))>,
  1213. <&dma0
  1214. (AT91_XDMAC_DT_MEM_IF(0) | AT91_XDMAC_DT_PER_IF(1) |
  1215. AT91_XDMAC_DT_PERID(9))>;
  1216. dma-names = "tx", "rx";
  1217. clocks = <&spi1_clk>;
  1218. clock-names = "spi_clk";
  1219. atmel,fifo-size = <16>;
  1220. #address-cells = <1>;
  1221. #size-cells = <0>;
  1222. status = "disabled";
  1223. };
  1224.  
  1225. uart3: serial@fc008000 {
  1226. compatible = "atmel,at91sam9260-usart";
  1227. reg = <0xfc008000 0x100>;
  1228. interrupts = <27 IRQ_TYPE_LEVEL_HIGH 7>;
  1229. dmas = <&dma0
  1230. (AT91_XDMAC_DT_MEM_IF(0) | AT91_XDMAC_DT_PER_IF(1) |
  1231. AT91_XDMAC_DT_PERID(41))>,
  1232. <&dma0
  1233. (AT91_XDMAC_DT_MEM_IF(0) | AT91_XDMAC_DT_PER_IF(1) |
  1234. AT91_XDMAC_DT_PERID(42))>;
  1235. dma-names = "tx", "rx";
  1236. clocks = <&uart3_clk>;
  1237. clock-names = "usart";
  1238. status = "disabled";
  1239. };
  1240.  
  1241. uart4: serial@fc00c000 {
  1242. compatible = "atmel,at91sam9260-usart";
  1243. reg = <0xfc00c000 0x100>;
  1244. dmas = <&dma0
  1245. (AT91_XDMAC_DT_MEM_IF(0) | AT91_XDMAC_DT_PER_IF(1) |
  1246. AT91_XDMAC_DT_PERID(43))>,
  1247. <&dma0
  1248. (AT91_XDMAC_DT_MEM_IF(0) | AT91_XDMAC_DT_PER_IF(1) |
  1249. AT91_XDMAC_DT_PERID(44))>;
  1250. dma-names = "tx", "rx";
  1251. interrupts = <28 IRQ_TYPE_LEVEL_HIGH 7>;
  1252. clocks = <&uart4_clk>;
  1253. clock-names = "usart";
  1254. status = "disabled";
  1255. };
  1256.  
  1257. flx2: flexcom@fc010000 {
  1258. compatible = "atmel,sama5d2-flexcom";
  1259. reg = <0xfc010000 0x200>;
  1260. clocks = <&flx2_clk>;
  1261. #address-cells = <1>;
  1262. #size-cells = <1>;
  1263. ranges = <0x0 0xfc010000 0x800>;
  1264. status = "disabled";
  1265. };
  1266.  
  1267. flx3: flexcom@fc014000 {
  1268. compatible = "atmel,sama5d2-flexcom";
  1269. reg = <0xfc014000 0x200>;
  1270. clocks = <&flx3_clk>;
  1271. #address-cells = <1>;
  1272. #size-cells = <1>;
  1273. ranges = <0x0 0xfc014000 0x800>;
  1274. status = "disabled";
  1275. };
  1276.  
  1277. flx4: flexcom@fc018000 {
  1278. compatible = "atmel,sama5d2-flexcom";
  1279. reg = <0xfc018000 0x200>;
  1280. clocks = <&flx4_clk>;
  1281. #address-cells = <1>;
  1282. #size-cells = <1>;
  1283. ranges = <0x0 0xfc018000 0x800>;
  1284. status = "disabled";
  1285. };
  1286.  
  1287. trng@fc01c000 {
  1288. compatible = "atmel,at91sam9g45-trng";
  1289. reg = <0xfc01c000 0x100>;
  1290. interrupts = <47 IRQ_TYPE_LEVEL_HIGH 0>;
  1291. clocks = <&trng_clk>;
  1292. };
  1293.  
  1294. aic: interrupt-controller@fc020000 {
  1295. #interrupt-cells = <3>;
  1296. compatible = "atmel,sama5d2-aic";
  1297. interrupt-controller;
  1298. reg = <0xfc020000 0x200>;
  1299. atmel,external-irqs = <49>;
  1300. };
  1301.  
  1302. i2c1: i2c@fc028000 {
  1303. compatible = "atmel,sama5d2-i2c";
  1304. reg = <0xfc028000 0x100>;
  1305. interrupts = <30 IRQ_TYPE_LEVEL_HIGH 7>;
  1306. dmas = <&dma0
  1307. (AT91_XDMAC_DT_MEM_IF(0) | AT91_XDMAC_DT_PER_IF(1) |
  1308. AT91_XDMAC_DT_PERID(2))>,
  1309. <&dma0
  1310. (AT91_XDMAC_DT_MEM_IF(0) | AT91_XDMAC_DT_PER_IF(1) |
  1311. AT91_XDMAC_DT_PERID(3))>;
  1312. dma-names = "tx", "rx";
  1313. #address-cells = <1>;
  1314. #size-cells = <0>;
  1315. clocks = <&twi1_clk>;
  1316. status = "disabled";
  1317. };
  1318.  
  1319. adc: adc@fc030000 {
  1320. compatible = "atmel,sama5d2-adc";
  1321. reg = <0xfc030000 0x100>;
  1322. interrupts = <40 IRQ_TYPE_LEVEL_HIGH 7>;
  1323. clocks = <&adc_clk>;
  1324. clock-names = "adc_clk";
  1325. atmel,min-sample-rate-hz = <200000>;
  1326. atmel,max-sample-rate-hz = <20000000>;
  1327. atmel,startup-time-ms = <4>;
  1328. status = "disabled";
  1329. };
  1330.  
  1331. pioA: pinctrl@fc038000 {
  1332. compatible = "atmel,sama5d2-pinctrl";
  1333. reg = <0xfc038000 0x600>;
  1334. interrupts = <18 IRQ_TYPE_LEVEL_HIGH 7>,
  1335. <68 IRQ_TYPE_LEVEL_HIGH 7>,
  1336. <69 IRQ_TYPE_LEVEL_HIGH 7>,
  1337. <70 IRQ_TYPE_LEVEL_HIGH 7>;
  1338. interrupt-controller;
  1339. #interrupt-cells = <2>;
  1340. gpio-controller;
  1341. #gpio-cells = <2>;
  1342. clocks = <&pioA_clk>;
  1343. };
  1344.  
  1345. tdes@fc044000 {
  1346. compatible = "atmel,at91sam9g46-tdes";
  1347. reg = <0xfc044000 0x100>;
  1348. interrupts = <11 IRQ_TYPE_LEVEL_HIGH 0>;
  1349. dmas = <&dma0
  1350. (AT91_XDMAC_DT_MEM_IF(0) | AT91_XDMAC_DT_PER_IF(1) |
  1351. AT91_XDMAC_DT_PERID(28))>,
  1352. <&dma0
  1353. (AT91_XDMAC_DT_MEM_IF(0) | AT91_XDMAC_DT_PER_IF(1) |
  1354. AT91_XDMAC_DT_PERID(29))>;
  1355. dma-names = "tx", "rx";
  1356. clocks = <&tdes_clk>;
  1357. clock-names = "tdes_clk";
  1358. status = "okay";
  1359. };
  1360.  
  1361. classd: classd@fc048000 {
  1362. compatible = "atmel,sama5d2-classd";
  1363. reg = <0xfc048000 0x100>;
  1364. interrupts = <59 IRQ_TYPE_LEVEL_HIGH 7>;
  1365. dmas = <&dma0
  1366. (AT91_XDMAC_DT_MEM_IF(0) | AT91_XDMAC_DT_PER_IF(1) |
  1367. AT91_XDMAC_DT_PERID(47))>;
  1368. dma-names = "tx";
  1369. clocks = <&classd_clk>, <&classd_gclk>, <&audio_pll_pmc>;
  1370. clock-names = "pclk", "gclk", "aclk";
  1371. status = "disabled";
  1372. };
  1373.  
  1374. i2s1: i2s@fc04c000 {
  1375. compatible = "atmel,sama5d2-i2s";
  1376. reg = <0xfc04c000 0x100>;
  1377. interrupts = <55 IRQ_TYPE_LEVEL_HIGH 7>;
  1378. dmas = <&dma0
  1379. (AT91_XDMAC_DT_MEM_IF(0) | AT91_XDMAC_DT_PER_IF(1) |
  1380. AT91_XDMAC_DT_PERID(33))>,
  1381. <&dma0
  1382. (AT91_XDMAC_DT_MEM_IF(0) | AT91_XDMAC_DT_PER_IF(1) |
  1383. AT91_XDMAC_DT_PERID(34))>;
  1384. dma-names = "tx", "rx";
  1385. clocks = <&i2s1_clk>, <&i2s1_gclk>, <&audio_pll_pmc>;
  1386. clock-names = "pclk", "gclk", "aclk";
  1387. status = "disabled";
  1388. };
  1389.  
  1390. can1: can@fc050000 {
  1391. compatible = "bosch,m_can";
  1392. reg = <0xfc050000 0x4000>, <0x210000 0x4000>;
  1393. reg-names = "m_can", "message_ram";
  1394. interrupts = <57 IRQ_TYPE_LEVEL_HIGH 7>,
  1395. <65 IRQ_TYPE_LEVEL_HIGH 7>;
  1396. interrupt-names = "int0", "int1";
  1397. clocks = <&can1_clk>, <&can1_gclk>;
  1398. clock-names = "hclk", "cclk";
  1399. assigned-clocks = <&can1_gclk>;
  1400. assigned-clock-parents = <&utmi>;
  1401. assigned-clock-rates = <40000000>;
  1402. bosch,mram-cfg = <0x0 0 0 32 0 0 0 1>;
  1403. status = "disabled";
  1404. };
  1405.  
  1406. chipid@fc069000 {
  1407. compatible = "atmel,sama5d2-chipid";
  1408. reg = <0xfc069000 0x8>;
  1409. };
  1410. };
  1411. };
  1412. };
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