dts_ov7740.dts

	compatible = "castel,imx6dl-castel", "fsl,imx6dl", "fsl,imx6dl-sabresd";

	v4l2_cap_0 {
		compatible = "fsl,imx6q-v4l2-capture";
		ipu_id = <0>;
		csi_id = <0>;
		mclk_source = <0>;
		status = "okay";
	};

&iomuxc {
	pinctrl-names = "default";
	yourboard {
		pinctrl_i2c1_gip2: i2c1grp-gip2 {
			fsl,pins = <
				MX6QDL_PAD_CSI0_DAT9__I2C1_SCL 0x4001b8b1
				MX6QDL_PAD_CSI0_DAT8__I2C1_SDA 0x4001b8b1
				MX6QDL_PAD_GPIO_0__CCM_CLKO1    	   0x130b0		/* GPIO0 that give clock to camera */
			>;
		};
		pinctrl_ipu_camera_gip2: ipucameragrp-2 { /* parallel camera */
			fsl,pins = <
				MX6QDL_PAD_CSI0_DAT12__IPU1_CSI0_DATA12    0x000130B0
				MX6QDL_PAD_CSI0_DAT13__IPU1_CSI0_DATA13    0x000130B0
				MX6QDL_PAD_CSI0_DAT14__IPU1_CSI0_DATA14    0x000130B0
				MX6QDL_PAD_CSI0_DAT15__IPU1_CSI0_DATA15    0x000130B0
				MX6QDL_PAD_CSI0_DAT16__IPU1_CSI0_DATA16    0x000130B0
				MX6QDL_PAD_CSI0_DAT17__IPU1_CSI0_DATA17    0x000130B0
				MX6QDL_PAD_CSI0_DAT18__IPU1_CSI0_DATA18    0x000130B0
				MX6QDL_PAD_CSI0_DAT19__IPU1_CSI0_DATA19    0x000130B0
				MX6QDL_PAD_CSI0_DATA_EN__GPIO5_IO20	0x80000000
				MX6QDL_PAD_CSI0_PIXCLK__IPU1_CSI0_PIXCLK   0x000130B0
				MX6QDL_PAD_CSI0_MCLK__IPU1_CSI0_HSYNC      0x000130B0
				MX6QDL_PAD_CSI0_VSYNC__IPU1_CSI0_VSYNC     0x000130B0
			>;
		};
&i2c1 {
	status = "okay";
	clock-frequency = <100000>;
	pinctrl-names = "default";
	pinctrl-0 = <&pinctrl_i2c1_gip2>;
	ov7740: ov7740x@21 {
		compatible = "ovti,ovcompany";
		reg = <0x21>;
		pinctrl-names = "default";
		pinctrl-0 = <&pinctrl_ipu_camera_gip2>;
		clocks = <&clks 201>;	/* video_27m:204 */ /* cko(24MHz 201) */
		clock-names = "csi_mclk";
		DOVDD-supply = <&reg_1p8v>; /* 1.8v */
		AVDD-supply = <&reg_3p3v>;  /* AVDD taken from 3.3v */
		DVDD-supply = <&reg_3p3v>;  /* DVDD taken from 3.3v */
		pwn-gpios = <&gpio5 20 0>;   /* fake data enable */
		rst-gpios = <&gpio5 20 0>;   /* fake data enable */
		csi_id = <0>;
		mclk = <24000000>;
		mclk_source = <0>;
	};
};