[smd@alaska openrisc]$ fusesoc --cores-root=/home/smd/work/coding/openrisc/mor1kx/ sim --sim=verilator  mor1kx-generic  --elf-load=/home/smd/work/coding/openrisc/dhrystone/dhrystone_10  --trace_enable > dhry_out
^C[smd@alaska openrisc]$ fusesoc --cores-root=/home/smd/work/coding/openrisc/mor1kx/ sim --sim=verilator  mor1kx-generic  --elf-load=/home/smd/work/coding/openrisc/dhrystone/dhrystone_10  --trace_enable
WARN:  plusargs section is deprecated and will be removed in future versions. Please migrate to parameters in vlog_tb_utils
WARN:  plusargs section is deprecated and will be removed in future versions. Please migrate to parameters in wb_intercon
WARN:  plusargs section is deprecated and will be removed in future versions. Please migrate to parameters in wb_intercon-1.0
WARN:  plusargs section is deprecated and will be removed in future versions. Please migrate to parameters in fifo-1.0
WARN:  plusargs section is deprecated and will be removed in future versions. Please migrate to parameters in elf-loader
WARN:  plusargs section is deprecated and will be removed in future versions. Please migrate to parameters in ram_wb
WARN:  plusargs section is deprecated and will be removed in future versions. Please migrate to parameters in wb_sdram_ctrl
WARN:  plusargs section is deprecated and will be removed in future versions. Please migrate to parameters in wb_altera_ddr_wrapper
WARN:  plusargs section is deprecated and will be removed in future versions. Please migrate to parameters in stream_utils-1.0
INFO:  Preparing verilator_tb_utils
INFO:  Preparing adv_debug_sys
INFO:  Preparing jtag_tap-1.13
INFO:  Preparing mor1kx
INFO:  Preparing uart16550-1.5.4
INFO:  Preparing verilog-arbiter-r1
INFO:  Preparing verilog_utils
INFO:  Preparing wb_common
INFO:  Preparing wb_intercon-1.0
INFO:  Preparing wb_ram-1.0
INFO:  Preparing elf-loader
INFO:  Preparing mor1kx-generic

INFO:  Running /home/smd/work/coding/openrisc/orpsoc-cores/cores/elf-loader/check_libelf.sh
/home/smd/work/coding/openrisc/build/mor1kx-generic/src/verilator_tb_utils/
/home/smd/work/coding/openrisc/build/mor1kx-generic/src/elf-loader/
/home/smd/work/coding/openrisc/build/mor1kx-generic/sim-verilator/bench/verilator
/home/smd/work/coding/openrisc/build/mor1kx-generic/src
INFO:  Verilating source

INFO:  Starting Verilator:

INFO:  Compiling verilator_tb_utils.cpp
INFO:  Compiling jtagServer.cpp
ar: creating verilator_tb_utils.a
a - verilator_tb_utils.o
a - jtagServer.o

INFO:  Compiling elf-loader.c
ar: creating elf-loader.a
a - elf-loader.o

INFO:  Building verilator executable:
/home/smd/work/coding/openrisc/build/mor1kx-generic/src/mor1kx-generic/bench/verilator/tb.cpp: In function ‘int main(int, char**, char**)’:
/home/smd/work/coding/openrisc/build/mor1kx-generic/src/mor1kx-generic/bench/verilator/tb.cpp:89:29: error: ‘class Vorpsoc_top’ has no member named ‘v’
   new VerilatorTbUtils(top->v->wb_bfm_memory0->ram0->mem);
                             ^
/home/smd/work/coding/openrisc/build/mor1kx-generic/src/mor1kx-generic/bench/verilator/tb.cpp:110:15: error: ‘class Vorpsoc_top’ has no member named ‘v’
   insn = top->v->mor1kx0->mor1kx_cpu->monitor_execute_insn;
               ^
/home/smd/work/coding/openrisc/build/mor1kx-generic/src/mor1kx-generic/bench/verilator/tb.cpp:111:16: error: ‘class Vorpsoc_top’ has no member named ‘v’
   ex_pc = top->v->mor1kx0->mor1kx_cpu->monitor_execute_pc;
                ^
At global scope:
cc1plus: warning: unrecognized command line option ‘-Wno-parentheses-equality’
make: *** [tb.o] Error 1
ERROR: Failed to build simulation model
ERROR: "make -f Vorpsoc_top.mk Vorpsoc_top" exited with an error code.
ERROR: See stderr for details.