clock_divder

module clk_gen#(parameter tact=5000000)(input clk, // the 50 MHz clock input
        input rst,
        input en,
        output clk_div); //the 5 MHZ clock output

reg [26:0] cnt_reg, cnt_nxt;
reg clk_div_reg, clk_div_nxt;

always @(posedge clk or negedge rst)
    if (rst == 0)
    begin
        cnt_reg <= 0;
                clk_div_reg <= 0;
    end
    else
    begin
        cnt_reg <= cnt_nxt;
        clk_div_reg <= clk_div_nxt;
    end


always @(en, cnt_reg)
begin
    clk_div_nxt = clk_div_reg;
    if(en == 1)
    begin
        if(cnt_reg == tact)
        begin
            cnt_nxt = 0;
            clk_div_nxt = ~clk_div_reg;
        end
        else
        cnt_nxt = cnt_reg + 1;
    end
end

assign clk_div = clk_div_reg;

endmodule