library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;

entity ChangeSevernSeg is
    port(
        clk      : in  std_logic;
        rst      : in  std_logic;
        segment7 : out std_logic_vector(3 downto 0)
    );
end entity ChangeSevernSeg;

architecture Behavioral of ChangeSevernSeg is
    constant clock : integer                      := 1024;
    variable count : integer                      := 0;
    signal sign    : std_logic_vector(3 downto 0) := "0111";

begin
    process(clk, rst) is
    begin
        if rst = '1' then
            sign  <= "0111";
            count := 0;
        elsif rising_edge(clk) then
            count := count + 1;
        end if;
        if count = clock then
            count := 0;
            case sign is
                when "0111" =>
                    sign <= "1011";
                when "1011" =>
                    sign <= "1101";
                when "1101" =>
                    sign <= "1110";
                when "1110" =>
                    sign <= "0111";
            end case;
        end if;
    end process;
    segment7 <= sign;
end architecture Behavioral;