library ieee;
use ieee.std_logic_1164.all;

entity tb_receiver is
end tb_receiver;

architecture testbench of tb_receiver is

signal clk          : std_logic;
signal areset       : std_logic;
signal ack          : std_logic;
signal RxD          : std_logic;
signal data         : std_logic_vector(7 downto 0);
signal received : std_logic;
signal fault        : std_logic;

component receiver is
    generic (
        sys_freq    : integer := 50000000;
        baudrate    : integer := 9600
    );

    port (
        clk     : in std_logic;                             -- Bound to 50 MHz system clock
        areset  : in std_logic;                             -- Bound to BUTTON0
        ack     : in std_logic;                             -- Bound to BUTTON1
        RxD     : in std_logic;
        data        : out std_logic_vector(7 downto 0);
        received    : out std_logic;
        fault       : out std_logic
    );
end component receiver;

begin

    dut : receiver
    port map (
        clk     => clk,
        areset  => areset,
        ack     => ack,
        RxD     => RxD,
        data        => data,
        received    => received,
        fault       => fault
    );

    clockgen: process is
    begin
        clk <= '0';
        wait for 1 ns;
        clk <= '1';
        wait for 1 ns;
    end process clockgen;

    datagen: process is
    begin

        -- Set with initial values
        areset  <= '1';
        ack     <= '1';
        RxD     <= '1';
        wait until clk = '1';
        wait for 10 ns;
        -- Send in false bit
        areset  <= '1';
        ack     <= '1';
        RxD     <= '0';
        wait until clk = '1';
        wait for 2 us;
        -- Let it stay in faulty for a bit
        areset  <= '1';
        ack     <= '1';
        RxD     <= '1';
        wait until clk = '1';
        wait for 2 us;
        -- Acknowledge
        areset  <= '1';
        ack     <= '0';
        RxD     <= '1';
        wait until clk = '1';
        wait for 20 ns;
        -- Let it stay idle a bit
        areset  <= '1';
        ack     <= '1';
        RxD     <= '1';
        wait until clk = '1';
        wait for 20 ns;
        -- Send in proper data, startbit here, we're receiving 00000000, LSB on the left
        areset  <= '1';
        ack     <= '1';
        RxD     <= '0';
        wait until clk = '1';
        wait for 2*5208 ns;
        -- 1st data bit
        areset  <= '1';
        ack     <= '1';
        RxD     <= '0';
        wait until clk = '1';
        wait for 2*5208 ns;
        -- 2st data bit
        areset  <= '1';
        ack     <= '1';
        RxD     <= '0';
        wait until clk = '1';
        wait for 2*5208 ns;
        -- 3rd data bit
        areset  <= '1';
        ack     <= '1';
        RxD     <= '0';
        wait until clk = '1';
        wait for 2*5208 ns;
        -- The 4th data bit
        areset  <= '1';
        ack     <= '1';
        RxD     <= '0';
        wait until clk = '1';
        wait for 2*5208 ns;
        -- 5th data bit
        areset  <= '1';
        ack     <= '1';
        RxD     <= '0';
        wait until clk = '1';
        wait for 2*5208 ns;
        -- 6th data bit
        areset  <= '1';
        ack     <= '1';
        RxD     <= '0';
        wait until clk = '1';
        wait for 2*5208 ns;
        -- 7th data bit
        areset  <= '1';
        ack     <= '1';
        RxD     <= '0';
        wait until clk = '1';
        wait for 2*5208 ns;
        -- 8th data bit
        areset  <= '1';
        ack     <= '1';
        RxD     <= '0';
        wait until clk = '1';
        wait for 2*5208 ns;
        -- Stop bit and let it stay in succes for a bit
        areset  <= '1';
        ack     <= '1';
        RxD     <= '1';
        wait until clk = '1';
        wait for 2*6208 ns;
        -- Acknowledge
        areset  <= '1';
        ack     <= '0';
        RxD     <= '1';
        wait until clk = '1';
        wait for 20 ns;
        -- We're done
        areset  <= '1';
        ack     <= '1';
        RxD     <= '1';
        wait until clk = '1';
        wait for 20 ns;
        wait;
    end process;
end testbench;