Sigma Delta Test - Working @ Low Freq

library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use ieee.numeric_std.all;

library unisim;
use unisim.vcomponents.all;

entity SigmaDelta is
    Port ( clk : in  STD_LOGIC;
            clk_out : out std_logic;
           rst : in  STD_LOGIC;
           diff_n : in  STD_LOGIC;
           diff_p : in  STD_LOGIC;
           o : out  STD_LOGIC;
              leds : out std_logic_vector(7 downto 0);
              dac : out std_logic_vector(7 downto 0));
end SigmaDelta;

architecture Behavioral of SigmaDelta is
--  signal max_count : integer := 256;
    signal o_buf : std_logic;
    signal total : unsigned(10 downto 0) := (others => '0');
    signal count : unsigned(31 downto 0) := (others => '0');
    signal fast_clk : std_logic := '0';
    signal clk_buffer : std_logic := '0';
    component mult
port
 (-- Clock in ports
  CLK_IN1           : in     std_logic;
  -- Clock out ports
  CLK_OUT1          : out    std_logic
 );
end component;
begin
    clk_out <= clk_buffer;
    ibufds_inst : IBUFDS
    generic map (
        IOSTANDARD => "LVDS_25"
    )
    port map (
        O => o_buf,
        I => diff_p,
        IB => diff_n
    );

--  your_instance_name : mult
--  port map
--   (-- Clock in ports
--    CLK_IN1 => clk,
--    -- Clock out ports
--    CLK_OUT1 => fast_clk);

--  process(clk, rst)
--      variable counter : unsigned(31 downto 0) := (others => '0');
--      type lut_type is array (0 to 255) of integer range 0 to 255;
--      variable lut : lut_type := (127,130,133,136,139,142,145,148,151,154,157,160,163,166,169,172,175,178,181,184,186,189,192,194,197,200,202,205,207,209,212,214,216,218,221,223,225,227,229,230,232,234,235,237,239,240,241,243,244,245,246,247,248,249,250,250,251,252,252,253,253,253,253,253,254,253,253,253,253,253,252,252,251,250,250,249,248,247,246,245,244,243,241,240,239,237,235,234,232,230,229,227,225,223,221,218,216,214,212,209,207,205,202,200,197,194,192,189,186,184,181,178,175,172,169,166,163,160,157,154,151,148,145,142,139,136,133,130,127,123,120,117,114,111,108,105,102,99,96,93,90,87,84,81,78,75,72,69,67,64,61,59,56,53,51,48,46,44,41,39,37,35,32,30,28,26,24,23,21,19,18,16,14,13,12,10,9,8,7,6,5,4,3,3,2,1,1,0,0,0,0,0,0,0,0,0,0,0,1,1,2,3,3,4,5,6,7,8,9,10,12,13,14,16,18,19,21,23,24,26,28,30,32,35,37,39,41,44,46,48,51,53,56,59,61,64,67,69,72,75,78,81,84,87,90,93,96,99,102,105,108,111,114,117,120,123);
--      variable lut_pos : unsigned(7 downto 0) := (others => '0');
--  begin
--      if(rst = '0') then
--          counter := (others => '0');
--          lut_pos := (others => '0');
--      elsif(rising_edge(clk)) then
--          if(counter = 50000000/6400) then
--              dac <= std_logic_vector(to_unsigned(lut(to_integer(lut_pos)), 8));
--              lut_pos := lut_pos + 1;
--              counter := (others => '0');
--          else
--              counter := counter + 1;
--          end if;
--      end if;
--  end process;


    process(clk, rst)
        variable counter : unsigned(31 downto 0) := (others => '0');
    begin
        if(rst = '0') then
            counter := (others => '0');
            count <= (others => '0');
            total <= (others => '0');
            leds <= (others => '0');
        elsif(rising_edge(clk)) then
            if(counter = 1) then
                counter := (others => '0');
                clk_buffer <= not clk_buffer;
                o <= o_buf;
                if(o_buf = '1') then
                    total <= total + 1;
                end if;
                if(count = 100000000/(44000*64)) then
                    leds <= std_logic_vector(total(7 downto 0));
                    total <= (others => '0');
                    count <= (others => '0');
                    dac <= std_logic_vector(total(7 downto 0));
                else
                    count <= count + 1;
                end if;
            else
                counter := counter + 1;
            end if;
        end if;
    end process;

end Behavioral;