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May 29th, 2016
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VHDL 1.35 KB | None | 0 0
  1. begin  -- process p _state_machine
  2. if ext_reset = '1   ' then  -- asynchronous reset (active high)
  3. gamelogic_state <= IDLE;   
  4. elsif clk25'event   and clk25 = '1' then  -- rising clock edge
  5. case gamelogic_state is
  6.        
  7. when IDLE =>       
  8. if tick = ' 1' then
  9.    
  10. gamelogic_state <=  CHECK;
  11. end if;    
  12. when CHECK =>      
  13.    
  14. if (check_done_int =    '1') and (nochange_int = '1') and (crashed_int =
  15. '0') then      
  16.    
  17. gamelogic_state <=  HEAD_DATA;
  18. elsif (check_done_int = '1') and (nochange_int = '0') and (crashed_int =
  19. '0') then      
  20. gamelogic_state <=  CORNER;
  21. elsif (crashed_int =    '1') then
  22. gamelogic_state <=  RESET;
  23.        
  24. else       
  25. gamelogic_state <=  CHECK;
  26.        
  27. end if;    
  28. when    HEAD_DATA =>   
  29. if  (head_addr_done_int = '1') then
  30.        
  31.     gamelogic_state <=  HEAD_WRITE;
  32. end if;
  33. when    HEAD_WRITE =>  
  34. if  (head_done_int =1') then
  35.     gamelogic_state <=  IDLE;
  36. end if;
  37.        
  38. when    CORNER =>  
  39. if  (corner_done_int = '1') then
  40.     gamelogic_state <=  IDLE;
  41. end if;
  42. when    TAIL_READ =>   
  43.    
  44. if  (tailread_done_int = '1') then
  45.     gamelogic_state <=  TAIL_WRITE;
  46. elsif (tail_done_int    = '1') then
  47.        
  48.     gamelogic_state <=  SCORE;
  49. end if;
  50. when    TAIL_WRITE =>  
  51.    
  52. if  (tailwrite_done_int = '1') then
  53.     gamelogic_state <=  SCORE;
  54.    
  55. end if;
  56. when    SCORE =>   
  57. if  (score_done_int =   '1') then
  58.        
  59.     gamelogic_state <=  IDLE;
  60. end if;
  61. when    RESET =>   
  62.        
  63. if  (reset_done_int =   '1') then
  64.     gamelogic_state <=  IDLE;
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