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  1. Index: src/mess/drivers/a7150.c
  2. ===================================================================
  3. --- src/mess/drivers/a7150.c (revision 26850)
  4. +++ src/mess/drivers/a7150.c (working copy)
  5. @@ -4,28 +4,158 @@
  6.  
  7. 04/10/2009 Skeleton driver.
  8.  
  9. + TODO:
  10. +
  11. + - KGS (It's a uPD7220 controlled by a Z80, which from the main system, is controlled by an 8086. I don't even see the point of that.)
  12. + - A whole crapload of other controllers.
  13. +
  14. http://www.robotrontechnik.de/index.htm?/html/computer/a7150.htm
  15.  
  16. + Additional, more helpful docs here:
  17. +
  18. + http://www.tiffe.de/Robotron/MMS16/
  19. +
  20. ****************************************************************************/
  21.  
  22. #include "emu.h"
  23. +
  24. #include "cpu/i86/i86.h"
  25. +#include "machine/i8251.h"
  26. +#include "machine/i8255.h"
  27. +#include "machine/pit8253.h"
  28. +#include "machine/pic8259.h"
  29.  
  30. +#include "cpu/z80/z80.h"
  31. +#include "machine/z80ctc.h"
  32. +#include "machine/z80sio.h"
  33.  
  34. +#include "video/upd7220.h"
  35. +
  36. class a7150_state : public driver_device
  37. {
  38. public:
  39. a7150_state(const machine_config &mconfig, device_type type, const char *tag)
  40. : driver_device(mconfig, type, tag) ,
  41. - m_maincpu(*this, "maincpu") { }
  42. + m_maincpu(*this, "maincpu"),
  43. + m_pit8253(*this, "pit8253"),
  44. + m_pic8259(*this, "pic8259"),
  45. + m_gfxcpu(*this, "gfxcpu"),
  46. + m_upd7220(*this, "upd7220"),
  47. + m_video_ram(*this, "video_ram") { }
  48.  
  49. virtual void machine_reset();
  50. virtual void video_start();
  51. - UINT32 screen_update_a7150(screen_device &screen, bitmap_ind16 &bitmap, const rectangle &cliprect);
  52. +
  53. + DECLARE_READ8_MEMBER(a7150_ppi_r);
  54. + DECLARE_WRITE8_MEMBER(a7150_ppi_w);
  55. + DECLARE_READ8_MEMBER(a7150_pit_r);
  56. + DECLARE_WRITE8_MEMBER(a7150_pit_w);
  57. + DECLARE_READ8_MEMBER(a7150_pic_r);
  58. + DECLARE_WRITE8_MEMBER(a7150_pic_w);
  59. + DECLARE_READ8_MEMBER(a7150_i8251_r);
  60. + DECLARE_WRITE8_MEMBER(a7150_i8251_w);
  61. +
  62. required_device<cpu_device> m_maincpu;
  63. + required_device<pit8253_device> m_pit8253;
  64. + required_device<pic8259_device> m_pic8259;
  65. + //KGS stuff.
  66. + required_device<z80_device> m_gfxcpu;
  67. + required_device<upd7220_device> m_upd7220;
  68. + required_shared_ptr<UINT8> m_video_ram;
  69. };
  70.  
  71. +Z80CTC_INTERFACE(a7150_z80ctc_interface)
  72. +{
  73. + DEVCB_NULL,
  74. + DEVCB_NULL,
  75. + DEVCB_NULL,
  76. + DEVCB_NULL
  77. +};
  78.  
  79. +const i8251_interface a7150_i8251_interface =
  80. +{
  81. + DEVCB_NULL,
  82. + DEVCB_NULL,
  83. + DEVCB_NULL,
  84. + DEVCB_NULL,
  85. + DEVCB_NULL,
  86. + DEVCB_NULL,
  87. + DEVCB_NULL
  88. +};
  89. +
  90. +const z80sio_interface a7150_z80sio_interface =
  91. +{
  92. + DEVCB_NULL,
  93. + DEVCB_NULL,
  94. + DEVCB_NULL,
  95. + DEVCB_NULL,
  96. + DEVCB_NULL,
  97. + DEVCB_NULL
  98. +};
  99. +
  100. +I8255_INTERFACE(a7150_ppi8255_interface)
  101. +{
  102. + DEVCB_NULL,
  103. + DEVCB_NULL,
  104. + DEVCB_NULL,
  105. + DEVCB_NULL,
  106. + DEVCB_NULL,
  107. + DEVCB_NULL
  108. +};
  109. +
  110. +//The clock rate given here is a sheer guess based on the PC/XT, which this thing tries to be compatible with.
  111. +const pit8253_interface a7150_pit8253_config =
  112. +{
  113. + {
  114. + {
  115. + 4915000,
  116. + DEVCB_NULL,
  117. + DEVCB_DEVICE_LINE_MEMBER("pic8259", pic8259_device, ir2_w)
  118. + },
  119. + {
  120. + 4915000,
  121. + DEVCB_NULL,
  122. + DEVCB_NULL
  123. + },
  124. + {
  125. + 4915000,
  126. + DEVCB_NULL,
  127. + DEVCB_NULL
  128. + }
  129. + }
  130. +};
  131. +
  132. +static UPD7220_DISPLAY_PIXELS( abg_display_pixels )
  133. +{
  134. + a7150_state *state = device->machine().driver_data<a7150_state>();
  135. + const rgb_t *palette = palette_entry_list_raw(bitmap.palette());
  136. +
  137. + int xi,gfx;
  138. + UINT8 pen;
  139. +
  140. + gfx = state->m_video_ram[address & 0xffff];
  141. +
  142. + for(xi=0;xi<8;xi++)
  143. + {
  144. + pen = ((gfx >> xi) & 1) ? 7 : 0;
  145. +
  146. + bitmap.pix32(y, x + xi) = palette[pen];
  147. + }
  148. +}
  149. +
  150. +static UPD7220_DRAW_TEXT_LINE( abg_draw_text )
  151. +{
  152. +}
  153. +
  154. +static UPD7220_INTERFACE( abg_intf )
  155. +{
  156. + abg_display_pixels,
  157. + abg_draw_text,
  158. + DEVCB_NULL,
  159. + DEVCB_NULL,
  160. + DEVCB_NULL
  161. +};
  162. +
  163. static ADDRESS_MAP_START(a7150_mem, AS_PROGRAM, 16, a7150_state)
  164. ADDRESS_MAP_UNMAP_HIGH
  165. AM_RANGE(0x00000,0xeffff) AM_RAM
  166. @@ -32,6 +162,106 @@
  167. AM_RANGE(0xf8000,0xfffff) AM_ROM AM_REGION("user1", 0)
  168. ADDRESS_MAP_END
  169.  
  170. +static ADDRESS_MAP_START( upd7220_map, AS_0, 8, a7150_state)
  171. + ADDRESS_MAP_GLOBAL_MASK(0xffff)
  172. + AM_RANGE(0x00000, 0x0ffff) AM_RAM AM_SHARE("video_ram")
  173. +ADDRESS_MAP_END
  174. +
  175. +//Ugly, ugly hacks. These also assume the PPI addresses are only partially decoded, which they probably are.
  176. +
  177. +READ8_MEMBER(a7150_state::a7150_ppi_r)
  178. +{
  179. + i8255_device* dev = machine().device<i8255_device>("ppi8255");
  180. + return dev->read(space, offset >> 1, mem_mask);
  181. +}
  182. +
  183. +WRITE8_MEMBER(a7150_state::a7150_ppi_w)
  184. +{
  185. + i8255_device* dev = machine().device<i8255_device>("ppi8255");
  186. + dev->write(space, offset >> 1, data, mem_mask);
  187. +}
  188. +
  189. +READ8_MEMBER(a7150_state::a7150_i8251_r)
  190. +{
  191. + i8251_device* dev = machine().device<i8251_device>("usart8251");
  192. + switch(offset >> 1)
  193. + {
  194. + case 0:
  195. + {
  196. + return dev->data_r(space, 0, mem_mask);
  197. + break;
  198. + }
  199. + case 1:
  200. + {
  201. + return dev->status_r(space, 0, mem_mask);
  202. + break;
  203. + }
  204. + }
  205. + return 0;
  206. +}
  207. +
  208. +WRITE8_MEMBER(a7150_state::a7150_i8251_w)
  209. +{
  210. + i8251_device* dev = machine().device<i8251_device>("usart8251");
  211. + switch(offset >> 1)
  212. + {
  213. + case 0:
  214. + {
  215. + dev->data_w(space, 0, data, mem_mask);
  216. + break;
  217. + }
  218. + case 1:
  219. + {
  220. + dev->control_w(space, 0, data, mem_mask);
  221. + break;
  222. + }
  223. + }
  224. +}
  225. +
  226. +READ8_MEMBER(a7150_state::a7150_pic_r)
  227. +{
  228. + pic8259_device* dev = machine().device<pic8259_device>("pic8259");
  229. + return dev->read(space, offset >> 1, mem_mask);
  230. +}
  231. +
  232. +WRITE8_MEMBER(a7150_state::a7150_pic_w)
  233. +{
  234. + pic8259_device* dev = machine().device<pic8259_device>("pic8259");
  235. + dev->write(space, offset >> 1, data, mem_mask);
  236. +}
  237. +
  238. +READ8_MEMBER(a7150_state::a7150_pit_r)
  239. +{
  240. + return m_pit8253->read(space, offset >> 1, mem_mask);
  241. +}
  242. +
  243. +WRITE8_MEMBER(a7150_state::a7150_pit_w)
  244. +{
  245. + m_pit8253->write(space, offset >> 1, data, mem_mask);
  246. +}
  247. +
  248. +static ADDRESS_MAP_START(a7150_io, AS_IO, 16, a7150_state)
  249. + ADDRESS_MAP_UNMAP_HIGH
  250. + AM_RANGE(0x00c0,0x00c3) AM_READWRITE8(a7150_pic_r, a7150_pic_w, 0xffff)
  251. + AM_RANGE(0x00c8,0x00cf) AM_READWRITE8(a7150_ppi_r, a7150_ppi_w, 0xffff)
  252. + AM_RANGE(0x00d0,0x00d7) AM_READWRITE8(a7150_pit_r, a7150_pit_w, 0xffff)
  253. + AM_RANGE(0x00d8,0x00db) AM_READWRITE8(a7150_i8251_r, a7150_i8251_w, 0xffff)
  254. +ADDRESS_MAP_END
  255. +
  256. +static ADDRESS_MAP_START(a7150_gfxcpu_mem, AS_PROGRAM, 8, a7150_state)
  257. + ADDRESS_MAP_UNMAP_HIGH
  258. + AM_RANGE(0x0000,0x1fff) AM_ROM AM_REGION("user2", 0)
  259. + AM_RANGE(0x2000,0xffff) AM_RAM
  260. +ADDRESS_MAP_END
  261. +
  262. +static ADDRESS_MAP_START(a7150_gfxcpu_io, AS_IO, 8, a7150_state)
  263. + ADDRESS_MAP_UNMAP_HIGH
  264. + ADDRESS_MAP_GLOBAL_MASK(0x1ffff)
  265. + AM_RANGE(0x0000,0x0003) AM_DEVREADWRITE("z80ctc", z80ctc_device, read, write)
  266. + AM_RANGE(0x0008,0x000b) AM_DEVREADWRITE("z80sio", z80sio_device, read, write)
  267. + AM_RANGE(0x0010,0x0011) AM_DEVREADWRITE("upd7220", upd7220_device, read, write)
  268. +ADDRESS_MAP_END
  269. +
  270. /* Input ports */
  271. static INPUT_PORTS_START( a7150 )
  272. INPUT_PORTS_END
  273. @@ -45,24 +275,36 @@
  274. {
  275. }
  276.  
  277. -UINT32 a7150_state::screen_update_a7150(screen_device &screen, bitmap_ind16 &bitmap, const rectangle &cliprect)
  278. -{
  279. - return 0;
  280. -}
  281. -
  282. static MACHINE_CONFIG_START( a7150, a7150_state )
  283. /* basic machine hardware */
  284. MCFG_CPU_ADD("maincpu", I8086, 4915000)
  285. MCFG_CPU_PROGRAM_MAP(a7150_mem)
  286. + MCFG_CPU_IO_MAP(a7150_io)
  287.  
  288. + MCFG_I8255_ADD("ppi8255", a7150_ppi8255_interface)
  289.  
  290. + MCFG_PIT8253_ADD("pit8253", a7150_pit8253_config)
  291. +
  292. + MCFG_PIC8259_ADD( "pic8259", INPUTLINE("maincpu",0), VCC, NULL )
  293. +
  294. + MCFG_I8251_ADD("usart8251", a7150_i8251_interface)
  295. +
  296. + MCFG_CPU_ADD("gfxcpu", Z80, 4915000) //Guessing up the wazoo here.
  297. + MCFG_CPU_PROGRAM_MAP(a7150_gfxcpu_mem)
  298. + MCFG_CPU_IO_MAP(a7150_gfxcpu_io)
  299. +
  300. + MCFG_Z80CTC_ADD("z80ctc", 4915000, a7150_z80ctc_interface) //More guessing.
  301. + MCFG_Z80SIO_ADD("z80sio", 4915000, a7150_z80sio_interface) //Even more guessing
  302. +
  303. + MCFG_UPD7220_ADD("upd7220", 4915000/4, abg_intf, upd7220_map)
  304. +
  305. /* video hardware */
  306. MCFG_SCREEN_ADD("screen", RASTER)
  307. - MCFG_SCREEN_REFRESH_RATE(50)
  308. + MCFG_SCREEN_REFRESH_RATE(58) //Turns out the original churned frames out at around 58 Hz.
  309. MCFG_SCREEN_VBLANK_TIME(ATTOSECONDS_IN_USEC(2500)) /* not accurate */
  310. MCFG_SCREEN_SIZE(640, 480)
  311. MCFG_SCREEN_VISIBLE_AREA(0, 640-1, 0, 480-1)
  312. - MCFG_SCREEN_UPDATE_DRIVER(a7150_state, screen_update_a7150)
  313. + MCFG_SCREEN_UPDATE_DEVICE("upd7220", upd7220_device, screen_update)
  314.  
  315. MCFG_PALETTE_LENGTH(2)
  316. MCFG_PALETTE_INIT_OVERRIDE(driver_device, black_and_white)
  317. @@ -73,6 +315,8 @@
  318. ROM_START( a7150 )
  319. ROM_REGION( 0x10000, "user1", ROMREGION_ERASEFF )
  320. ROM_LOAD( "a7150.rom", 0x0000, 0x8000, CRC(57855abd) SHA1(b58f1363623d2c3ff1221e449529ecaa22573bff))
  321. + ROM_REGION( 0x10000, "user2", ROMREGION_ERASEFF )
  322. + ROM_LOAD( "kgs.bin", 0x0000, 0x2000, CRC(403f4235) SHA1(d07ccd40f8b600651d513f588bcf1ea4f15ed094))
  323. ROM_END
  324.  
  325. /* Driver */
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