hazi

// TOPLEVEL///////////////////////////////////////////////////////////////
`timescale 1ns / 1ps
//////////////////////////////////////////////////////////////////////////////////
// Company: BME
// Engineer: Ecsedi Gergő, Szabó Patrik
//
// Create Date:    22:33:30 11/14/2014
// Design Name:
// Module Name:    toplevel
// Project Name:
// Target Devices:
// Tool versions:
// Description:
//
// Dependencies:
//
// Revision:
// Revision 0.01 - File Created
// Additional Comments:
//
//////////////////////////////////////////////////////////////////////////////////
module toplevel(
            input clk,
            input btn1,
            input sw6,
            input sw7,
            input rst,
            input urst,

            output txd,
            output [33:0] LANAL
 );
 reg[2:0] go;
 reg ujra;

 wire baud;
 wire btn_sign;
 wire rst_sign;
 wire rtsState;
wire urst_sign;
 wire wordBit;
 wire[1:0] word;
 wire[3:0] wordDigitSel;


pergesmentesito rstpergment (
        .clk(clk),
        .btn_in(rst),
        .btn_en(rst_sign)
);
pergesmentesito btnpergment(
        .clk(clk),
        .btn_in(btn1),
        .btn_en(btn_sign)
);
pergesmentesito urstpergment(
        .clk(clk),
        .btn_in(urst),
        .btn_en(urst_sign)
);
brgen brgenerator(
        .clk(clk),
        .rst(rst_sign ||ujra),
        .rate(sw7),
        .brout(baud)
);

cntr2_ascii counterWord(
        .clk(clk),
        .en( (wordDigitSel == 4'b1010) & !(go==0 ) &baud ),
        .rst(rst_sign||ujra),
        .out(word)
);
cntr4_kivalaszto counterDigit(
        .clk(clk),
        .en(baud & !(go==0 ) ),

        .rst(rst_sign||ujra),
        .parity(sw6),
        .out(wordDigitSel )
);
RTS rts(
        .clk(clk),
        .stop(rst_sign||ujra),
        .btn(btn_sign),
        .out(rtsState)
);
multiplexer mux(
        .sel(wordDigitSel ),
        .din(word),
        .outAscii(wordBit)
);

 always@(posedge clk)
    begin

        if(rst_sign)
            go<=0;
        else if( urst_sign && (go==0 || go==3'b101) )
                    begin go<=0; ujra<=1;  end
        else if(baud && (wordDigitSel == 4'b1010) && ~(go==3'b101) )
                begin go<=go+1; end
        else if(btn_sign && go==0 )
                 begin go<=1; ujra<=0; end

    end


assign txd = (go==0 || go==3'b101)? 1: wordBit;     //ha go==0, tehát ha nincs adás. akkor idle(magas).

assign LANAL[33] = clk;
assign LANAL[0] = btn1;
assign LANAL[1] = btn_sign;
assign LANAL[2] = sw6;          //parity
assign LANAL[3] = sw7;          //rate
assign LANAL[4] = rst_sign;
assign LANAL[5] = baud;
assign LANAL[6] = rtsState;
assign LANAL[7] = wordBit;
assign LANAL[9:8] = word;
assign LANAL[13:10] = wordDigitSel;
assign LANAL[14] = txd;
assign LANAL[17:15] = go;
assign LANAL[18]=urst;
assign LANAL[19]=urst_sign;
assign LANAL[32:20] = 0;

endmodule

//PERGESMENTESITO//////////////////////////////////////////////////////////////
`timescale 1ns / 1ps
module pergesmentesito(
    input clk,
    input btn_in,
    output btn_en
    );

    reg[1:0] perg;

    always@(posedge clk)
        perg <= {perg[0],btn_in};

    assign btn_en = perg[0] & perg[1];          //ha 00 vagy 11 akkor nem pereg

endmodule
//////BAUD-RATE-GENERATOR /////////////////////////////////////////////////////////
`timescale 1ns / 1ps
module brgen(
    input clk,
    input rst,
    input rate,
    output brout
     //output[12:0] brcntr   //debug
    );

reg[12:0] baudRate;
reg[12:0] baudRateCounter;


//BaudRate számláló
always@(posedge clk)
    if(rst || brout )
            baudRateCounter <= 0;
    else
            baudRateCounter <= baudRateCounter +1;

//baudRate= clock/sample*br  sample=1; br={9600, 19200} clock = 50 000 000
always@(posedge clk)
    baudRate <= (rate == 0) ? 5208 : 2604;  //9600 és 19200 Br


//assign brcntr = baudRateCounter;  //debug
assign brout = ( baudRateCounter == baudRate) ? 1 : 0;

endmodule

////////CNTR2BIT_ASCI KÓD GENERÁLÓ //////////////////////////////////////////////
`timescale 1ns / 1ps
module cntr2_ascii(
    input clk,
    input en,
    input rst,
    output [1:0] out
    );
reg[1:0] data;

always@(posedge clk)
begin
    if(rst )
        data<=2'b01;
    else if(en)
        data<=data+1;
end

assign out = data;
endmodule

////////////CNTR4BIT_MUXSELECTER //////////////////////////////////////////////
`timescale 1ns / 1ps

module cntr4_kivalaszto(
    input clk,
    input en,

    input rst,
     input parity,
    output [3:0] out
 );
reg[3:0] Q;


always@(posedge clk)
    begin
        if (rst)
            Q<=0;
        else
            if(en)
                    if(~parity & Q == 8)
                        Q<=Q + 2;
                    else if( Q ==10)
                        Q<=1;
                    else
                        Q<=Q+1;
        end

assign out = Q;

endmodule

///////////RTS////////////////////////////////////////////////////
`timescale 1ns / 1ps
module RTS(
    input clk,
    input stop,
    input btn,
    output out
    );
reg q;

always@(posedge clk)
begin
    if(btn & !stop)
        q<=1;
    else if(stop)
        q<=0;
end

assign out = q;
endmodule

///////////////MUX_16///////////////////////////////////////////////////////////////////////////
`timescale 1ns / 1ps
module multiplexer(
    input [3:0] sel,
    input [1:0] din,

    output outAscii
    );

reg rr;

always @ (*)
case (sel)
        4'b0000: rr <= 1;               //0
         4'b0001: rr <= 0;          //1
         4'b0010: rr <= din[0];         //2
         4'b0011: rr <= din[1];         //3
         4'b0100: rr <= ( (~din[0]) & (~din[1]) );          //4
         4'b0101: rr <= 0;          //5
         4'b0110: rr <= 0;          //6
         4'b0111: rr <= 1;          //7
         4'b1000: rr <= 1;          //8
         4'b1001: rr <= ~(din[0]^din[1]^( (~din[0]) & (~din[1]) ));         //9
         4'b1010: rr <= 1;          //10
        default: rr<=1;         //11!!!

endcase

assign outAscii = rr;

endmodule
///LANAL.UCF//////////////////////////////////
NET "LANAL<33>"     LOC = "C10"; #CLK2
NET "LANAL<32>"     LOC = "C15"; #CLK1


NET "LANAL<31>"     LOC = "T3";  #D31
NET "LANAL<30>"     LOC = "E10"; #D30
NET "LANAL<29>"     LOC = "N11"; #D29
NET "LANAL<28>"     LOC = "C11"; #D28
NET "LANAL<27>"     LOC = "P10"; #D27
NET "LANAL<26>"     LOC = "D11"; #D26
NET "LANAL<25>"     LOC = "R10"; #D25
NET "LANAL<24>"     LOC = "C12"; #D24
NET "LANAL<23>"     LOC = "T7";  #D23
NET "LANAL<22>"     LOC = "D12"; #D22
NET "LANAL<21>"     LOC = "R7";  #D21
NET "LANAL<20>"     LOC = "E11"; #D20
NET "LANAL<19>"     LOC = "N6";  #D19
NET "LANAL<18>"     LOC = "B16"; #D18
NET "LANAL<17>"     LOC = "M6";  #D17
NET "LANAL<16>"     LOC = "R3"; #D16
NET "LANAL<15>"     LOC = "C16"; #D15
NET "LANAL<14>"     LOC = "D15"; #D14
NET "LANAL<13>"     LOC = "D16"; #D13
NET "LANAL<12>"     LOC = "E15"; #D12
NET "LANAL<11>"     LOC = "E16"; #D11
NET "LANAL<10>"     LOC = "F15"; #D10
NET "LANAL<9>"      LOC = "G15"; #D9
NET "LANAL<8>"      LOC = "G16"; #D8
NET "LANAL<7>"      LOC = "H15"; #D7
NET "LANAL<6>"      LOC = "H16"; #D6
NET "LANAL<5>"      LOC = "J16"; #D5
NET "LANAL<4>"      LOC = "K16"; #D4
NET "LANAL<3>"      LOC = "K15"; #D3
NET "LANAL<2>"      LOC = "L15"; #D2
NET "LANAL<1>"      LOC = "N9";  #D1
NET "LANAL<0>"      LOC = "M11"; #D0

/////////////////////PINS.UCF/////////////////////////////////
NET clk LOC = T9;
NET rst LOC = M13;
NET btn1 LOC = M14;
NET sw6 LOC = K14;
NET sw7 LOC = K13;
NET txd LOC = R6;
NET urst LOC = L14;