`timescale 1ns/1ps
module myfsm (input clk, reset, in, output reg out);
  parameter S0 = 0;
  parameter S1 = 1;
  parameter S2 = 2;
  parameter S3 = 3;
  reg [1:0] state, next_state;
  // new state assignment
  always @(posedge clk)
    if (reset) state <= #1 S0;
    else state <= #1 next_state;
  // output assignment
  always @(in or state)
    out <= #1 (state [1] & state [0]);
  // next state computation
  always @(in or state)
    case (state)
      S0: if (in) next_state <= #1 S1;
        else next_state <= #1 S0;
      S1:  if (in) next_state <= #1 S2;
        else next_state <= #1 S0;
      S2: if (in) next_state <= #1 S3;
        else next_state <= #1 S0;
      S3: if (in) next_state <= #1 S3;
        else next_state <= #1 S0;
     endcase
endmodule