/*
create_clock -period 3.333 -name ref_clk -waveform {0.000 1.666} [get_ports ref_clk_p]
set_input_delay -clock ref_clk -max 0.200 [get_ports sysref_in]
set_input_delay -clock ref_clk -min -0.500 [get_ports sysref_in]
*/

module clock_test (
	input ref_clk_p,
	input ref_clk_n,
	input sysref_in_p,
	input sysref_in_n,
	output data_out
);

wire ref_clk;
wire div_clk;

wire sysref_in;
reg sysref_r;
reg out;

IBUFDS_GTE2 i_ibufds_ref_clk (
    .CEB (1'd0),
    .I (ref_clk_p),
    .IB (ref_clk_n),
    .O (ref_clk),
    .ODIV2 ());
/*
IBUFDS i_ibufds_ref_clk (
    .I(ref_clk_p),
    .IB(ref_clk_n),
    .O(ref_clk)
);*/

BUFH i_bufh_divclk (
    .I(ref_clk),
    .O(div_clk));

/*
BUFG i_bufg_divclk (
    .I(ref_clk),
    .O(div_clk));
*/

IBUFDS i_ibufds_sysref (
    .I(sysref_in_p),
    .IB(sysref_in_n),
    .O(sysref_in)
);

always @(posedge div_clk) begin
    sysref_r <= sysref_in;
    out <= out ^ sysref_r;
end

assign data_out = out;

endmodule