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By: a guest on Jan 2nd, 2012  |  syntax: VeriLog  |  size: 0.50 KB  |  views: 134  |  expires: Never
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  1.         // synthesis attribute RLOC of BITMUX[0] is X0Y0
  2.         // synthesis attribute RLOC of BITMUX[1] is X2Y2
  3.  
  4.         genvar i;
  5.         generate       
  6.                 for(i=0; i<WIDTH; i = i+1) begin:BITMUX
  7.                         Mux16to1_raw bitmux (
  8.                                 .in0(in0[i]), .in1(in1[i]), .in2(in2[i]), .in3(in3[i]),
  9.                                 .in4(in4[i]), .in5(in5[i]), .in6(in6[i]), .in7(in7[i]),
  10.                                 .in8(in8[i]), .in9(in9[i]), .ina(ina[i]), .inb(inb[i]),
  11.                                 .inc(inc[i]), .ind(ind[i]), .ine(ine[i]), .inf(inf[i]),
  12.                                 .select(select),
  13.                                 .out(out[i])
  14.                                 );
  15.                 end
  16.         endgenerate
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