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  1. /*
  2. * Copyright 2011 Freescale Semiconductor, Inc.
  3. * Copyright 2011 Linaro Ltd.
  4. *
  5. * The code contained herein is licensed under the GNU General Public
  6. * License. You may obtain a copy of the GNU General Public License
  7. * Version 2 or later at the following locations:
  8. *
  9. * http://www.opensource.org/licenses/gpl-license.html
  10. * http://www.gnu.org/copyleft/gpl.html
  11. */
  12.  
  13. /dts-v1/;
  14. #include "imx6q.dtsi"
  15.  
  16. / {
  17. model = "i.MX6 Quad starterkit";
  18. compatible = "sk,imx6q-sk", "fsl,imx6q-sabresd", "fsl,imx6q";
  19.  
  20. aliases {
  21. mxcfb0 = &mxcfb1;
  22. mxcfb1 = &mxcfb2;
  23. mxcfb2 = &mxcfb3;
  24. mxcfb3 = &mxcfb4;
  25. };
  26.  
  27. memory {
  28. reg = <0x10000000 0x40000000>;
  29. };
  30.  
  31. regulators {
  32. compatible = "simple-bus";
  33.  
  34. reg_3p3v: 3p3v {
  35. compatible = "regulator-fixed";
  36. regulator-name = "3P3V";
  37. regulator-min-microvolt = <3300000>;
  38. regulator-max-microvolt = <3300000>;
  39. regulator-always-on;
  40. };
  41.  
  42. reg_usb_otg_vbus: usb_otg_vbus {
  43. compatible = "regulator-fixed";
  44. regulator-name = "usb_otg_vbus";
  45. regulator-min-microvolt = <5000000>;
  46. regulator-max-microvolt = <5000000>;
  47. gpio = <&gpio1 28 0>;
  48. enable-active-high;
  49. };
  50. };
  51. /*
  52. soc {
  53. busfreq {
  54. fsl,med_ddr_freq = <400000000>;
  55. };
  56. };
  57. */
  58. sound {
  59. compatible = "sk,sk-tlv320";
  60. model = "sk-tlv320";
  61. ssi-controller = <&ssi2>;
  62. audio-codec = <&codec>;
  63. audio-routing =
  64. "MICIN", "Mic Jack",
  65. "Headphone Jack", "LHPOUT",
  66. "Headphone Jack", "RHPOUT";
  67. mux-int-port = <2>;
  68. mux-ext-port = <5>;
  69. };
  70.  
  71. mxcfb1: fb@0 {
  72. compatible = "fsl,mxc_sdc_fb";
  73. disp_dev = "ldb";
  74. interface_pix_fmt = "RGB24";
  75. mode_str ="LDB-XGA";
  76. default_bpp = <16>;
  77. int_clk = <0>;
  78. late_init = <0>;
  79. status = "okay";
  80. };
  81.  
  82. mxcfb2: fb@1 {
  83. compatible = "fsl,mxc_sdc_fb";
  84. disp_dev = "hdmi";
  85. interface_pix_fmt = "RGB24";
  86. mode_str ="1920x1080M@60";
  87. default_bpp = <24>;
  88. int_clk = <0>;
  89. late_init = <0>;
  90. status = "okay";
  91. };
  92.  
  93. mxcfb3: fb@2 {
  94. compatible = "fsl,mxc_sdc_fb";
  95. disp_dev = "lcd";
  96. interface_pix_fmt = "RGB24";
  97. mode_str ="CLAA-WVGA";
  98. default_bpp = <16>;
  99. int_clk = <0>;
  100. late_init = <0>;
  101. status = "okay";
  102. };
  103.  
  104. mxcfb4: fb@3 {
  105. compatible = "fsl,mxc_sdc_fb";
  106. disp_dev = "ldb";
  107. interface_pix_fmt = "RGB24";
  108. mode_str ="LDB-XGA";
  109. default_bpp = <16>;
  110. int_clk = <0>;
  111. late_init = <0>;
  112. status = "okay";
  113. };
  114.  
  115. lcd@0 {
  116. compatible = "fsl,lcd";
  117. ipu_id = <0>;
  118. disp_id = <0>;
  119. default_ifmt = "RGB24";
  120. pinctrl-names = "default";
  121. pinctrl-0 = <&pinctrl_ipu1_1>;
  122. status = "okay";
  123. };
  124.  
  125. spi_lcd {
  126. compatible = "spi-gpio";
  127. gpio-sck = <&gpio1 1 0>;
  128. gpio-miso = <&gpio7 11 0>;
  129. gpio-mosi = <&gpio1 2 0>;
  130. cs-gpios = <&gpio4 15 0>;
  131. num-chipselects = <1>;
  132. #address-cells = <1>;
  133. #size-cells = <0>;
  134. status = "disabled";
  135.  
  136. tsc2046@0 {
  137. compatible = "ti,tsc2046";
  138. reg = <0>;
  139. spi-max-frequency = <1000000>;
  140. /* pen irq is GPIO1_8 */
  141. interrupt-parent = <&gpio1>;
  142. interrupts = <8 0x2>;
  143. pendown-gpio = <&gpio1 8 0>;
  144. vcc-supply = <&reg_3p3v>;
  145.  
  146. ti,x-min = <150>;
  147. ti,x-max = <3830>;
  148. ti,y-min = <190>;
  149. ti,y-max = <3830>;
  150.  
  151. linux,wakeup;
  152. };
  153. };
  154.  
  155. sound-hdmi {
  156. compatible = "fsl,imx6q-audio-hdmi",
  157. "fsl,imx-audio-hdmi";
  158. model = "imx-audio-hdmi";
  159. hdmi-controller = <&hdmi_audio>;
  160. };
  161.  
  162. sound-spdif {
  163. compatible = "fsl,imx-audio-spdif",
  164. "fsl,imx-sabreauto-spdif";
  165. model = "imx-spdif";
  166. spdif-controller = <&spdif>;
  167. spdif-out;
  168. };
  169.  
  170. v4l2_cap_0 {
  171. compatible = "fsl,imx6q-v4l2-capture";
  172. ipu_id = <0>;
  173. csi_id = <0>;
  174. mclk_source = <0>;
  175. status = "okay";
  176. };
  177.  
  178. v4l2_out {
  179. compatible = "fsl,mxc_v4l2_output";
  180. status = "okay";
  181. };
  182. };
  183.  
  184. &audmux {
  185. status = "okay";
  186. pinctrl-names = "default";
  187. pinctrl-0 = <&pinctrl_audmux_sk>;
  188. };
  189.  
  190. &ecspi1 {
  191. fsl,spi-num-chipselects = <1>;
  192. cs-gpios = <&gpio5 25 0>;
  193. pinctrl-names = "default";
  194. pinctrl-0 = <&pinctrl_ecspi1_sk>;
  195. status = "okay";
  196.  
  197. tsc2046@0 {
  198. compatible = "ti,tsc2046";
  199. reg = <0>;
  200. spi-max-frequency = <1000000>;
  201. /* pen irq is GPIO1_7 */
  202. interrupt-parent = <&gpio1>;
  203. interrupts = <7 0x2>;
  204. pendown-gpio = <&gpio1 7 0>;
  205. vcc-supply = <&reg_3p3v>;
  206.  
  207. ti,x-min = <150>;
  208. ti,x-max = <3830>;
  209. ti,y-min = <190>;
  210. ti,y-max = <3830>;
  211.  
  212. linux,wakeup;
  213. };
  214. };
  215.  
  216. &ecspi4 {
  217. fsl,spi-num-chipselects = <1>;
  218. cs-gpios = <&gpio3 29 0>;
  219. pinctrl-names = "default";
  220. pinctrl-0 = <&pinctrl_ecspi4_sk>;
  221. status = "disabled";
  222.  
  223. tsc2046@0 {
  224. compatible = "ti,tsc2046";
  225. reg = <0>;
  226. spi-max-frequency = <1000000>;
  227. /* pen irq is GPIO4_10 */
  228. interrupt-parent = <&gpio4>;
  229. interrupts = <10 0x2>;
  230. pendown-gpio = <&gpio4 10 0>;
  231. vcc-supply = <&reg_3p3v>;
  232.  
  233. ti,x-min = <150>;
  234. ti,x-max = <3830>;
  235. ti,y-min = <190>;
  236. ti,y-max = <3830>;
  237.  
  238. linux,wakeup;
  239. };
  240. };
  241.  
  242. &fec {
  243. pinctrl-names = "default";
  244. pinctrl-0 = <&pinctrl_enet_sk>;
  245. phy-mode = "rgmii";
  246. phy-reset-gpios = <&gpio1 25 0>;
  247. status = "okay";
  248. };
  249.  
  250. &flexcan1 {
  251. pinctrl-names = "default";
  252. pinctrl-0 = <&pinctrl_flexcan1_sk>;
  253. status = "okay";
  254. };
  255.  
  256. &flexcan2 {
  257. pinctrl-names = "default";
  258. pinctrl-0 = <&pinctrl_flexcan2_sk>;
  259. status = "okay";
  260. };
  261.  
  262. &gpmi {
  263. pinctrl-names = "default";
  264. pinctrl-0 = <&pinctrl_gpmi_nand_1>;
  265. status = "okay";
  266.  
  267. partition@0 {
  268. label = "bootloader";
  269. reg = <0x0000000 0x01000000>;
  270. };
  271.  
  272. partition@1000000 {
  273. label = "environment";
  274. reg = <0x01000000 0x00200000>;
  275. };
  276.  
  277. partition@1200000 {
  278. label = "kernel";
  279. reg = <0x01200000 0x06400000>;
  280. };
  281.  
  282. partition@7600000 {
  283. label = "filesystem";
  284. reg = <0x07600000 0x78A00000>;
  285. };
  286. };
  287.  
  288. &hdmi_audio {
  289. status = "okay";
  290. };
  291.  
  292. &hdmi_cec {
  293. pinctrl-names = "default";
  294. pinctrl-0 = <&pinctrl_hdmi_cec_2>;
  295. status = "okay";
  296. };
  297.  
  298. &hdmi_core {
  299. ipu_id = <0>;
  300. disp_id = <1>;
  301. status = "okay";
  302. };
  303.  
  304. &hdmi_video {
  305. pinctrl-names = "default";
  306. pinctrl-0 = <&pinctrl_hdmi_hdcp_1>;
  307. fsl,phy_reg_vlev = <0x0294>;
  308. fsl,phy_reg_cksymtx = <0x800d>;
  309. fsl,hdcp;
  310. status = "okay";
  311. };
  312.  
  313. &i2c1 {
  314. status = "okay";
  315. clock-frequency = <100000>;
  316. pinctrl-names = "default";
  317. pinctrl-0 = <&pinctrl_i2c1_2>;
  318.  
  319. codec: tlv320aic23@1a {
  320. compatible = "ti,tlv320aic23";
  321. reg = <0x1a>;
  322. clocks = <&clks 200>;
  323. clock-frequency = <12000000>;
  324. };
  325.  
  326. adv7180: adv7180@21 {
  327. compatible = "adv,adv7180";
  328. reg = <0x21>;
  329. pinctrl-names = "default";
  330. pinctrl-0 = <&pinctrl_ipu1_2>;
  331. clocks = <&clks 201>;
  332. clock-names = "csi_mclk";
  333. DOVDD-supply = <&reg_3p3v>;
  334. AVDD-supply = <&reg_3p3v>;
  335. DVDD-supply = <&reg_3p3v>;
  336. PVDD-supply = <&reg_3p3v>;
  337. pwn-gpios = <&gpio7 6 0>;
  338. csi_id = <0>;
  339. mclk = <24000000>;
  340. mclk_source = <0>;
  341. cvbs = <1>;
  342. };
  343. };
  344.  
  345. &iomuxc {
  346. pinctrl-names = "default";
  347. pinctrl-0 = <&pinctrl_hog>;
  348.  
  349. hog {
  350. pinctrl_hog: hoggrp {
  351. fsl,pins = <
  352. /* SD1_DET */
  353. MX6QDL_PAD_SD4_DAT1__GPIO2_IO09 0x80000000
  354. /* SD2_DET */
  355. MX6QDL_PAD_SD4_DAT3__GPIO2_IO11 0x80000000
  356. /* LVDS0 TS-CS */
  357. MX6QDL_PAD_CSI0_DAT7__GPIO5_IO25 0x80000000
  358. /* LVDS0 TS-PENIRQ */
  359. MX6QDL_PAD_GPIO_7__GPIO1_IO07 0x80000000
  360. /* LVDS1 TS-CS */
  361. MX6QDL_PAD_EIM_D29__GPIO3_IO29 0x80000000
  362. /* LVDS1 TS-PENIRQ */
  363. MX6QDL_PAD_KEY_COL2__GPIO4_IO10 0x80000000
  364. /* LCD-SPI CLK */
  365. MX6QDL_PAD_GPIO_1__GPIO1_IO01 0x80000000
  366. /* LCD-SPI MISO */
  367. MX6QDL_PAD_GPIO_16__GPIO7_IO11 0x80000000
  368. /* LCD-SPI MOSI */
  369. MX6QDL_PAD_GPIO_2__GPIO1_IO02 0x80000000
  370. /* LCD-SPI TS-CS */
  371. MX6QDL_PAD_KEY_ROW4__GPIO4_IO15 0x80000000
  372. /* LCD-SPI TS-PENIRQ */
  373. MX6QDL_PAD_GPIO_8__GPIO1_IO08 0x80000000
  374. /* ETH_RESET */
  375. MX6QDL_PAD_ENET_CRS_DV__GPIO1_IO25 0x80000000
  376. /* AUDIO_MCLK */
  377. MX6QDL_PAD_NANDF_CS2__CCM_CLKO2 0x80000000
  378. /* USB0_PWR */
  379. MX6QDL_PAD_ENET_TX_EN__GPIO1_IO28 0x80000000
  380. /* CSI PD */
  381. MX6QDL_PAD_SD3_DAT2__GPIO7_IO06 0x80000000
  382. >;
  383. };
  384. };
  385.  
  386. audmux {
  387. pinctrl_audmux_sk: audmux-sk {
  388. fsl,pins = <
  389. MX6QDL_PAD_KEY_COL0__AUD5_TXC 0x130b0
  390. MX6QDL_PAD_KEY_ROW0__AUD5_TXD 0x130b0
  391. MX6QDL_PAD_KEY_COL1__AUD5_TXFS 0x130b0
  392. MX6QDL_PAD_KEY_ROW1__AUD5_RXD 0x130b0
  393. >;
  394. };
  395. };
  396.  
  397. ecspi1 {
  398. pinctrl_ecspi1_sk: ecspi1grp-sk {
  399. fsl,pins = <
  400. MX6QDL_PAD_CSI0_DAT4__ECSPI1_SCLK 0x100b1
  401. MX6QDL_PAD_CSI0_DAT5__ECSPI1_MOSI 0x100b1
  402. MX6QDL_PAD_CSI0_DAT6__ECSPI1_MISO 0x100b1
  403. >;
  404. };
  405. };
  406.  
  407. ecspi4 {
  408. pinctrl_ecspi4_sk: ecspi4grp-sk {
  409. fsl,pins = <
  410. MX6QDL_PAD_EIM_D22__ECSPI4_MISO 0x100b1
  411. MX6QDL_PAD_EIM_D28__ECSPI4_MOSI 0x100b1
  412. MX6QDL_PAD_EIM_D21__ECSPI4_SCLK 0x100b1
  413. >;
  414. };
  415. };
  416.  
  417. enet {
  418. pinctrl_enet_sk: enetgrp-sk {
  419. fsl,pins = <
  420. MX6QDL_PAD_ENET_MDIO__ENET_MDIO 0x1b0b0
  421. MX6QDL_PAD_ENET_MDC__ENET_MDC 0x1b0b0
  422. MX6QDL_PAD_RGMII_TXC__RGMII_TXC 0x1b0b0
  423. MX6QDL_PAD_RGMII_TD0__RGMII_TD0 0x1b0b0
  424. MX6QDL_PAD_RGMII_TD1__RGMII_TD1 0x1b0b0
  425. MX6QDL_PAD_RGMII_TD2__RGMII_TD2 0x1b0b0
  426. MX6QDL_PAD_RGMII_TD3__RGMII_TD3 0x1b0b0
  427. MX6QDL_PAD_RGMII_TX_CTL__RGMII_TX_CTL 0x1b0b0
  428. MX6QDL_PAD_ENET_REF_CLK__ENET_TX_CLK 0x1b0b0
  429. MX6QDL_PAD_RGMII_RXC__RGMII_RXC 0x1b0b0
  430. MX6QDL_PAD_RGMII_RD0__RGMII_RD0 0x1b0b0
  431. MX6QDL_PAD_RGMII_RD1__RGMII_RD1 0x1b0b0
  432. MX6QDL_PAD_RGMII_RD2__RGMII_RD2 0x1b0b0
  433. MX6QDL_PAD_RGMII_RD3__RGMII_RD3 0x1b0b0
  434. MX6QDL_PAD_RGMII_RX_CTL__RGMII_RX_CTL 0x1b0b0
  435. >;
  436. };
  437. };
  438.  
  439. flexcan1 {
  440. pinctrl_flexcan1_sk: flexcan1grp-sk {
  441. fsl,pins = <
  442. MX6QDL_PAD_SD3_CLK__FLEXCAN1_RX 0x80000000
  443. MX6QDL_PAD_SD3_CMD__FLEXCAN1_TX 0x80000000
  444. >;
  445. };
  446. };
  447.  
  448. flexcan2 {
  449. pinctrl_flexcan2_sk: flexcan2grp-sk {
  450. fsl,pins = <
  451. MX6QDL_PAD_SD3_DAT1__FLEXCAN2_RX 0x80000000
  452. MX6QDL_PAD_SD3_DAT0__FLEXCAN2_TX 0x80000000
  453. >;
  454. };
  455. };
  456.  
  457. spdif {
  458. pinctrl_spdif_sk: spdifgrp-sk {
  459. fsl,pins = <
  460. MX6QDL_PAD_GPIO_17__SPDIF_OUT 0x1b0b0
  461. >;
  462. };
  463. };
  464.  
  465. usdhc1 {
  466. pinctrl_usdhc1_sk: usdhc1grp-sk {
  467. fsl,pins = <
  468. MX6QDL_PAD_SD1_CMD__SD1_CMD 0x17059
  469. MX6QDL_PAD_SD1_CLK__SD1_CLK 0x10059
  470. MX6QDL_PAD_SD1_DAT0__SD1_DATA0 0x17059
  471. MX6QDL_PAD_SD1_DAT1__SD1_DATA1 0x17059
  472. MX6QDL_PAD_SD1_DAT2__SD1_DATA2 0x17059
  473. MX6QDL_PAD_SD1_DAT3__SD1_DATA3 0x17059
  474. >;
  475. };
  476. };
  477.  
  478. usdhc2 {
  479. pinctrl_usdhc2_sk: usdhc2grp-sk {
  480. fsl,pins = <
  481. MX6QDL_PAD_SD2_CMD__SD2_CMD 0x17059
  482. MX6QDL_PAD_SD2_CLK__SD2_CLK 0x10059
  483. MX6QDL_PAD_SD2_DAT0__SD2_DATA0 0x17059
  484. MX6QDL_PAD_SD2_DAT1__SD2_DATA1 0x17059
  485. MX6QDL_PAD_SD2_DAT2__SD2_DATA2 0x17059
  486. MX6QDL_PAD_SD2_DAT3__SD2_DATA3 0x17059
  487. >;
  488. };
  489. };
  490. };
  491.  
  492. &ldb {
  493. ipu_id = <1>;
  494. disp_id = <0>;
  495. ext_ref = <1>;
  496. mode = "sep0";
  497. sec_ipu_id = <1>;
  498. sec_disp_id = <1>;
  499. status = "okay";
  500. };
  501.  
  502. &pcie {
  503. status = "okay";
  504. };
  505.  
  506. &sata {
  507. status = "okay";
  508. };
  509.  
  510. &spdif {
  511. pinctrl-names = "default";
  512. pinctrl-0 = <&pinctrl_spdif_sk>;
  513. status = "okay";
  514. };
  515.  
  516. &ssi2 {
  517. fsl,mode = "i2s-slave";
  518. status = "okay";
  519. };
  520.  
  521. &uart1 {
  522. pinctrl-names = "default";
  523. pinctrl-0 = <&pinctrl_uart1_1>;
  524. status = "okay";
  525. };
  526.  
  527. &usbh1 {
  528. status = "okay";
  529. };
  530.  
  531. &usbotg {
  532. vbus-supply = <&reg_usb_otg_vbus>;
  533. pinctrl-names = "default";
  534. pinctrl-0 = <&pinctrl_usbotg_2>;
  535. disable-over-current;
  536. status = "okay";
  537. };
  538.  
  539. &usdhc1 {
  540. pinctrl-names = "default";
  541. pinctrl-0 = <&pinctrl_usdhc1_sk>;
  542. cd-gpios = <&gpio2 9 0>;
  543. vmmc-supply = <&reg_3p3v>;
  544. no-1-8-v;
  545. status = "okay";
  546. };
  547.  
  548. &usdhc2 {
  549. pinctrl-names = "default";
  550. pinctrl-0 = <&pinctrl_usdhc2_sk>;
  551. cd-gpios = <&gpio2 11 0>;
  552. vmmc-supply = <&reg_3p3v>;
  553. no-1-8-v;
  554. status = "okay";
  555. };
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