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  1. /*
  2.  * Copyright (C) 2011-2012 Freescale Semiconductor, Inc. All Rights Reserved.
  3.  *
  4.  * This program is free software; you can redistribute it and/or modify
  5.  * it under the terms of the GNU General Public License as published by
  6.  * the Free Software Foundation; either version 2 of the License, or
  7.  * (at your option) any later version.
  8.  
  9.  * This program is distributed in the hope that it will be useful,
  10.  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  11.  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  12.  * GNU General Public License for more details.
  13.  
  14.  * You should have received a copy of the GNU General Public License along
  15.  * with this program; if not, write to the Free Software Foundation, Inc.,
  16.  * 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA.
  17.  */
  18.  
  19. #include <linux/types.h>
  20. #include <linux/sched.h>
  21. #include <linux/delay.h>
  22. #include <linux/pm.h>
  23. #include <linux/interrupt.h>
  24. #include <linux/irq.h>
  25. #include <linux/init.h>
  26. #include <linux/input.h>
  27. #include <linux/nodemask.h>
  28. #include <linux/clk.h>
  29. #include <linux/platform_device.h>
  30. #include <linux/fsl_devices.h>
  31. #include <linux/spi/spi.h>
  32.  
  33. #include <linux/spi/spi_gpio.h>
  34. #include <linux/spi/ads7846.h>
  35.  
  36. #include <linux/spi/flash.h>
  37. #include <linux/i2c.h>
  38. #include <linux/i2c/pca953x.h>
  39. #include <linux/ata.h>
  40. #include <linux/mtd/mtd.h>
  41. #include <linux/mtd/map.h>
  42. #include <linux/mtd/partitions.h>
  43. #include <linux/regulator/consumer.h>
  44. #include <linux/pmic_external.h>
  45. #include <linux/pmic_status.h>
  46. #include <linux/ipu.h>
  47. #include <linux/mxcfb.h>
  48. #include <linux/pwm_backlight.h>
  49. #include <linux/fec.h>
  50. #include <linux/memblock.h>
  51. #include <linux/gpio.h>
  52. #include <linux/etherdevice.h>
  53. #include <linux/regulator/anatop-regulator.h>
  54. #include <linux/regulator/consumer.h>
  55. #include <linux/regulator/machine.h>
  56. #include <linux/regulator/fixed.h>
  57.  
  58. #include <mach/common.h>
  59. #include <mach/hardware.h>
  60. #include <mach/mxc_dvfs.h>
  61. #include <mach/memory.h>
  62. #include <mach/iomux-mx6q.h>
  63. #include <mach/iomux-mx6dl.h>
  64. #include <mach/imx-uart.h>
  65. #include <mach/viv_gpu.h>
  66. #include <mach/ahci_sata.h>
  67. #include <mach/ipu-v3.h>
  68. #include <mach/mxc_hdmi.h>
  69. #include <mach/mxc_asrc.h>
  70. #include <mach/mipi_dsi.h>
  71. #include <mach/mipi_csi2.h>
  72.  
  73. #include <asm/irq.h>
  74. #include <asm/setup.h>
  75. #include <asm/mach-types.h>
  76. #include <asm/mach/arch.h>
  77. #include <asm/mach/time.h>
  78.  
  79. #include "usb.h"
  80. #include "devices-imx6q.h"
  81. #include "crm_regs.h"
  82. #include "cpu_op-mx6.h"
  83.  
  84. #define MX6Q_SK_CEC IMX_GPIO_NR(4, 11)
  85.  
  86. #define MX6Q_SK_SD1_CD  IMX_GPIO_NR(2, 9)
  87. #define MX6Q_SK_SD2_CD  IMX_GPIO_NR(2, 11)
  88.  
  89. #define MX6Q_SK_ETH_RESET   IMX_GPIO_NR(1, 25)
  90. #define MX6DL_SK_ETH_RESET  IMX_GPIO_NR(1, 23)
  91.  
  92. #define MX6Q_SK_USB_OTG_PWR IMX_GPIO_NR(1, 28)
  93. #define MX6Q_SK_USB_HOST_PWR    IMX_GPIO_NR(7, 7)
  94.  
  95. #define MX6Q_SK_ECSPI1_CS0  IMX_GPIO_NR(5, 25)
  96. #define MX6Q_SK_ECSPI4_CS0  IMX_GPIO_NR(3, 29)
  97. #define MX6DL_SK_ECSPI4_CS0 IMX_GPIO_NR(3, 20)
  98.  
  99. #define MX6Q_SK_LVDS0_PENIRQ    IMX_GPIO_NR(1, 7)
  100. #define MX6Q_SK_DISP_PENIRQ IMX_GPIO_NR(2, 31)
  101. #define MX6DL_SK_LVDS0_PENIRQ   IMX_GPIO_NR(1, 9)
  102. #define MX6DL_SK_LVDS1_PENIRQ   IMX_GPIO_NR(4, 15)
  103.  
  104. #define MX6Q_SK_LVDS1_SCK   IMX_GPIO_NR(1, 1)
  105. #define MX6Q_SK_LVDS1_MOSI  IMX_GPIO_NR(1, 2)
  106. #define MX6Q_SK_LVDS1_MISO  IMX_GPIO_NR(7, 11)
  107. #define MX6Q_SK_LVDS1_CS    IMX_GPIO_NR(4, 15)
  108. #define MX6Q_SK_LVDS1_PENIRQ    IMX_GPIO_NR(4, 10)
  109.  
  110. #define MX6_ENET_IRQ        IMX_GPIO_NR(1, 6)
  111. #define IOMUX_OBSRV_MUX1_OFFSET 0x3c
  112. #define OBSRV_MUX1_MASK         0x3f
  113. #define OBSRV_MUX1_ENET_IRQ     0x9
  114.  
  115. void __init early_console_setup(unsigned long base, struct clk *clk);
  116. static struct clk *sata_clk;
  117.  
  118. extern char *gp_reg_id;
  119. extern char *soc_reg_id;
  120. extern char *pu_reg_id;
  121. extern bool enet_to_gpio_6;
  122. static int caam_enabled;
  123.  
  124. extern struct regulator *(*get_cpu_regulator)(void);
  125. extern void (*put_cpu_regulator)(void);
  126.  
  127. static iomux_v3_cfg_t mx6q_sabrelite_pads[] = {
  128.     /* spi-gpio, LVDS1 */
  129.     MX6Q_PAD_GPIO_1__GPIO_1_1,          /* TS CLK */
  130.     MX6Q_PAD_GPIO_2__GPIO_1_2,          /* TS DIN */
  131.     MX6Q_PAD_GPIO_16__GPIO_7_11,        /* TS DOUT */
  132.     MX6Q_PAD_KEY_ROW4__GPIO_4_15,       /* TS CS */
  133.     MX6Q_PAD_KEY_COL2__GPIO_4_10,       /* TS PENIRQ */
  134.  
  135.     /* USDHC1 */
  136.     MX6Q_PAD_SD1_CLK__USDHC1_CLK,
  137.     MX6Q_PAD_SD1_CMD__USDHC1_CMD,
  138.     MX6Q_PAD_SD1_DAT0__USDHC1_DAT0,
  139.     MX6Q_PAD_SD1_DAT1__USDHC1_DAT1,
  140.     MX6Q_PAD_SD1_DAT2__USDHC1_DAT2,
  141.     MX6Q_PAD_SD1_DAT3__USDHC1_DAT3,
  142.     MX6Q_PAD_SD4_DAT1__GPIO_2_9,        /* SD1_DET */
  143.  
  144.     /* USDHC2 */
  145.     MX6Q_PAD_SD2_CLK__USDHC2_CLK,
  146.     MX6Q_PAD_SD2_CMD__USDHC2_CMD,
  147.     MX6Q_PAD_SD2_DAT0__USDHC2_DAT0,
  148.     MX6Q_PAD_SD2_DAT1__USDHC2_DAT1,
  149.     MX6Q_PAD_SD2_DAT2__USDHC2_DAT2,
  150.     MX6Q_PAD_SD2_DAT3__USDHC2_DAT3,
  151.     MX6Q_PAD_SD4_DAT3__GPIO_2_11,       /* SD2_DET */
  152.  
  153.     /* UART1  */
  154.     MX6Q_PAD_CSI0_DAT10__UART1_TXD,
  155.     MX6Q_PAD_CSI0_DAT11__UART1_RXD,
  156.  
  157.     /* ECSPI1 */
  158.     MX6Q_PAD_CSI0_DAT4__ECSPI1_SCLK,
  159.     MX6Q_PAD_CSI0_DAT5__ECSPI1_MOSI,
  160.     MX6Q_PAD_CSI0_DAT6__ECSPI1_MISO,
  161.     MX6Q_PAD_CSI0_DAT7__GPIO_5_25,      /* LVDS0 TS CS */
  162.     MX6Q_PAD_GPIO_7__GPIO_1_7,          /* LVDS0 TS PENIRQ */
  163.  
  164.     /* ECSPI4 */
  165.     MX6Q_PAD_EIM_D21__ECSPI4_SCLK,
  166.     MX6Q_PAD_EIM_D22__ECSPI4_MISO,
  167.     MX6Q_PAD_EIM_D28__ECSPI4_MOSI,
  168.     MX6Q_PAD_EIM_D29__GPIO_3_29,        /* RGB TS CS */
  169.     MX6Q_PAD_EIM_EB3__GPIO_2_31,        /* RGB TS PENIRQ */
  170.  
  171.     /* ENET */
  172.     MX6Q_PAD_ENET_MDIO__ENET_MDIO,
  173.     MX6Q_PAD_ENET_MDC__ENET_MDC,
  174.     MX6Q_PAD_RGMII_TXC__ENET_RGMII_TXC,
  175.     MX6Q_PAD_RGMII_TD0__ENET_RGMII_TD0,
  176.     MX6Q_PAD_RGMII_TD1__ENET_RGMII_TD1,
  177.     MX6Q_PAD_RGMII_TD2__ENET_RGMII_TD2,
  178.     MX6Q_PAD_RGMII_TD3__ENET_RGMII_TD3,
  179.     MX6Q_PAD_RGMII_TX_CTL__ENET_RGMII_TX_CTL,
  180.     MX6Q_PAD_ENET_REF_CLK__ENET_TX_CLK,
  181.     MX6Q_PAD_RGMII_RXC__ENET_RGMII_RXC,
  182.     MX6Q_PAD_RGMII_RD0__ENET_RGMII_RD0,
  183.     MX6Q_PAD_RGMII_RD1__ENET_RGMII_RD1,
  184.     MX6Q_PAD_RGMII_RD2__ENET_RGMII_RD2,
  185.     MX6Q_PAD_RGMII_RD3__ENET_RGMII_RD3,
  186.     MX6Q_PAD_RGMII_RX_CTL__ENET_RGMII_RX_CTL,
  187.     MX6Q_PAD_ENET_CRS_DV__GPIO_1_25,    /* ETH_RESET */
  188. #ifdef CONFIG_MX6_ENET_IRQ_TO_GPIO
  189.     MX6Q_PAD_GPIO_6__OBSERVE_MUX_OBSRV_INT_OUT1,
  190. #endif
  191.  
  192.     /* AUDMUX */
  193.     MX6Q_PAD_KEY_COL0__AUDMUX_AUD5_TXC,
  194.     MX6Q_PAD_KEY_ROW0__AUDMUX_AUD5_TXD,
  195.     MX6Q_PAD_KEY_COL1__AUDMUX_AUD5_TXFS,
  196.     MX6Q_PAD_KEY_ROW1__AUDMUX_AUD5_RXD,
  197.     MX6Q_PAD_NANDF_CS2__CCM_CLKO2,      /* AUDIO_MCLK */
  198.  
  199.     /* CAN1  */
  200.     MX6Q_PAD_SD3_CMD__CAN1_TXCAN,
  201.     MX6Q_PAD_SD3_CLK__CAN1_RXCAN,
  202.  
  203.     /* CAN2  */
  204.     MX6Q_PAD_SD3_DAT0__CAN2_TXCAN,
  205.     MX6Q_PAD_SD3_DAT1__CAN2_RXCAN,
  206.  
  207.     /* DISPLAY */
  208.     MX6Q_PAD_DI0_DISP_CLK__IPU1_DI0_DISP_CLK,
  209.     MX6Q_PAD_DI0_PIN15__IPU1_DI0_PIN15,     /* DE */
  210.     MX6Q_PAD_DI0_PIN2__IPU1_DI0_PIN2,       /* HSync */
  211.     MX6Q_PAD_DI0_PIN3__IPU1_DI0_PIN3,       /* VSync */
  212.     MX6Q_PAD_DISP0_DAT0__IPU1_DISP0_DAT_0,
  213.     MX6Q_PAD_DISP0_DAT1__IPU1_DISP0_DAT_1,
  214.     MX6Q_PAD_DISP0_DAT2__IPU1_DISP0_DAT_2,
  215.     MX6Q_PAD_DISP0_DAT3__IPU1_DISP0_DAT_3,
  216.     MX6Q_PAD_DISP0_DAT4__IPU1_DISP0_DAT_4,
  217.     MX6Q_PAD_DISP0_DAT5__IPU1_DISP0_DAT_5,
  218.     MX6Q_PAD_DISP0_DAT6__IPU1_DISP0_DAT_6,
  219.     MX6Q_PAD_DISP0_DAT7__IPU1_DISP0_DAT_7,
  220.     MX6Q_PAD_DISP0_DAT8__IPU1_DISP0_DAT_8,
  221.     MX6Q_PAD_DISP0_DAT9__IPU1_DISP0_DAT_9,
  222.     MX6Q_PAD_DISP0_DAT10__IPU1_DISP0_DAT_10,
  223.     MX6Q_PAD_DISP0_DAT11__IPU1_DISP0_DAT_11,
  224.     MX6Q_PAD_DISP0_DAT12__IPU1_DISP0_DAT_12,
  225.     MX6Q_PAD_DISP0_DAT13__IPU1_DISP0_DAT_13,
  226.     MX6Q_PAD_DISP0_DAT14__IPU1_DISP0_DAT_14,
  227.     MX6Q_PAD_DISP0_DAT15__IPU1_DISP0_DAT_15,
  228.     MX6Q_PAD_DISP0_DAT16__IPU1_DISP0_DAT_16,
  229.     MX6Q_PAD_DISP0_DAT17__IPU1_DISP0_DAT_17,
  230.     MX6Q_PAD_DISP0_DAT18__IPU1_DISP0_DAT_18,
  231.     MX6Q_PAD_DISP0_DAT19__IPU1_DISP0_DAT_19,
  232.     MX6Q_PAD_DISP0_DAT20__IPU1_DISP0_DAT_20,
  233.     MX6Q_PAD_DISP0_DAT21__IPU1_DISP0_DAT_21,
  234.     MX6Q_PAD_DISP0_DAT22__IPU1_DISP0_DAT_22,
  235.     MX6Q_PAD_DISP0_DAT23__IPU1_DISP0_DAT_23,
  236.  
  237.     /* HDMI */
  238.     MX6Q_PAD_KEY_COL3__I2C2_SCL,
  239.     MX6Q_PAD_KEY_ROW3__I2C2_SDA,
  240.     MX6Q_PAD_KEY_ROW2__HDMI_TX_CEC_LINE,
  241.    
  242.     /* I2C1, TLV320AIC23, ADV7180 */
  243.     MX6Q_PAD_CSI0_DAT8__I2C1_SDA,
  244.     MX6Q_PAD_CSI0_DAT9__I2C1_SCL,
  245.    
  246.     /* USB OTG PWR */
  247.     MX6Q_PAD_ENET_TX_EN__GPIO_1_28,
  248.     /* USB HOST PWR */
  249.     MX6Q_PAD_SD3_DAT3__GPIO_7_7,
  250.  
  251.     /* IPU1 Camera */
  252.     MX6Q_PAD_CSI0_DAT12__IPU1_CSI0_D_12,
  253.     MX6Q_PAD_CSI0_DAT13__IPU1_CSI0_D_13,
  254.     MX6Q_PAD_CSI0_DAT14__IPU1_CSI0_D_14,
  255.     MX6Q_PAD_CSI0_DAT15__IPU1_CSI0_D_15,
  256.     MX6Q_PAD_CSI0_DAT16__IPU1_CSI0_D_16,
  257.     MX6Q_PAD_CSI0_DAT17__IPU1_CSI0_D_17,
  258.     MX6Q_PAD_CSI0_DAT18__IPU1_CSI0_D_18,
  259.     MX6Q_PAD_CSI0_DAT19__IPU1_CSI0_D_19,
  260.     MX6Q_PAD_CSI0_MCLK__IPU1_CSI0_HSYNC,
  261.     MX6Q_PAD_CSI0_PIXCLK__IPU1_CSI0_PIXCLK,
  262.     MX6Q_PAD_CSI0_VSYNC__IPU1_CSI0_VSYNC,
  263.    
  264.     /* NAND */
  265.     MX6Q_PAD_NANDF_CLE__RAWNAND_CLE,
  266.     MX6Q_PAD_NANDF_ALE__RAWNAND_ALE,
  267.     MX6Q_PAD_NANDF_CS0__RAWNAND_CE0N,
  268.     MX6Q_PAD_NANDF_CS1__RAWNAND_CE1N,
  269.     MX6Q_PAD_NANDF_RB0__RAWNAND_READY0,
  270.     MX6Q_PAD_NANDF_D0__RAWNAND_D0,
  271.     MX6Q_PAD_NANDF_D1__RAWNAND_D1,
  272.     MX6Q_PAD_NANDF_D2__RAWNAND_D2,
  273.     MX6Q_PAD_NANDF_D3__RAWNAND_D3,
  274.     MX6Q_PAD_NANDF_D4__RAWNAND_D4,
  275.     MX6Q_PAD_NANDF_D5__RAWNAND_D5,
  276.     MX6Q_PAD_NANDF_D6__RAWNAND_D6,
  277.     MX6Q_PAD_NANDF_D7__RAWNAND_D7,
  278.     MX6Q_PAD_SD4_CMD__RAWNAND_RDN,
  279.     MX6Q_PAD_SD4_CLK__RAWNAND_WRN,
  280.     MX6Q_PAD_NANDF_WP_B__RAWNAND_RESETN,   
  281. };
  282.  
  283. static iomux_v3_cfg_t mx6dl_sabrelite_pads[] = {
  284.     /* USDHC1 */
  285.     MX6DL_PAD_SD1_CLK__USDHC1_CLK,
  286.     MX6DL_PAD_SD1_CMD__USDHC1_CMD,
  287.     MX6DL_PAD_SD1_DAT0__USDHC1_DAT0,
  288.     MX6DL_PAD_SD1_DAT1__USDHC1_DAT1,
  289.     MX6DL_PAD_SD1_DAT2__USDHC1_DAT2,
  290.     MX6DL_PAD_SD1_DAT3__USDHC1_DAT3,
  291.     MX6DL_PAD_SD4_DAT1__GPIO_2_9,       /* SD1_DET */
  292.  
  293.     /* USDHC2 */
  294.     MX6DL_PAD_SD2_CLK__USDHC2_CLK,
  295.     MX6DL_PAD_SD2_CMD__USDHC2_CMD,
  296.     MX6DL_PAD_SD2_DAT0__USDHC2_DAT0,
  297.     MX6DL_PAD_SD2_DAT1__USDHC2_DAT1,
  298.     MX6DL_PAD_SD2_DAT2__USDHC2_DAT2,
  299.     MX6DL_PAD_SD2_DAT3__USDHC2_DAT3,
  300.     MX6DL_PAD_SD4_DAT3__GPIO_2_11,      /* SD2_DET */
  301.  
  302.     /* UART1  */
  303.     MX6DL_PAD_CSI0_DAT10__UART1_TXD,
  304.     MX6DL_PAD_CSI0_DAT11__UART1_RXD,
  305.  
  306.     /* ECSPI1 */
  307.     MX6DL_PAD_CSI0_DAT4__ECSPI1_SCLK,
  308.     MX6DL_PAD_CSI0_DAT5__ECSPI1_MOSI,
  309.     MX6DL_PAD_CSI0_DAT6__ECSPI1_MISO,
  310.     MX6DL_PAD_CSI0_DAT7__GPIO_5_25,     /* LVDS1 TS CS */
  311.     MX6DL_PAD_KEY_ROW4__GPIO_4_15,      /* LVDS1 TS PENIRQ */
  312.  
  313.     /* ECSPI4 */
  314.     MX6DL_PAD_EIM_D21__ECSPI4_SCLK,
  315.     MX6DL_PAD_EIM_D22__ECSPI4_MISO,
  316.     MX6DL_PAD_EIM_D28__ECSPI4_MOSI,
  317.     MX6DL_PAD_EIM_D20__GPIO_3_20,       /* LVDS0 TS CS */
  318.     MX6DL_PAD_GPIO_9__GPIO_1_9,         /* LVDS0 TS PENIRQ */
  319.  
  320.     /* ENET */
  321.     MX6DL_PAD_GPIO_16__ENET_ANATOP_ETHERNET_REF_OUT,
  322.     MX6DL_PAD_ENET_MDIO__ENET_MDIO,
  323.     MX6DL_PAD_ENET_MDC__ENET_MDC,
  324.     MX6DL_PAD_ENET_CRS_DV__ENET_RX_EN,
  325.     MX6DL_PAD_ENET_RX_ER__ENET_RX_ER,
  326.     MX6DL_PAD_ENET_TX_EN__ENET_TX_EN,
  327.     MX6DL_PAD_ENET_RXD0__ENET_RDATA_0,
  328.     MX6DL_PAD_ENET_RXD1__ENET_RDATA_1,
  329.     MX6DL_PAD_ENET_TXD0__ENET_TDATA_0,
  330.     MX6DL_PAD_ENET_TXD1__ENET_TDATA_1,
  331.     MX6DL_PAD_ENET_REF_CLK__GPIO_1_23,
  332. #ifdef CONFIG_MX6_ENET_IRQ_TO_GPIO
  333.     MX6DL_PAD_GPIO_6__OBSERVE_MUX_OBSRV_INT_OUT1,
  334. #endif
  335.  
  336.     /* AUDMUX */
  337.     MX6DL_PAD_KEY_COL0__AUDMUX_AUD5_TXC,
  338.     MX6DL_PAD_KEY_ROW0__AUDMUX_AUD5_TXD,
  339.     MX6DL_PAD_KEY_COL1__AUDMUX_AUD5_TXFS,
  340.     MX6DL_PAD_KEY_ROW1__AUDMUX_AUD5_RXD,
  341.     MX6DL_PAD_NANDF_CS2__CCM_CLKO2,     /* AUDIO_MCLK */
  342.  
  343.     /* CAN1  */
  344.     MX6DL_PAD_SD3_CMD__CAN1_TXCAN,
  345.     MX6DL_PAD_SD3_CLK__CAN1_RXCAN,
  346.  
  347.     /* CAN2  */
  348.     MX6DL_PAD_SD3_DAT0__CAN2_TXCAN,
  349.     MX6DL_PAD_SD3_DAT1__CAN2_RXCAN,
  350.  
  351.     /* DISPLAY */
  352.     MX6DL_PAD_DI0_DISP_CLK__IPU1_DI0_DISP_CLK,
  353.     MX6DL_PAD_DI0_PIN15__IPU1_DI0_PIN15,        /* DE */
  354.     MX6DL_PAD_DI0_PIN2__IPU1_DI0_PIN2,      /* HSync */
  355.     MX6DL_PAD_DI0_PIN3__IPU1_DI0_PIN3,      /* VSync */
  356.     MX6DL_PAD_DISP0_DAT0__IPU1_DISP0_DAT_0,
  357.     MX6DL_PAD_DISP0_DAT1__IPU1_DISP0_DAT_1,
  358.     MX6DL_PAD_DISP0_DAT2__IPU1_DISP0_DAT_2,
  359.     MX6DL_PAD_DISP0_DAT3__IPU1_DISP0_DAT_3,
  360.     MX6DL_PAD_DISP0_DAT4__IPU1_DISP0_DAT_4,
  361.     MX6DL_PAD_DISP0_DAT5__IPU1_DISP0_DAT_5,
  362.     MX6DL_PAD_DISP0_DAT6__IPU1_DISP0_DAT_6,
  363.     MX6DL_PAD_DISP0_DAT7__IPU1_DISP0_DAT_7,
  364.     MX6DL_PAD_DISP0_DAT8__IPU1_DISP0_DAT_8,
  365.     MX6DL_PAD_DISP0_DAT9__IPU1_DISP0_DAT_9,
  366.     MX6DL_PAD_DISP0_DAT10__IPU1_DISP0_DAT_10,
  367.     MX6DL_PAD_DISP0_DAT11__IPU1_DISP0_DAT_11,
  368.     MX6DL_PAD_DISP0_DAT12__IPU1_DISP0_DAT_12,
  369.     MX6DL_PAD_DISP0_DAT13__IPU1_DISP0_DAT_13,
  370.     MX6DL_PAD_DISP0_DAT14__IPU1_DISP0_DAT_14,
  371.     MX6DL_PAD_DISP0_DAT15__IPU1_DISP0_DAT_15,
  372.     MX6DL_PAD_DISP0_DAT16__IPU1_DISP0_DAT_16,
  373.     MX6DL_PAD_DISP0_DAT17__IPU1_DISP0_DAT_17,
  374.     MX6DL_PAD_DISP0_DAT18__IPU1_DISP0_DAT_18,
  375.     MX6DL_PAD_DISP0_DAT19__IPU1_DISP0_DAT_19,
  376.     MX6DL_PAD_DISP0_DAT20__IPU1_DISP0_DAT_20,
  377.     MX6DL_PAD_DISP0_DAT21__IPU1_DISP0_DAT_21,
  378.     MX6DL_PAD_DISP0_DAT22__IPU1_DISP0_DAT_22,
  379.     MX6DL_PAD_DISP0_DAT23__IPU1_DISP0_DAT_23,
  380.  
  381.     /* HDMI */
  382. //  MX6DL_PAD_KEY_COL3__I2C2_SCL,
  383. //  MX6DL_PAD_KEY_ROW3__I2C2_SDA,
  384. //  MX6DL_PAD_KEY_ROW2__HDMI_TX_CEC_LINE,
  385.     MX6DL_PAD_KEY_ROW2__USDHC2_VSELECT,
  386.  
  387.     /* I2C2 */
  388.     MX6DL_PAD_EIM_D16__I2C2_SDA,
  389.     MX6DL_PAD_EIM_EB2__I2C2_SCL,
  390.     /* I2C3 */
  391.     MX6DL_PAD_EIM_D18__I2C3_SDA,
  392.     MX6DL_PAD_EIM_D17__I2C3_SCL,
  393.    
  394.     /* USB HOST PWR */
  395.     MX6DL_PAD_SD3_DAT3__GPIO_7_7,
  396.  
  397.     /* IPU1 Camera */
  398.     MX6DL_PAD_CSI0_DAT12__IPU1_CSI0_D_12,
  399.     MX6DL_PAD_CSI0_DAT13__IPU1_CSI0_D_13,
  400.     MX6DL_PAD_CSI0_DAT14__IPU1_CSI0_D_14,
  401.     MX6DL_PAD_CSI0_DAT15__IPU1_CSI0_D_15,
  402.     MX6DL_PAD_CSI0_DAT16__IPU1_CSI0_D_16,
  403.     MX6DL_PAD_CSI0_DAT17__IPU1_CSI0_D_17,
  404.     MX6DL_PAD_CSI0_DAT18__IPU1_CSI0_D_18,
  405.     MX6DL_PAD_CSI0_DAT19__IPU1_CSI0_D_19,
  406.     MX6DL_PAD_CSI0_MCLK__IPU1_CSI0_HSYNC,
  407.     MX6DL_PAD_CSI0_PIXCLK__IPU1_CSI0_PIXCLK,
  408.     MX6DL_PAD_CSI0_VSYNC__IPU1_CSI0_VSYNC,
  409.    
  410.     /* NAND */
  411.     MX6DL_PAD_NANDF_CLE__RAWNAND_CLE,
  412.     MX6DL_PAD_NANDF_ALE__RAWNAND_ALE,
  413.     MX6DL_PAD_NANDF_CS0__RAWNAND_CE0N,
  414.     MX6DL_PAD_NANDF_CS1__RAWNAND_CE1N,
  415.     MX6DL_PAD_NANDF_RB0__RAWNAND_READY0,
  416.     MX6DL_PAD_NANDF_D0__RAWNAND_D0,
  417.     MX6DL_PAD_NANDF_D1__RAWNAND_D1,
  418.     MX6DL_PAD_NANDF_D2__RAWNAND_D2,
  419.     MX6DL_PAD_NANDF_D3__RAWNAND_D3,
  420.     MX6DL_PAD_NANDF_D4__RAWNAND_D4,
  421.     MX6DL_PAD_NANDF_D5__RAWNAND_D5,
  422.     MX6DL_PAD_NANDF_D6__RAWNAND_D6,
  423.     MX6DL_PAD_NANDF_D7__RAWNAND_D7,
  424.     MX6DL_PAD_SD4_CMD__RAWNAND_RDN,
  425.     MX6DL_PAD_SD4_CLK__RAWNAND_WRN,
  426.     MX6DL_PAD_NANDF_WP_B__RAWNAND_RESETN,  
  427. };
  428.  
  429. static iomux_v3_cfg_t mx6q_sabrelite_hdmi_ddc_pads[] = {
  430.     MX6Q_PAD_KEY_COL3__HDMI_TX_DDC_SCL,
  431.     MX6Q_PAD_KEY_ROW3__HDMI_TX_DDC_SDA,
  432. };
  433.  
  434. static iomux_v3_cfg_t mx6q_sabrelite_i2c2_pads[] = {
  435.     MX6Q_PAD_KEY_COL3__I2C2_SCL,
  436.     MX6Q_PAD_KEY_ROW3__I2C2_SDA,
  437. };
  438.  
  439. static iomux_v3_cfg_t mx6dl_sabrelite_hdmi_ddc_pads[] = {
  440.     MX6DL_PAD_KEY_COL3__HDMI_TX_DDC_SCL,
  441.     MX6DL_PAD_KEY_ROW3__HDMI_TX_DDC_SDA,
  442. };
  443.  
  444. static iomux_v3_cfg_t mx6dl_sabrelite_i2c2_pads[] = {
  445.     MX6DL_PAD_KEY_COL3__I2C2_SCL,
  446.     MX6DL_PAD_KEY_ROW3__I2C2_SDA,
  447. };
  448.  
  449. #define MX6DL_USDHC_PAD_SETTING(id, speed)  \
  450. mx6dl_sd##id##_##speed##mhz[] = {       \
  451.     MX6DL_PAD_SD##id##_CLK__USDHC##id##_CLK_##speed##MHZ,   \
  452.     MX6DL_PAD_SD##id##_CMD__USDHC##id##_CMD_##speed##MHZ,   \
  453.     MX6DL_PAD_SD##id##_DAT0__USDHC##id##_DAT0_##speed##MHZ, \
  454.     MX6DL_PAD_SD##id##_DAT1__USDHC##id##_DAT1_##speed##MHZ, \
  455.     MX6DL_PAD_SD##id##_DAT2__USDHC##id##_DAT2_##speed##MHZ, \
  456.     MX6DL_PAD_SD##id##_DAT3__USDHC##id##_DAT3_##speed##MHZ, \
  457. }
  458.  
  459. static iomux_v3_cfg_t MX6DL_USDHC_PAD_SETTING(2, 50);
  460. static iomux_v3_cfg_t MX6DL_USDHC_PAD_SETTING(2, 100);
  461. static iomux_v3_cfg_t MX6DL_USDHC_PAD_SETTING(2, 200);
  462.  
  463. #define MX6Q_USDHC_PAD_SETTING(id, speed)   \
  464. mx6q_sd##id##_##speed##mhz[] = {        \
  465.     MX6Q_PAD_SD##id##_CLK__USDHC##id##_CLK_##speed##MHZ,    \
  466.     MX6Q_PAD_SD##id##_CMD__USDHC##id##_CMD_##speed##MHZ,    \
  467.     MX6Q_PAD_SD##id##_DAT0__USDHC##id##_DAT0_##speed##MHZ,  \
  468.     MX6Q_PAD_SD##id##_DAT1__USDHC##id##_DAT1_##speed##MHZ,  \
  469.     MX6Q_PAD_SD##id##_DAT2__USDHC##id##_DAT2_##speed##MHZ,  \
  470.     MX6Q_PAD_SD##id##_DAT3__USDHC##id##_DAT3_##speed##MHZ,  \
  471. }
  472.  
  473. static iomux_v3_cfg_t MX6Q_USDHC_PAD_SETTING(1, 50);
  474. static iomux_v3_cfg_t MX6Q_USDHC_PAD_SETTING(1, 100);
  475. static iomux_v3_cfg_t MX6Q_USDHC_PAD_SETTING(1, 200);
  476.  
  477. enum sd_pad_mode {
  478.     SD_PAD_MODE_LOW_SPEED,
  479.     SD_PAD_MODE_MED_SPEED,
  480.     SD_PAD_MODE_HIGH_SPEED,
  481. };
  482.  
  483. static int plt_sd_pad_change(unsigned int index, int clock)
  484. {
  485.     /* LOW speed is the default state of SD pads */
  486.     static enum sd_pad_mode pad_mode = SD_PAD_MODE_LOW_SPEED;
  487.  
  488.     iomux_v3_cfg_t *sd_pads_200mhz = NULL;
  489.     iomux_v3_cfg_t *sd_pads_100mhz = NULL;
  490.     iomux_v3_cfg_t *sd_pads_50mhz = NULL;
  491.  
  492.     u32 sd_pads_200mhz_cnt;
  493.     u32 sd_pads_100mhz_cnt;
  494.     u32 sd_pads_50mhz_cnt;
  495.  
  496.     switch (index) {
  497.     case 0:
  498.         if (cpu_is_mx6q()) {
  499.             sd_pads_200mhz = mx6q_sd1_200mhz;
  500.             sd_pads_100mhz = mx6q_sd1_100mhz;
  501.             sd_pads_50mhz = mx6q_sd1_50mhz;
  502.  
  503.             sd_pads_200mhz_cnt = ARRAY_SIZE(mx6q_sd1_200mhz);
  504.             sd_pads_100mhz_cnt = ARRAY_SIZE(mx6q_sd1_100mhz);
  505.             sd_pads_50mhz_cnt = ARRAY_SIZE(mx6q_sd1_50mhz);
  506.         }
  507.         break;
  508.     case 1:
  509.         if (cpu_is_mx6dl()) {
  510.             sd_pads_200mhz = mx6dl_sd2_200mhz;
  511.             sd_pads_100mhz = mx6dl_sd2_100mhz;
  512.             sd_pads_50mhz = mx6dl_sd2_50mhz;
  513.  
  514.             sd_pads_200mhz_cnt = ARRAY_SIZE(mx6dl_sd2_200mhz);
  515.             sd_pads_100mhz_cnt = ARRAY_SIZE(mx6dl_sd2_100mhz);
  516.             sd_pads_50mhz_cnt = ARRAY_SIZE(mx6dl_sd2_50mhz);
  517.         }
  518.         break;
  519.     default:
  520.         printk(KERN_ERR "no such SD host controller index %d\n", index);
  521.         return -EINVAL;
  522.     }
  523.  
  524.     if (clock > 100000000) {
  525.         if (pad_mode == SD_PAD_MODE_HIGH_SPEED)
  526.             return 0;
  527.         BUG_ON(!sd_pads_200mhz);
  528.         pad_mode = SD_PAD_MODE_HIGH_SPEED;
  529.         return mxc_iomux_v3_setup_multiple_pads(sd_pads_200mhz,
  530.                             sd_pads_200mhz_cnt);
  531.     } else if (clock > 52000000) {
  532.         if (pad_mode == SD_PAD_MODE_MED_SPEED)
  533.             return 0;
  534.         BUG_ON(!sd_pads_100mhz);
  535.         pad_mode = SD_PAD_MODE_MED_SPEED;
  536.         return mxc_iomux_v3_setup_multiple_pads(sd_pads_100mhz,
  537.                             sd_pads_100mhz_cnt);
  538.     } else {
  539.         if (pad_mode == SD_PAD_MODE_LOW_SPEED)
  540.             return 0;
  541.         BUG_ON(!sd_pads_50mhz);
  542.         pad_mode = SD_PAD_MODE_LOW_SPEED;
  543.         return mxc_iomux_v3_setup_multiple_pads(sd_pads_50mhz,
  544.                             sd_pads_50mhz_cnt);
  545.     }
  546. }
  547.  
  548. static const struct esdhc_platform_data mx6q_sabrelite_sd1_data __initconst = {
  549.     .cd_gpio = MX6Q_SK_SD1_CD,
  550.     .keep_power_at_suspend = 1,
  551.     .platform_pad_change    = plt_sd_pad_change,
  552. //  .support_18v        = 1,
  553. };
  554.  
  555. static const struct esdhc_platform_data mx6q_sabrelite_sd2_data __initconst = {
  556.     .cd_gpio = MX6Q_SK_SD2_CD,
  557.     .keep_power_at_suspend = 1,
  558.     .platform_pad_change    = plt_sd_pad_change,
  559. //  .support_18v        = 1,
  560. };
  561.  
  562. static struct mtd_partition sk_nand_partitions[] = {
  563.     {
  564.         .name   = "U-boot partition",
  565.         .offset = 0,
  566.         .size   = 16 * SZ_1M,
  567.     },
  568.     {
  569.         .name   = "U-boot environment partition",
  570.         .offset = MTDPART_OFS_APPEND,
  571.         .size   = SZ_1M,
  572.     },
  573.     {
  574.         .name   = "Linux kernel partition",
  575.         .offset = MTDPART_OFS_APPEND,
  576.         .size   = 7 * SZ_1M,
  577.     },
  578.     {
  579.         .name   = "Linux safe kernel partition (rootfs in initramfs)",
  580.         .offset = MTDPART_OFS_APPEND,
  581.         .size   = 12 * SZ_1M,
  582.     },
  583.     {
  584.         .name   = "NAND rootfs partition",
  585.         .offset = MTDPART_OFS_NXTBLK,
  586.         .size   = MTDPART_SIZ_FULL,
  587.     },
  588. };
  589.  
  590. static int __init gpmi_nand_platform_init(void) { return 0; }
  591.  
  592. static const struct gpmi_nand_platform_data
  593. mx6q_gpmi_nand_platform_data __initconst = {
  594.     .platform_init           = gpmi_nand_platform_init,
  595.     .min_prop_delay_in_ns    = 5,
  596.     .max_prop_delay_in_ns    = 9,
  597.     .max_chip_count          = 1,
  598.     .enable_bbt              = 1,
  599.     .partitions              = sk_nand_partitions,
  600.     .partition_count         = ARRAY_SIZE(sk_nand_partitions),
  601. };
  602.  
  603. static const struct anatop_thermal_platform_data
  604.     mx6q_sabrelite_anatop_thermal_data __initconst = {
  605.         .name = "anatop_thermal",
  606. };
  607.  
  608. static inline void mx6q_sabrelite_init_uart(void)
  609. {
  610.     imx6q_add_imx_uart(0, NULL);
  611. }
  612.  
  613. static int mx6q_sabrelite_fec_phy_init(struct phy_device *phydev)
  614. {
  615.     unsigned int rst_gpio;
  616.    
  617.     if (cpu_is_mx6q())
  618.         rst_gpio = MX6Q_SK_ETH_RESET;
  619.     else
  620.         rst_gpio = MX6DL_SK_ETH_RESET;
  621.  
  622.     gpio_request(rst_gpio, "sk-eth-reset");
  623.     gpio_direction_output(rst_gpio, 1);
  624.     gpio_set_value(rst_gpio, 0);
  625.     msleep(1);
  626.     gpio_set_value(rst_gpio, 1);
  627.    
  628.     return 0;
  629. }
  630.  
  631. static struct fec_platform_data fec_data __initdata = {
  632.     .init = mx6q_sabrelite_fec_phy_init,
  633.     .phy = PHY_INTERFACE_MODE_RGMII,
  634.     .gpio_irq = MX6_ENET_IRQ,
  635. };
  636.  
  637. static int mx6q_sabrelite_spi1_cs[] = {
  638.     MX6Q_SK_ECSPI1_CS0,
  639. };
  640.  
  641. static const struct spi_imx_master mx6q_sabrelite_spi1_data __initconst = {
  642.     .chipselect     = mx6q_sabrelite_spi1_cs,
  643.     .num_chipselect = ARRAY_SIZE(mx6q_sabrelite_spi1_cs),
  644. };
  645.  
  646. static int mx6q_sabrelite_spi4_cs[] = {
  647.     MX6Q_SK_ECSPI4_CS0,
  648. };
  649.  
  650. static const struct spi_imx_master mx6q_sabrelite_spi4_data __initconst = {
  651.     .chipselect     = mx6q_sabrelite_spi4_cs,
  652.     .num_chipselect = ARRAY_SIZE(mx6q_sabrelite_spi4_cs),
  653. };
  654.  
  655. static int lvds0_pendown_state(void)
  656. {
  657.     unsigned int penirq_gpio;
  658.    
  659.     if (cpu_is_mx6q())
  660.         penirq_gpio = MX6Q_SK_LVDS0_PENIRQ;
  661.     else
  662.         penirq_gpio = MX6DL_SK_LVDS0_PENIRQ;
  663.  
  664.     return !gpio_get_value(penirq_gpio);
  665. }
  666.  
  667. static struct ads7846_platform_data lvds0_ads_info = {
  668.     .x_min  = 150,
  669.     .x_max  = 3830,
  670.     .y_min  = 190,
  671.     .y_max  = 3830,
  672.     .debounce_max   = 5,
  673.     .debounce_tol   = 5, //10
  674.     .debounce_rep   = 0,
  675.     .get_pendown_state = lvds0_pendown_state,
  676. };
  677.  
  678. static int lvds1_pendown_state(void)
  679. {
  680.     unsigned int penirq_gpio;
  681.    
  682.     if (cpu_is_mx6q())
  683.         penirq_gpio = MX6Q_SK_LVDS1_PENIRQ;
  684.     else
  685.         penirq_gpio = MX6DL_SK_LVDS1_PENIRQ;
  686.  
  687.     return !gpio_get_value(penirq_gpio);
  688. }
  689.  
  690. static struct ads7846_platform_data lvds1_ads_info = {
  691.     .x_min  = 150,
  692.     .x_max  = 3830,
  693.     .y_min  = 190,
  694.     .y_max  = 3830,
  695.     .debounce_max   = 5,
  696.     .debounce_tol   = 5, //10
  697.     .debounce_rep   = 0,
  698.     .get_pendown_state = lvds1_pendown_state,
  699. };
  700.  
  701. static int disp_pendown_state(void)
  702. {
  703.     return !gpio_get_value(MX6Q_SK_DISP_PENIRQ);
  704. }
  705.  
  706. static struct ads7846_platform_data disp_ads_info = {
  707.     .x_min  = 150,
  708.     .x_max  = 3830,
  709.     .y_min  = 190,
  710.     .y_max  = 3830,
  711.     .debounce_max   = 5,
  712.     .debounce_tol   = 5, //10
  713.     .debounce_rep   = 0,
  714.     .get_pendown_state = disp_pendown_state,
  715. };
  716.  
  717. static struct spi_board_info imx6_sabrelite_spi_devices[] __initdata = {
  718.     {
  719.         .modalias = "ads7846",
  720.         .max_speed_hz = 1000 * 1000,
  721.         .bus_num = 0,
  722.         .chip_select = 0,
  723.         .platform_data = &lvds0_ads_info,
  724.         .irq = gpio_to_irq(MX6Q_SK_LVDS0_PENIRQ),
  725.     },
  726.     {
  727.         .modalias = "ads7846",
  728.         .max_speed_hz = 1000 * 1000,
  729.         .bus_num = 3,
  730.         .chip_select = 0,
  731.         .platform_data = &disp_ads_info,
  732.         .irq = gpio_to_irq(MX6Q_SK_DISP_PENIRQ),
  733.     },
  734.     {
  735.         .modalias = "ads7846",
  736.         .max_speed_hz = 1000 * 1000,
  737.         .bus_num = 4,
  738.         .chip_select = 0,
  739.         .controller_data = (void *)MX6Q_SK_LVDS1_CS,
  740.         .platform_data = &lvds1_ads_info,
  741.         .irq = gpio_to_irq(MX6Q_SK_LVDS1_PENIRQ),
  742.     }, 
  743. };
  744.  
  745. struct spi_gpio_platform_data lvds1_spi_platform_data = {
  746.     .sck = MX6Q_SK_LVDS1_SCK,
  747.     .mosi = MX6Q_SK_LVDS1_MOSI,
  748.     .miso = MX6Q_SK_LVDS1_MISO,
  749.     .num_chipselect = 1,
  750. };
  751.  
  752. struct platform_device lvds1_spi_gpio_device = {
  753.     .name = "spi_gpio",
  754.     .id = 4,
  755.     .dev = {
  756.         .platform_data = &lvds1_spi_platform_data,
  757.     },
  758. };
  759.  
  760. static void spi_device_init(void)
  761. {
  762.     if (cpu_is_mx6q()) {
  763.         platform_device_register(&lvds1_spi_gpio_device);
  764.  
  765.         spi_register_board_info(imx6_sabrelite_spi_devices,
  766.             ARRAY_SIZE(imx6_sabrelite_spi_devices));
  767.     } else {
  768.         imx6_sabrelite_spi_devices[0].platform_data = &lvds1_ads_info;
  769.         imx6_sabrelite_spi_devices[0].irq = gpio_to_irq(MX6DL_SK_LVDS1_PENIRQ);
  770.         imx6_sabrelite_spi_devices[1].platform_data = &lvds0_ads_info;
  771.         imx6_sabrelite_spi_devices[1].irq = gpio_to_irq(MX6DL_SK_LVDS0_PENIRQ);
  772.  
  773.         spi_register_board_info(imx6_sabrelite_spi_devices, 2);
  774.     }
  775. }
  776.  
  777. static struct mxc_audio_platform_data mx6_sabrelite_audio_data;
  778.  
  779. static int mx6_sabrelite_sgtl5000_init(void)
  780. {
  781.     struct clk *clko2;
  782.     struct clk *new_parent;
  783.     int rate;
  784.  
  785.     clko2 = clk_get(NULL, "clko2_clk");
  786.     if (IS_ERR(clko2)) {
  787.         pr_err("can't get CLKO2 clock.\n");
  788.         return PTR_ERR(clko2);
  789.     }
  790.    
  791.     new_parent = clk_get(NULL, "osc_clk");
  792.     if (!IS_ERR(new_parent)) {
  793.         clk_set_parent(clko2, new_parent);
  794.         clk_put(new_parent);
  795.     }
  796.     rate = clk_round_rate(clko2, 12000000);
  797.  
  798.     mx6_sabrelite_audio_data.sysclk = rate;
  799.     clk_set_rate(clko2, rate);
  800.     clk_enable(clko2);
  801.  
  802.     return 0;
  803. }
  804.  
  805. static struct imx_ssi_platform_data mx6_sabrelite_ssi_pdata = {
  806.     .flags = IMX_SSI_DMA | IMX_SSI_SYN,
  807. };
  808.  
  809. static struct mxc_audio_platform_data mx6_sabrelite_audio_data = {
  810.     .ssi_num = 1,
  811.     .src_port = 2,
  812.     .ext_port = 5,
  813.     .init = mx6_sabrelite_sgtl5000_init,
  814.     .hp_gpio = -1,
  815. };
  816.  
  817. static struct platform_device mx6_sabrelite_audio_device = {
  818.     .name = "imx-sgtl5000",
  819. };
  820.  
  821. static struct imxi2c_platform_data mx6q_sabrelite_i2c_data = {
  822.     .bitrate = 100000,
  823. };
  824.  
  825. static void mx6q_csi0_io_init(void)
  826. {
  827.     if (cpu_is_mx6q())
  828.         mxc_iomux_set_gpr_register(1, 19, 1, 1);
  829.     else
  830.         mxc_iomux_set_gpr_register(13, 0, 3, 4);
  831. }
  832.  
  833. static struct fsl_mxc_tvin_platform_data adv7180_data = {
  834.     .dvddio_reg = NULL,
  835.     .dvdd_reg   = NULL,
  836.     .avdd_reg   = NULL,
  837.     .pvdd_reg   = NULL,
  838.     .pwdn       = NULL,
  839.     .reset      = NULL,
  840.     .cvbs       = true,
  841.     .io_init    = mx6q_csi0_io_init,
  842. };
  843.  
  844. static void mx6q_csi0_cam_powerndown(int powerdown)
  845.     {
  846.     //TODO...
  847.     msleep(2);
  848.     }
  849.  
  850. static struct fsl_mxc_camera_platform_data camera_data = {
  851.     .mclk       = 24000000,
  852.     .mclk_source    = 0,
  853.     .csi        = 0,
  854.     .io_init    = mx6q_csi0_io_init,
  855.     .pwdn       = mx6q_csi0_cam_powerndown,
  856. };
  857.  
  858. static struct i2c_board_info mx6q_sk_i2c0_board_info[] __initdata = {
  859.     {
  860.         I2C_BOARD_INFO("tlv320aic23", 0x1a),
  861.     },
  862. //  {
  863. //      I2C_BOARD_INFO("adv7180", 0x21),
  864. //      .platform_data = (void *)&adv7180_data,
  865. //
  866. //  },
  867.     {
  868.         I2C_BOARD_INFO("ov2640", 0x30),
  869.         .platform_data = (void *)&camera_data,
  870.     },
  871. };
  872.  
  873. static struct i2c_board_info mx6q_sk_i2c1_board_info[] __initdata = {
  874.     {
  875.         I2C_BOARD_INFO("mxc_hdmi_i2c", 0x50),
  876.     },
  877. };
  878.  
  879. static struct i2c_board_info mx6dl_sk_i2c1_board_info[] __initdata = {
  880.     {
  881.         I2C_BOARD_INFO("tlv320aic23", 0x1a),
  882.     },
  883.     {
  884.         I2C_BOARD_INFO("adv7180", 0x21),
  885.         .platform_data = (void *)&adv7180_data,
  886.  
  887.     },
  888.     {
  889.         I2C_BOARD_INFO("pcf8563", 0x51),
  890.     },
  891.     {
  892.         I2C_BOARD_INFO("mxc_hdmi_i2c", 0x50),
  893.     },
  894. };
  895.  
  896. static void imx6q_sabrelite_usbotg_vbus(bool on)
  897. {
  898.     if (cpu_is_mx6q()) {
  899.         if (on)
  900.             gpio_set_value_cansleep(MX6Q_SK_USB_OTG_PWR, 1);
  901.         else
  902.             gpio_set_value_cansleep(MX6Q_SK_USB_OTG_PWR, 0);
  903.     }
  904. }
  905.  
  906. static void imx6q_sabrelite_usbhost1_vbus(bool on)
  907. {
  908.     if (on)
  909.         gpio_set_value_cansleep(MX6Q_SK_USB_HOST_PWR, 1);
  910.     else
  911.         gpio_set_value_cansleep(MX6Q_SK_USB_HOST_PWR, 0);
  912. }
  913.  
  914. static void __init imx6q_sabrelite_init_usb(void)
  915. {
  916.     int ret = 0;
  917.  
  918.     imx_otg_base = MX6_IO_ADDRESS(MX6Q_USB_OTG_BASE_ADDR);
  919.  
  920.     if (cpu_is_mx6q()) {
  921.         ret = gpio_request(MX6Q_SK_USB_OTG_PWR, "sk-usb-otg-pwr");
  922.         if (ret) {
  923.             pr_err("failed to get GPIO MX6Q_SK_USB_OTG_PWR: %d\n", ret);
  924.             return;
  925.         }
  926.         gpio_direction_output(MX6Q_SK_USB_OTG_PWR, 1);
  927.     }
  928.  
  929.     ret = gpio_request(MX6Q_SK_USB_HOST_PWR, "sk-usb-host-pwr");
  930.     if (ret) {
  931.         pr_err("failed to get GPIO MX6Q_SK_USB_HOST_PWR: %d\n", ret);
  932.         return;
  933.     }
  934.     gpio_direction_output(MX6Q_SK_USB_HOST_PWR, 1);
  935.  
  936.     mxc_iomux_set_gpr_register(1, 13, 1, 1);
  937.  
  938.     mx6_set_otghost_vbus_func(imx6q_sabrelite_usbotg_vbus);
  939.     mx6_set_host1_vbus_func(imx6q_sabrelite_usbhost1_vbus);
  940. }
  941.  
  942. /* HW Initialization, if return 0, initialization is successful. */
  943. static int mx6q_sabrelite_sata_init(struct device *dev, void __iomem *addr)
  944. {
  945.     u32 tmpdata;
  946.     int ret = 0;
  947.     struct clk *clk;
  948.  
  949.     sata_clk = clk_get(dev, "imx_sata_clk");
  950.     if (IS_ERR(sata_clk)) {
  951.         dev_err(dev, "no sata clock.\n");
  952.         return PTR_ERR(sata_clk);
  953.     }
  954.     ret = clk_enable(sata_clk);
  955.     if (ret) {
  956.         dev_err(dev, "can't enable sata clock.\n");
  957.         goto put_sata_clk;
  958.     }
  959.  
  960.     tmpdata = readl(IOMUXC_GPR13);
  961.     writel(((tmpdata & ~0x07FFFFFD) | 0x0593A044), IOMUXC_GPR13);
  962.  
  963.     /* enable SATA_PHY PLL */
  964.     tmpdata = readl(IOMUXC_GPR13);
  965.     writel(((tmpdata & ~0x2) | 0x2), IOMUXC_GPR13);
  966.  
  967.     /* Get the AHB clock rate, and configure the TIMER1MS reg later */
  968.     clk = clk_get(NULL, "ahb");
  969.     if (IS_ERR(clk)) {
  970.         dev_err(dev, "no ahb clock.\n");
  971.         ret = PTR_ERR(clk);
  972.         goto release_sata_clk;
  973.     }
  974.     tmpdata = clk_get_rate(clk) / 1000;
  975.     clk_put(clk);
  976.  
  977. #ifdef CONFIG_SATA_AHCI_PLATFORM
  978.     ret = sata_init(addr, tmpdata);
  979.     if (ret == 0)
  980.         return ret;
  981. #else
  982.     usleep_range(1000, 2000);
  983.     /* AHCI PHY enter into PDDQ mode if the AHCI module is not enabled */
  984.     tmpdata = readl(addr + PORT_PHY_CTL);
  985.     writel(tmpdata | PORT_PHY_CTL_PDDQ_LOC, addr + PORT_PHY_CTL);
  986.     pr_info("No AHCI save PWR: PDDQ %s\n", ((readl(addr + PORT_PHY_CTL)
  987.                     >> 20) & 1) ? "enabled" : "disabled");
  988. #endif
  989.  
  990. release_sata_clk:
  991.     /* disable SATA_PHY PLL */
  992.     writel((readl(IOMUXC_GPR13) & ~0x2), IOMUXC_GPR13);
  993.     clk_disable(sata_clk);
  994. put_sata_clk:
  995.     clk_put(sata_clk);
  996.  
  997.     return ret;
  998. }
  999.  
  1000. #ifdef CONFIG_SATA_AHCI_PLATFORM
  1001. static void mx6q_sabrelite_sata_exit(struct device *dev)
  1002. {
  1003.     clk_disable(sata_clk);
  1004.     clk_put(sata_clk);
  1005. }
  1006.  
  1007. static struct ahci_platform_data mx6q_sabrelite_sata_data = {
  1008.     .init = mx6q_sabrelite_sata_init,
  1009.     .exit = mx6q_sabrelite_sata_exit,
  1010. };
  1011. #endif
  1012.  
  1013. static void mx6q_sabrelite_flexcan0_switch(int enable) {}
  1014. static void mx6q_sabrelite_flexcan1_switch(int enable) {}
  1015.  
  1016. static const struct flexcan_platform_data
  1017.     mx6q_sabrelite_flexcan0_pdata __initconst = {
  1018.     .transceiver_switch = mx6q_sabrelite_flexcan0_switch,
  1019. };
  1020.  
  1021. static const struct flexcan_platform_data
  1022.     mx6q_sabrelite_flexcan1_pdata __initconst = {
  1023.     .transceiver_switch = mx6q_sabrelite_flexcan1_switch,
  1024. };
  1025.  
  1026. static struct viv_gpu_platform_data imx6q_gpu_pdata __initdata = {
  1027.     .reserved_mem_size = SZ_128M,
  1028. };
  1029.  
  1030. static struct imx_asrc_platform_data imx_asrc_data = {
  1031.     .channel_bits = 4,
  1032.     .clk_map_ver = 2,
  1033. };
  1034.  
  1035. static struct ipuv3_fb_platform_data sabrelite_fb_data[] = {
  1036.     { /*fb0*/
  1037.     .disp_dev = "ldb",
  1038.     .interface_pix_fmt = IPU_PIX_FMT_RGB24,
  1039.     .mode_str = "SK-ATM0704",
  1040.     .default_bpp = 16,
  1041.     .int_clk = false,
  1042.     }, {
  1043.     .disp_dev = "lcd",
  1044.     .interface_pix_fmt = IPU_PIX_FMT_RGB24,
  1045.     .mode_str = "SK-MI0430",
  1046.     .default_bpp = 16,
  1047.     .int_clk = false,
  1048.     }, {
  1049.     .disp_dev = "ldb",
  1050.     .interface_pix_fmt = IPU_PIX_FMT_RGB24,
  1051.     .mode_str = "LDB-XGA",
  1052.     .default_bpp = 16,
  1053.     .int_clk = false,
  1054.     }, {
  1055.     .disp_dev = "ldb",
  1056.     .interface_pix_fmt = IPU_PIX_FMT_RGB24,
  1057.     .mode_str = "SK-ATM0704",
  1058.     .default_bpp = 16,
  1059.     .int_clk = false,
  1060.     },
  1061. };
  1062.  
  1063. static void hdmi_init(int ipu_id, int disp_id)
  1064. {
  1065.     int hdmi_mux_setting;
  1066.  
  1067.     if ((ipu_id > 1) || (ipu_id < 0)) {
  1068.         pr_err("Invalid IPU select for HDMI: %d. Set to 0\n", ipu_id);
  1069.         ipu_id = 0;
  1070.     }
  1071.  
  1072.     if ((disp_id > 1) || (disp_id < 0)) {
  1073.         pr_err("Invalid DI select for HDMI: %d. Set to 0\n", disp_id);
  1074.         disp_id = 0;
  1075.     }
  1076.  
  1077.     /* Configure the connection between IPU1/2 and HDMI */
  1078.     hdmi_mux_setting = 2*ipu_id + disp_id;
  1079.  
  1080.     /* GPR3, bits 2-3 = HDMI_MUX_CTL */
  1081.     mxc_iomux_set_gpr_register(3, 2, 2, hdmi_mux_setting);
  1082.  
  1083.     /* Set HDMI event as SDMA event2 while Chip version later than TO1.2 */
  1084.     if ((mx6q_revision() > IMX_CHIP_REVISION_1_1))
  1085.         mxc_iomux_set_gpr_register(0, 0, 1, 1);
  1086. }
  1087.  
  1088. static void hdmi_enable_ddc_pin(void)
  1089. {
  1090.     if (cpu_is_mx6q())
  1091.         mxc_iomux_v3_setup_multiple_pads(mx6q_sabrelite_hdmi_ddc_pads,
  1092.             ARRAY_SIZE(mx6q_sabrelite_hdmi_ddc_pads));
  1093. //  else
  1094. //      mxc_iomux_v3_setup_multiple_pads(mx6dl_sabrelite_hdmi_ddc_pads,
  1095. //          ARRAY_SIZE(mx6q_sabrelite_hdmi_ddc_pads));
  1096. }
  1097.  
  1098. static void hdmi_disable_ddc_pin(void)
  1099. {
  1100.     if (cpu_is_mx6q())
  1101.         mxc_iomux_v3_setup_multiple_pads(mx6q_sabrelite_i2c2_pads,
  1102.             ARRAY_SIZE(mx6q_sabrelite_i2c2_pads));
  1103. //  else
  1104. //      mxc_iomux_v3_setup_multiple_pads(mx6dl_sabrelite_i2c2_pads,
  1105. //          ARRAY_SIZE(mx6q_sabrelite_i2c2_pads));
  1106. }
  1107.  
  1108. static struct fsl_mxc_hdmi_platform_data hdmi_data = {
  1109.     .init = hdmi_init,
  1110.     .enable_pins = hdmi_enable_ddc_pin,
  1111.     .disable_pins = hdmi_disable_ddc_pin,
  1112. };
  1113.  
  1114. static struct fsl_mxc_hdmi_core_platform_data hdmi_core_data = {
  1115.     .ipu_id = 0,
  1116.     .disp_id = 1,
  1117. };
  1118.  
  1119. static struct fsl_mxc_lcd_platform_data lcdif_data = {
  1120.     .ipu_id = 0,
  1121.     .disp_id = 0,
  1122.     .default_ifmt = IPU_PIX_FMT_RGB565,
  1123. };
  1124.  
  1125. static struct fsl_mxc_ldb_platform_data ldb_data = {
  1126.     .ipu_id = 1,
  1127.     .disp_id = 0,
  1128.     .ext_ref = 1,
  1129.     .mode = LDB_SEP0,
  1130.     .sec_ipu_id = 1,
  1131.     .sec_disp_id = 1,
  1132. };
  1133.  
  1134. static struct imx_ipuv3_platform_data ipu_data[] = {
  1135.     {
  1136.         .rev = 4,
  1137.         .csi_clk[0] = "clko_clk",
  1138.     }, {
  1139.         .rev = 4,
  1140.         .csi_clk[0] = "clko_clk",
  1141.     },
  1142. };
  1143.  
  1144. static struct fsl_mxc_capture_platform_data capture_data[] = {
  1145.     {
  1146.         .csi = 0,
  1147.         .ipu = 0,
  1148.         .mclk_source = 0,
  1149.         .is_mipi = 0,
  1150.     }, {
  1151.         .csi = 1,
  1152.         .ipu = 0,
  1153.         .mclk_source = 0,
  1154.         .is_mipi = 0,
  1155.     },
  1156. };
  1157.  
  1158. static struct mipi_csi2_platform_data mipi_csi2_pdata = {
  1159.     .ipu_id     = 0,
  1160.     .csi_id     = 1,
  1161.     .v_channel  = 0,
  1162.     .lanes      = 2,
  1163.     .dphy_clk   = "mipi_pllref_clk",
  1164.     .pixel_clk  = "emi_clk",
  1165. };
  1166.  
  1167. struct imx_vout_mem {
  1168.     resource_size_t res_mbase;
  1169.     resource_size_t res_msize;
  1170. };
  1171.  
  1172. static struct imx_vout_mem vout_mem __initdata = {
  1173.     .res_msize = SZ_128M,
  1174. };
  1175.  
  1176. static void sabrelite_suspend_enter(void)
  1177. {
  1178.     /* suspend preparation */
  1179. }
  1180.  
  1181. static void sabrelite_suspend_exit(void)
  1182. {
  1183.     /* resume restore */
  1184. }
  1185. static const struct pm_platform_data mx6q_sabrelite_pm_data __initconst = {
  1186.     .name = "imx_pm",
  1187.     .suspend_enter = sabrelite_suspend_enter,
  1188.     .suspend_exit = sabrelite_suspend_exit,
  1189. };
  1190.  
  1191.  
  1192. static struct regulator_consumer_supply sabrelite_vmmc_consumers[] = {
  1193.     REGULATOR_SUPPLY("vmmc", "sdhci-esdhc-imx.0"),
  1194.     REGULATOR_SUPPLY("vmmc", "sdhci-esdhc-imx.1"),
  1195. };
  1196.  
  1197. static struct regulator_init_data sabrelite_vmmc_init = {
  1198.     .num_consumer_supplies = ARRAY_SIZE(sabrelite_vmmc_consumers),
  1199.     .consumer_supplies = sabrelite_vmmc_consumers,
  1200. };
  1201.  
  1202. static struct fixed_voltage_config sabrelite_vmmc_reg_config = {
  1203.     .supply_name        = "vmmc",
  1204.     .microvolts     = 3300000,
  1205.     .gpio           = -1,
  1206.     .init_data      = &sabrelite_vmmc_init,
  1207. };
  1208.  
  1209. static struct platform_device sabrelite_vmmc_reg_devices = {
  1210.     .name   = "reg-fixed-voltage",
  1211.     .id = 3,
  1212.     .dev    = {
  1213.         .platform_data = &sabrelite_vmmc_reg_config,
  1214.     },
  1215. };
  1216.  
  1217. static int imx6q_init_audio(void)
  1218. {
  1219.     mxc_register_device(&mx6_sabrelite_audio_device,
  1220.                 &mx6_sabrelite_audio_data);
  1221.     imx6q_add_imx_ssi(1, &mx6_sabrelite_ssi_pdata);
  1222.  
  1223.     return 0;
  1224. }
  1225.  
  1226. static struct platform_pwm_backlight_data mx6_sabrelite_pwm_backlight_data = {
  1227.     .pwm_id = 3,
  1228.     .max_brightness = 255,
  1229.     .dft_brightness = 128,
  1230.     .pwm_period_ns = 50000,
  1231. };
  1232.  
  1233. static struct mxc_dvfs_platform_data sabrelite_dvfscore_data = {
  1234.     .reg_id = "cpu_vddgp",
  1235.     .soc_id = "cpu_vddsoc",
  1236.     .pu_id = "cpu_vddvpu",
  1237.     .clk1_id = "cpu_clk",
  1238.     .clk2_id = "gpc_dvfs_clk",
  1239.     .gpc_cntr_offset = MXC_GPC_CNTR_OFFSET,
  1240.     .ccm_cdcr_offset = MXC_CCM_CDCR_OFFSET,
  1241.     .ccm_cacrr_offset = MXC_CCM_CACRR_OFFSET,
  1242.     .ccm_cdhipr_offset = MXC_CCM_CDHIPR_OFFSET,
  1243.     .prediv_mask = 0x1F800,
  1244.     .prediv_offset = 11,
  1245.     .prediv_val = 3,
  1246.     .div3ck_mask = 0xE0000000,
  1247.     .div3ck_offset = 29,
  1248.     .div3ck_val = 2,
  1249.     .emac_val = 0x08,
  1250.     .upthr_val = 25,
  1251.     .dnthr_val = 9,
  1252.     .pncthr_val = 33,
  1253.     .upcnt_val = 10,
  1254.     .dncnt_val = 10,
  1255.     .delay_time = 80,
  1256. };
  1257.  
  1258. static void __init fixup_mxc_board(struct machine_desc *desc, struct tag *tags,
  1259.                    char **cmdline, struct meminfo *mi)
  1260. {
  1261. }
  1262.  
  1263. static int __init caam_setup(char *__unused)
  1264. {
  1265.     caam_enabled = 1;
  1266.     return 1;
  1267. }
  1268. early_param("caam", caam_setup);
  1269.  
  1270. static const struct imx_pcie_platform_data mx6_sabrelite_pcie_data __initconst = {
  1271.     .pcie_pwr_en    = -EINVAL,
  1272.     .pcie_rst   = -EINVAL,
  1273.     .pcie_wake_up   = -EINVAL,
  1274.     .pcie_dis   = -EINVAL,
  1275. };
  1276.  
  1277. /*!
  1278.  * Board specific initialization.
  1279.  */
  1280. static void __init mx6_sabrelite_board_init(void)
  1281. {
  1282.     int i;
  1283.     struct platform_device *voutdev;
  1284.    
  1285.     if (cpu_is_mx6q())
  1286.         mxc_iomux_v3_setup_multiple_pads(mx6q_sabrelite_pads,
  1287.                     ARRAY_SIZE(mx6q_sabrelite_pads));
  1288.     else
  1289.         mxc_iomux_v3_setup_multiple_pads(mx6dl_sabrelite_pads,
  1290.                     ARRAY_SIZE(mx6dl_sabrelite_pads));
  1291.  
  1292.     if (enet_to_gpio_6) {
  1293.         iomux_v3_cfg_t enet_gpio_pad =
  1294.             MX6Q_PAD_GPIO_6__ENET_IRQ_TO_GPIO_6;
  1295.         mxc_iomux_v3_setup_pad(enet_gpio_pad);
  1296.     }
  1297.    
  1298. #ifdef CONFIG_FEC_1588
  1299.     if (cpu_is_mx6q()) {   
  1300.         /* Set GPIO_16 input for IEEE-1588 ts_clk and RMII reference clock
  1301.         * For MX6 GPR1 bit21 meaning:
  1302.         * Bit21:       0 - GPIO_16 pad output
  1303.         *              1 - GPIO_16 pad input
  1304.         */
  1305.         mxc_iomux_set_gpr_register(1, 21, 1, 1);
  1306.     }
  1307. #endif
  1308.  
  1309.     gp_reg_id = sabrelite_dvfscore_data.reg_id;
  1310.     soc_reg_id = sabrelite_dvfscore_data.soc_id;
  1311.     pu_reg_id = sabrelite_dvfscore_data.pu_id;
  1312.     mx6q_sabrelite_init_uart();
  1313.  
  1314.     /*
  1315.      * MX6DL/Solo only supports single IPU
  1316.      * The following codes are used to change ipu id
  1317.      * and display id information for MX6DL/Solo. Then
  1318.      * register 1 IPU device and up to 2 displays for
  1319.      * MX6DL/Solo
  1320.      */
  1321.     if (cpu_is_mx6dl()) {
  1322.         ldb_data.ipu_id = 0;
  1323.         ldb_data.sec_ipu_id = 0;
  1324.     }
  1325.    
  1326.     imx6q_add_mxc_hdmi_core(&hdmi_core_data);
  1327.  
  1328.     imx6q_add_ipuv3(0, &ipu_data[0]);
  1329.     if (cpu_is_mx6q()) {
  1330.         imx6q_add_ipuv3(1, &ipu_data[1]);
  1331.         for (i = 0; i < ARRAY_SIZE(sabrelite_fb_data); i++)
  1332.             imx6q_add_ipuv3fb(i, &sabrelite_fb_data[i]);
  1333.     } else
  1334.         for (i = 0; i < 2 && i < ARRAY_SIZE(sabrelite_fb_data); i++)
  1335.             imx6q_add_ipuv3fb(i, &sabrelite_fb_data[i]);
  1336.  
  1337.     imx6q_add_vdoa();
  1338.     imx6q_add_lcdif(&lcdif_data);
  1339.     imx6q_add_ldb(&ldb_data);
  1340.     voutdev = imx6q_add_v4l2_output(0);
  1341.     if (vout_mem.res_msize && voutdev) {
  1342.         dma_declare_coherent_memory(&voutdev->dev,
  1343.                         vout_mem.res_mbase,
  1344.                         vout_mem.res_mbase,
  1345.                         vout_mem.res_msize,
  1346.                         (DMA_MEMORY_MAP |
  1347.                          DMA_MEMORY_EXCLUSIVE));
  1348.     }
  1349.     imx6q_add_v4l2_capture(0, &capture_data[0]);
  1350.     imx6q_add_v4l2_capture(1, &capture_data[1]);
  1351. //  imx6q_add_mipi_csi2(&mipi_csi2_pdata);
  1352.     imx6q_add_imx_snvs_rtc();
  1353.  
  1354.     if (1 == caam_enabled)
  1355.         imx6q_add_imx_caam();
  1356.  
  1357.     imx6q_add_imx_i2c(0, &mx6q_sabrelite_i2c_data);
  1358.     imx6q_add_imx_i2c(1, &mx6q_sabrelite_i2c_data);
  1359.     imx6q_add_imx_i2c(2, &mx6q_sabrelite_i2c_data);
  1360.     if (cpu_is_mx6q()) {
  1361.         i2c_register_board_info(0, mx6q_sk_i2c0_board_info,
  1362.                 ARRAY_SIZE(mx6q_sk_i2c0_board_info));
  1363.         i2c_register_board_info(1, mx6q_sk_i2c1_board_info,
  1364.                 ARRAY_SIZE(mx6q_sk_i2c1_board_info));
  1365.     } else {
  1366.         i2c_register_board_info(1, mx6dl_sk_i2c1_board_info,
  1367.                 ARRAY_SIZE(mx6dl_sk_i2c1_board_info));
  1368.     }
  1369.  
  1370.     /* SPI */
  1371.     if (cpu_is_mx6dl()) {
  1372.         mx6q_sabrelite_spi4_cs[0] = MX6DL_SK_ECSPI4_CS0;
  1373.     }
  1374.     imx6q_add_ecspi(0, &mx6q_sabrelite_spi1_data);
  1375.     imx6q_add_ecspi(3, &mx6q_sabrelite_spi4_data);
  1376.     spi_device_init();
  1377.  
  1378.     imx6q_add_mxc_hdmi(&hdmi_data);
  1379.  
  1380.     imx6q_add_anatop_thermal_imx(1, &mx6q_sabrelite_anatop_thermal_data);
  1381.  
  1382.     if (enet_to_gpio_6)
  1383.         /* Make sure the IOMUX_OBSRV_MUX1 is set to ENET_IRQ. */
  1384.         mxc_iomux_set_specialbits_register(
  1385.             IOMUX_OBSRV_MUX1_OFFSET,
  1386.             OBSRV_MUX1_ENET_IRQ,
  1387.             OBSRV_MUX1_MASK);
  1388.     else
  1389.         fec_data.gpio_irq = -1;
  1390.        
  1391.     if (cpu_is_mx6dl())
  1392.         fec_data.phy = PHY_INTERFACE_MODE_RMII;
  1393.     imx6_init_fec(fec_data);
  1394.     imx6q_add_pm_imx(0, &mx6q_sabrelite_pm_data);
  1395.     imx6q_add_sdhci_usdhc_imx(0, &mx6q_sabrelite_sd1_data);
  1396.     imx6q_add_sdhci_usdhc_imx(1, &mx6q_sabrelite_sd2_data);
  1397.     imx_add_viv_gpu(&imx6_gpu_data, &imx6q_gpu_pdata);
  1398.     imx6q_sabrelite_init_usb();
  1399.     if (cpu_is_mx6q()) {
  1400. #ifdef CONFIG_SATA_AHCI_PLATFORM
  1401.         imx6q_add_ahci(0, &mx6q_sabrelite_sata_data);
  1402. #else
  1403.         mx6q_sabrelite_sata_init(NULL,
  1404.             (void __iomem *)ioremap(MX6Q_SATA_BASE_ADDR, SZ_4K));
  1405. #endif
  1406.     }
  1407.     imx6q_add_vpu();
  1408.     imx6q_init_audio();
  1409.     platform_device_register(&sabrelite_vmmc_reg_devices);
  1410.     imx_asrc_data.asrc_core_clk = clk_get(NULL, "asrc_clk");
  1411.     imx_asrc_data.asrc_audio_clk = clk_get(NULL, "asrc_serial_clk");
  1412.     imx6q_add_asrc(&imx_asrc_data);
  1413.  
  1414.     imx6q_add_mxc_pwm(0);
  1415.     imx6q_add_mxc_pwm(1);
  1416.     imx6q_add_mxc_pwm(2);
  1417.     imx6q_add_mxc_pwm(3);
  1418.     imx6q_add_mxc_pwm_backlight(3, &mx6_sabrelite_pwm_backlight_data);
  1419.  
  1420.     imx6q_add_otp();
  1421.     imx6q_add_viim();
  1422.     imx6q_add_imx2_wdt(0, NULL);
  1423.     imx6q_add_dma();
  1424.    
  1425.     imx6q_add_gpmi(&mx6q_gpmi_nand_platform_data); 
  1426.  
  1427.     imx6q_add_dvfs_core(&sabrelite_dvfscore_data);
  1428.  
  1429.     imx6q_add_hdmi_soc();
  1430.     imx6q_add_hdmi_soc_dai();
  1431.  
  1432.     imx6q_add_flexcan0(&mx6q_sabrelite_flexcan0_pdata);
  1433.     imx6q_add_flexcan1(&mx6q_sabrelite_flexcan1_pdata);
  1434.  
  1435.     imx6q_add_busfreq();
  1436.  
  1437.     /* Add PCIe RC interface support */
  1438.     imx6q_add_pcie(&mx6_sabrelite_pcie_data);
  1439.  
  1440.     imx6q_add_perfmon(0);
  1441.     imx6q_add_perfmon(1);
  1442.     imx6q_add_perfmon(2);
  1443. }
  1444.  
  1445. extern void __iomem *twd_base;
  1446. static void __init mx6_sabrelite_timer_init(void)
  1447. {
  1448.     struct clk *uart_clk;
  1449. #ifdef CONFIG_LOCAL_TIMERS
  1450.     twd_base = ioremap(LOCAL_TWD_ADDR, SZ_256);
  1451.     BUG_ON(!twd_base);
  1452. #endif
  1453.     mx6_clocks_init(32768, 24000000, 0, 0);
  1454.  
  1455.     uart_clk = clk_get_sys("imx-uart.0", NULL);
  1456.     early_console_setup(UART1_BASE_ADDR, uart_clk);
  1457. }
  1458.  
  1459. static struct sys_timer mx6_sabrelite_timer = {
  1460.     .init   = mx6_sabrelite_timer_init,
  1461. };
  1462.  
  1463. static void __init mx6q_sabrelite_reserve(void)
  1464. {
  1465.     phys_addr_t phys;
  1466.  
  1467. #if defined(CONFIG_MXC_GPU_VIV) || defined(CONFIG_MXC_GPU_VIV_MODULE)
  1468.     if (imx6q_gpu_pdata.reserved_mem_size) {
  1469.         phys = memblock_alloc_base(imx6q_gpu_pdata.reserved_mem_size,
  1470.                        SZ_4K, SZ_1G);
  1471.         memblock_remove(phys, imx6q_gpu_pdata.reserved_mem_size);
  1472.         imx6q_gpu_pdata.reserved_mem_base = phys;
  1473.     }
  1474. #endif
  1475.     if (vout_mem.res_msize) {
  1476.         phys = memblock_alloc_base(vout_mem.res_msize,
  1477.                        SZ_4K, SZ_1G);
  1478.         memblock_remove(phys, vout_mem.res_msize);
  1479.         vout_mem.res_mbase = phys;
  1480.     }
  1481. }
  1482.  
  1483. /*
  1484.  * initialize __mach_desc_MX6Q_SABRELITE data structure.
  1485.  */
  1486. MACHINE_START(MX6Q_SABRELITE, "Freescale i.MX 6Quad Sabre-Lite Board")
  1487.     /* Maintainer: Freescale Semiconductor, Inc. */
  1488.     .boot_params = MX6_PHYS_OFFSET + 0x100,
  1489.     .fixup = fixup_mxc_board,
  1490.     .map_io = mx6_map_io,
  1491.     .init_irq = mx6_init_irq,
  1492.     .init_machine = mx6_sabrelite_board_init,
  1493.     .timer = &mx6_sabrelite_timer,
  1494.     .reserve = mx6q_sabrelite_reserve,
  1495. MACHINE_END
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