library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.NUMERIC_STD.ALL;

entity reg is
	generic (
	   	capacity	: natural := 4;
		write_delay : time    := 0 ns;
		z_delay 	: time    := 0 ns;
		x_delay 	: time    := 0 ns);

    port ( 	D : in std_logic_vector (capacity-1 downto 0);
			C : in std_logic;
			E : in std_logic;
           	Q : out std_logic_vector (capacity-1 downto 0));
end reg;

architecture behavioral of reg is
	signal tmp: std_logic_vector (capacity-1 downto 0) ;
begin

	z: process (E, tmp)
	begin

		if E = '1' then
			Q <= (others => 'Z') after z_delay;

		elsif E = '0' then
			Q <= tmp after z_delay;

		else
			Q <= (others => 'X') after z_delay;

		end if;

	end process z;


	r: process (C, D)

	begin

		if C = '0' then
			tmp <= D after write_delay;

		elsif C /= '1' then
			tmp <= (others => 'X') after x_delay;

		end if;

	end process r;

end behavioral;