[VHDL] ALU

entity ALU is
    port( CLK : in std_logic;
          A : in std_logic_vector(31 ownto 0);
          B : in std_logic_vector(31 downto 0);
          C : out std_logic_vector(31 downto 0);
          TYP_DZIALANIA : in std_logic_vector(2 downto 0) -- 1='+'; 2='-'; 3='*'; 4='and'; 5='or'
    );
end ALU;


architecture arch_ALU of ALU is
    process (CLK)
    begin
        if (CLK''event and CLK='1') then
            if (TYP_DZIALANIA = '001') then
                C <= A + B;
            elsif (TYP_DZIALANIA = '010') then
                C <= A - B;
            elsif (TYP_DZIALANIA = '011') then
                C <= A * B;
            elsif (TYP_DZIALANIA = '100') then
                C <= A and B;
            elsif (TYP_DZIALANIA = '101') then
                C <= A or B;
            end if;
        end if;
    end process;
end arch_ALU;